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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_flash.h 00004 * @author MCD Application Team 00005 * @brief Header file of FLASH HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file in 00013 * the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 ****************************************************************************** 00016 */ 00017 00018 /* Define to prevent recursive inclusion -------------------------------------*/ 00019 #ifndef STM32L4xx_HAL_FLASH_H 00020 #define STM32L4xx_HAL_FLASH_H 00021 00022 #ifdef __cplusplus 00023 extern "C" { 00024 #endif 00025 00026 /* Includes ------------------------------------------------------------------*/ 00027 #include "stm32l4xx_hal_def.h" 00028 00029 /** @addtogroup STM32L4xx_HAL_Driver 00030 * @{ 00031 */ 00032 00033 /** @addtogroup FLASH 00034 * @{ 00035 */ 00036 00037 /* Exported types ------------------------------------------------------------*/ 00038 /** @defgroup FLASH_Exported_Types FLASH Exported Types 00039 * @{ 00040 */ 00041 00042 /** 00043 * @brief FLASH Erase structure definition 00044 */ 00045 typedef struct 00046 { 00047 uint32_t TypeErase; /*!< Mass erase or page erase. 00048 This parameter can be a value of @ref FLASH_Type_Erase */ 00049 uint32_t Banks; /*!< Select bank to erase. 00050 This parameter must be a value of @ref FLASH_Banks 00051 (FLASH_BANK_BOTH should be used only for mass erase) */ 00052 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled 00053 This parameter must be a value between 0 and (max number of pages in the bank - 1) 00054 (eg : 255 for 1MB dual bank) */ 00055 uint32_t NbPages; /*!< Number of pages to be erased. 00056 This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ 00057 } FLASH_EraseInitTypeDef; 00058 00059 /** 00060 * @brief FLASH Option Bytes Program structure definition 00061 */ 00062 typedef struct 00063 { 00064 uint32_t OptionType; /*!< Option byte to be configured. 00065 This parameter can be a combination of the values of @ref FLASH_OB_Type */ 00066 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 00067 Only one WRP area could be programmed at the same time. 00068 This parameter can be value of @ref FLASH_OB_WRP_Area */ 00069 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 00070 This parameter must be a value between 0 and (max number of pages in the bank - 1) 00071 (eg : 25 for 1MB dual bank) */ 00072 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 00073 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ 00074 uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). 00075 This parameter can be a value of @ref FLASH_OB_Read_Protection */ 00076 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 00077 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 00078 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 00079 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 00080 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 00081 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 00082 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 00083 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, 00084 @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, 00085 @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */ 00086 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). 00087 This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) 00088 and @ref FLASH_OB_PCROP_RDP */ 00089 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). 00090 This parameter must be a value between begin and end of bank 00091 => Be careful of the bank swapping for the address */ 00092 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). 00093 This parameter must be a value between PCROP Start address and end of bank */ 00094 } FLASH_OBProgramInitTypeDef; 00095 00096 /** 00097 * @brief FLASH Procedure structure definition 00098 */ 00099 typedef enum 00100 { 00101 FLASH_PROC_NONE = 0, 00102 FLASH_PROC_PAGE_ERASE, 00103 FLASH_PROC_MASS_ERASE, 00104 FLASH_PROC_PROGRAM, 00105 FLASH_PROC_PROGRAM_LAST 00106 } FLASH_ProcedureTypeDef; 00107 00108 /** 00109 * @brief FLASH Cache structure definition 00110 */ 00111 typedef enum 00112 { 00113 FLASH_CACHE_DISABLED = 0, 00114 FLASH_CACHE_ICACHE_ENABLED, 00115 FLASH_CACHE_DCACHE_ENABLED, 00116 FLASH_CACHE_ICACHE_DCACHE_ENABLED 00117 } FLASH_CacheTypeDef; 00118 00119 /** 00120 * @brief FLASH handle Structure definition 00121 */ 00122 typedef struct 00123 { 00124 HAL_LockTypeDef Lock; /* FLASH locking object */ 00125 __IO uint32_t ErrorCode; /* FLASH error code */ 00126 __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ 00127 __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */ 00128 __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */ 00129 __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ 00130 __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ 00131 __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */ 00132 }FLASH_ProcessTypeDef; 00133 00134 /** 00135 * @} 00136 */ 00137 00138 /* Exported constants --------------------------------------------------------*/ 00139 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 00140 * @{ 00141 */ 00142 00143 /** @defgroup FLASH_Error FLASH Error 00144 * @{ 00145 */ 00146 #define HAL_FLASH_ERROR_NONE 0x00000000U 00147 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR 00148 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR 00149 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR 00150 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR 00151 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR 00152 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR 00153 #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR 00154 #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR 00155 #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR 00156 #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR 00157 #define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC 00158 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD 00159 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ 00160 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00161 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \ 00162 defined (STM32L4S7xx) || defined (STM32L4S9xx) 00163 #define HAL_FLASH_ERROR_PEMPTY FLASH_FLAG_PEMPTY 00164 #endif 00165 /** 00166 * @} 00167 */ 00168 00169 /** @defgroup FLASH_Type_Erase FLASH Erase Type 00170 * @{ 00171 */ 00172 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/ 00173 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/ 00174 /** 00175 * @} 00176 */ 00177 00178 /** @defgroup FLASH_Banks FLASH Banks 00179 * @{ 00180 */ 00181 #define FLASH_BANK_1 ((uint32_t)0x01) /*!< Bank 1 */ 00182 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00183 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 00184 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00185 #define FLASH_BANK_2 ((uint32_t)0x02) /*!< Bank 2 */ 00186 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ 00187 #else 00188 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1)) /*!< Bank 1 */ 00189 #endif 00190 /** 00191 * @} 00192 */ 00193 00194 00195 /** @defgroup FLASH_Type_Program FLASH Program Type 00196 * @{ 00197 */ 00198 #define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00) /*!<Program a double-word (64-bit) at a specified address.*/ 00199 #define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01) /*!<Fast program a 32 row double-word (64-bit) at a specified address. 00200 And another 32 row double-word (64-bit) will be programmed */ 00201 #define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02) /*!<Fast program a 32 row double-word (64-bit) at a specified address. 00202 And this is the last 32 row double-word (64-bit) programmed */ 00203 /** 00204 * @} 00205 */ 00206 00207 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type 00208 * @{ 00209 */ 00210 #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */ 00211 #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */ 00212 #define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */ 00213 #define OPTIONBYTE_PCROP ((uint32_t)0x08) /*!< PCROP option byte configuration */ 00214 /** 00215 * @} 00216 */ 00217 00218 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area 00219 * @{ 00220 */ 00221 #define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /*!< Flash Bank 1 Area A */ 00222 #define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /*!< Flash Bank 1 Area B */ 00223 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00224 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 00225 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00226 #define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /*!< Flash Bank 2 Area A */ 00227 #define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /*!< Flash Bank 2 Area B */ 00228 #endif 00229 /** 00230 * @} 00231 */ 00232 00233 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection 00234 * @{ 00235 */ 00236 #define OB_RDP_LEVEL_0 ((uint32_t)0xAA) 00237 #define OB_RDP_LEVEL_1 ((uint32_t)0xBB) 00238 #define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2 00239 it's no more possible to go back to level 1 or 0 */ 00240 /** 00241 * @} 00242 */ 00243 00244 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type 00245 * @{ 00246 */ 00247 #define OB_USER_BOR_LEV ((uint32_t)0x0001) /*!< BOR reset Level */ 00248 #define OB_USER_nRST_STOP ((uint32_t)0x0002) /*!< Reset generated when entering the stop mode */ 00249 #define OB_USER_nRST_STDBY ((uint32_t)0x0004) /*!< Reset generated when entering the standby mode */ 00250 #define OB_USER_IWDG_SW ((uint32_t)0x0008) /*!< Independent watchdog selection */ 00251 #define OB_USER_IWDG_STOP ((uint32_t)0x0010) /*!< Independent watchdog counter freeze in stop mode */ 00252 #define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /*!< Independent watchdog counter freeze in standby mode */ 00253 #define OB_USER_WWDG_SW ((uint32_t)0x0040) /*!< Window watchdog selection */ 00254 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00255 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 00256 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00257 #define OB_USER_BFB2 ((uint32_t)0x0080) /*!< Dual-bank boot */ 00258 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00259 #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 1MB or 512kB Flash memory devices */ 00260 #else 00261 #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 512KB or 256KB Flash memory devices */ 00262 #endif 00263 #endif 00264 #define OB_USER_nBOOT1 ((uint32_t)0x0200) /*!< Boot configuration */ 00265 #define OB_USER_SRAM2_PE ((uint32_t)0x0400) /*!< SRAM2 parity check enable */ 00266 #define OB_USER_SRAM2_RST ((uint32_t)0x0800) /*!< SRAM2 Erase when system reset */ 00267 #define OB_USER_nRST_SHDW ((uint32_t)0x1000) /*!< Reset generated when entering the shutdown mode */ 00268 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ 00269 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 00270 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 00271 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00272 #define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /*!< Software BOOT0 */ 00273 #define OB_USER_nBOOT0 ((uint32_t)0x4000) /*!< nBOOT0 option bit */ 00274 #endif 00275 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00276 #define OB_USER_DBANK ((uint32_t)0x8000) /*!< Single bank with 128-bits data or two banks with 64-bits data */ 00277 #endif 00278 /** 00279 * @} 00280 */ 00281 00282 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 00283 * @{ 00284 */ 00285 #define OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0) /*!< Reset level threshold is around 1.7V */ 00286 #define OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.0V */ 00287 #define OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2) /*!< Reset level threshold is around 2.2V */ 00288 #define OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3) /*!< Reset level threshold is around 2.5V */ 00289 #define OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4) /*!< Reset level threshold is around 2.8V */ 00290 /** 00291 * @} 00292 */ 00293 00294 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 00295 * @{ 00296 */ 00297 #define OB_STOP_RST ((uint32_t)0x0000) /*!< Reset generated when entering the stop mode */ 00298 #define OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP) /*!< No reset generated when entering the stop mode */ 00299 /** 00300 * @} 00301 */ 00302 00303 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 00304 * @{ 00305 */ 00306 #define OB_STANDBY_RST ((uint32_t)0x0000) /*!< Reset generated when entering the standby mode */ 00307 #define OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY) /*!< No reset generated when entering the standby mode */ 00308 /** 00309 * @} 00310 */ 00311 00312 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 00313 * @{ 00314 */ 00315 #define OB_SHUTDOWN_RST ((uint32_t)0x0000) /*!< Reset generated when entering the shutdown mode */ 00316 #define OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW) /*!< No reset generated when entering the shutdown mode */ 00317 /** 00318 * @} 00319 */ 00320 00321 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 00322 * @{ 00323 */ 00324 #define OB_IWDG_HW ((uint32_t)0x00000) /*!< Hardware independent watchdog */ 00325 #define OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW) /*!< Software independent watchdog */ 00326 /** 00327 * @} 00328 */ 00329 00330 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 00331 * @{ 00332 */ 00333 #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Stop mode */ 00334 #define OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP) /*!< Independent watchdog counter is running in Stop mode */ 00335 /** 00336 * @} 00337 */ 00338 00339 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 00340 * @{ 00341 */ 00342 #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Standby mode */ 00343 #define OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY) /*!< Independent watchdog counter is running in Standby mode */ 00344 /** 00345 * @} 00346 */ 00347 00348 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 00349 * @{ 00350 */ 00351 #define OB_WWDG_HW ((uint32_t)0x00000) /*!< Hardware window watchdog */ 00352 #define OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW) /*!< Software window watchdog */ 00353 /** 00354 * @} 00355 */ 00356 00357 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00358 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 00359 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00360 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode 00361 * @{ 00362 */ 00363 #define OB_BFB2_DISABLE ((uint32_t)0x000000) /*!< Dual-bank boot disable */ 00364 #define OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2) /*!< Dual-bank boot enable */ 00365 /** 00366 * @} 00367 */ 00368 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00369 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 00370 * @{ 00371 */ 00372 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 1 MB/512 kB Single-bank Flash */ 00373 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DB1M) /*!< 1 MB/512 kB Dual-bank Flash */ 00374 /** 00375 * @} 00376 */ 00377 #else 00378 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 00379 * @{ 00380 */ 00381 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 256 KB/512 KB Single-bank Flash */ 00382 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK) /*!< 256 KB/512 KB Dual-bank Flash */ 00383 /** 00384 * @} 00385 */ 00386 #endif 00387 #endif 00388 00389 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00390 /** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type 00391 * @{ 00392 */ 00393 #define OB_DBANK_128_BITS ((uint32_t)0x000000) /*!< Single-bank with 128-bits data */ 00394 #define OB_DBANK_64_BITS ((uint32_t)FLASH_OPTR_DBANK) /*!< Dual-bank with 64-bits data */ 00395 #endif 00396 /** 00397 * @} 00398 */ 00399 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type 00400 * @{ 00401 */ 00402 #define OB_BOOT1_SRAM ((uint32_t)0x000000) /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */ 00403 #define OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1) /*!< System memory is selected as boot space (if BOOT0=1) */ 00404 /** 00405 * @} 00406 */ 00407 00408 /** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type 00409 * @{ 00410 */ 00411 #define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000) /*!< SRAM2 parity check enable */ 00412 #define OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE) /*!< SRAM2 parity check disable */ 00413 /** 00414 * @} 00415 */ 00416 00417 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type 00418 * @{ 00419 */ 00420 #define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000) /*!< SRAM2 erased when a system reset occurs */ 00421 #define OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST) /*!< SRAM2 is not erased when a system reset occurs */ 00422 /** 00423 * @} 00424 */ 00425 00426 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ 00427 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 00428 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 00429 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00430 /** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 00431 * @{ 00432 */ 00433 #define OB_BOOT0_FROM_OB ((uint32_t)0x0000000) /*!< BOOT0 taken from the option bit nBOOT0 */ 00434 #define OB_BOOT0_FROM_PIN ((uint32_t)FLASH_OPTR_nSWBOOT0) /*!< BOOT0 taken from PH3/BOOT0 pin */ 00435 /** 00436 * @} 00437 */ 00438 00439 /** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 00440 * @{ 00441 */ 00442 #define OB_BOOT0_RESET ((uint32_t)0x0000000) /*!< nBOOT0 = 0 */ 00443 #define OB_BOOT0_SET ((uint32_t)FLASH_OPTR_nBOOT0) /*!< nBOOT0 = 1 */ 00444 /** 00445 * @} 00446 */ 00447 #endif 00448 00449 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type 00450 * @{ 00451 */ 00452 #define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000) /*!< PCROP area is not erased when the RDP level 00453 is decreased from Level 1 to Level 0 */ 00454 #define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is 00455 decreased from Level 1 to Level 0 (full mass erase) */ 00456 /** 00457 * @} 00458 */ 00459 00460 /** @defgroup FLASH_Latency FLASH Latency 00461 * @{ 00462 */ 00463 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 00464 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 00465 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 00466 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 00467 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 00468 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00469 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ 00470 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ 00471 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ 00472 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ 00473 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ 00474 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ 00475 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ 00476 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ 00477 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ 00478 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ 00479 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ 00480 #endif 00481 /** 00482 * @} 00483 */ 00484 00485 /** @defgroup FLASH_Keys FLASH Keys 00486 * @{ 00487 */ 00488 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 00489 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 00490 to unlock the FLASH registers access */ 00491 00492 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ 00493 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 00494 to unlock the RUN_PD bit in FLASH_ACR */ 00495 00496 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 00497 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 00498 to allow option bytes operations */ 00499 /** 00500 * @} 00501 */ 00502 00503 /** @defgroup FLASH_Flags FLASH Flags Definition 00504 * @{ 00505 */ 00506 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */ 00507 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */ 00508 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */ 00509 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */ 00510 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */ 00511 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ 00512 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */ 00513 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */ 00514 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */ 00515 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */ 00516 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ 00517 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ 00518 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ 00519 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 00520 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \ 00521 defined (STM32L4S7xx) || defined (STM32L4S9xx) 00522 #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */ 00523 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 00524 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 00525 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 00526 FLASH_FLAG_OPTVERR | FLASH_FLAG_PEMPTY) 00527 #else 00528 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 00529 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 00530 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 00531 FLASH_FLAG_OPTVERR) 00532 #endif 00533 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \ 00534 defined (STM32L4S7xx) || defined (STM32L4S9xx) 00535 #define FLASH_FLAG_ECCC (FLASH_ECCR_ECCC | FLASH_ECCR_ECCC2) /*!< FLASH ECC correction */ 00536 #define FLASH_FLAG_ECCD (FLASH_ECCR_ECCD | FLASH_ECCR_ECCD2) /*!< FLASH ECC detection */ 00537 #else 00538 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 00539 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 00540 #endif 00541 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) 00542 00543 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 00544 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 00545 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 00546 FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCR_ERRORS) 00547 /** 00548 * @} 00549 */ 00550 00551 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition 00552 * @brief FLASH Interrupt definition 00553 * @{ 00554 */ 00555 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ 00556 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */ 00557 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/ 00558 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 00559 /** 00560 * @} 00561 */ 00562 00563 /* Exported macros -----------------------------------------------------------*/ 00564 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 00565 * @brief macros to control FLASH features 00566 * @{ 00567 */ 00568 00569 /** 00570 * @brief Set the FLASH Latency. 00571 * @param __LATENCY__ FLASH Latency 00572 * This parameter can be one of the following values : 00573 * @arg FLASH_LATENCY_0: FLASH Zero wait state 00574 * @arg FLASH_LATENCY_1: FLASH One wait state 00575 * @arg FLASH_LATENCY_2: FLASH Two wait states 00576 * @arg FLASH_LATENCY_3: FLASH Three wait states 00577 * @arg FLASH_LATENCY_4: FLASH Four wait states 00578 * @retval None 00579 */ 00580 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) 00581 00582 /** 00583 * @brief Get the FLASH Latency. 00584 * @retval FLASH Latency 00585 * This parameter can be one of the following values : 00586 * @arg FLASH_LATENCY_0: FLASH Zero wait state 00587 * @arg FLASH_LATENCY_1: FLASH One wait state 00588 * @arg FLASH_LATENCY_2: FLASH Two wait states 00589 * @arg FLASH_LATENCY_3: FLASH Three wait states 00590 * @arg FLASH_LATENCY_4: FLASH Four wait states 00591 */ 00592 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 00593 00594 /** 00595 * @brief Enable the FLASH prefetch buffer. 00596 * @retval None 00597 */ 00598 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 00599 00600 /** 00601 * @brief Disable the FLASH prefetch buffer. 00602 * @retval None 00603 */ 00604 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 00605 00606 /** 00607 * @brief Enable the FLASH instruction cache. 00608 * @retval none 00609 */ 00610 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) 00611 00612 /** 00613 * @brief Disable the FLASH instruction cache. 00614 * @retval none 00615 */ 00616 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) 00617 00618 /** 00619 * @brief Enable the FLASH data cache. 00620 * @retval none 00621 */ 00622 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) 00623 00624 /** 00625 * @brief Disable the FLASH data cache. 00626 * @retval none 00627 */ 00628 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) 00629 00630 /** 00631 * @brief Reset the FLASH instruction Cache. 00632 * @note This function must be used only when the Instruction Cache is disabled. 00633 * @retval None 00634 */ 00635 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 00636 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 00637 } while (0) 00638 00639 /** 00640 * @brief Reset the FLASH data Cache. 00641 * @note This function must be used only when the data Cache is disabled. 00642 * @retval None 00643 */ 00644 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 00645 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 00646 } while (0) 00647 00648 /** 00649 * @brief Enable the FLASH power down during Low-power run mode. 00650 * @note Writing this bit to 0 this bit, automatically the keys are 00651 * loss and a new unlock sequence is necessary to re-write it to 1. 00652 */ 00653 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 00654 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 00655 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 00656 } while (0) 00657 00658 /** 00659 * @brief Disable the FLASH power down during Low-power run mode. 00660 * @note Writing this bit to 0 this bit, automatically the keys are 00661 * loss and a new unlock sequence is necessary to re-write it to 1. 00662 */ 00663 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 00664 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 00665 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 00666 } while (0) 00667 00668 /** 00669 * @brief Enable the FLASH power down during Low-Power sleep mode 00670 * @retval none 00671 */ 00672 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 00673 00674 /** 00675 * @brief Disable the FLASH power down during Low-Power sleep mode 00676 * @retval none 00677 */ 00678 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 00679 00680 /** 00681 * @} 00682 */ 00683 00684 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 00685 * @brief macros to handle FLASH interrupts 00686 * @{ 00687 */ 00688 00689 /** 00690 * @brief Enable the specified FLASH interrupt. 00691 * @param __INTERRUPT__ FLASH interrupt 00692 * This parameter can be any combination of the following values: 00693 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 00694 * @arg FLASH_IT_OPERR: Error Interrupt 00695 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt 00696 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 00697 * @retval none 00698 */ 00699 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 00700 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 00701 } while(0) 00702 00703 /** 00704 * @brief Disable the specified FLASH interrupt. 00705 * @param __INTERRUPT__ FLASH interrupt 00706 * This parameter can be any combination of the following values: 00707 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 00708 * @arg FLASH_IT_OPERR: Error Interrupt 00709 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt 00710 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 00711 * @retval none 00712 */ 00713 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 00714 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 00715 } while(0) 00716 00717 /** 00718 * @brief Check whether the specified FLASH flag is set or not. 00719 * @param __FLAG__ specifies the FLASH flag to check. 00720 * This parameter can be one of the following values: 00721 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 00722 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 00723 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 00724 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 00725 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 00726 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 00727 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 00728 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag 00729 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag 00730 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag 00731 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag 00732 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 00733 * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices) 00734 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 00735 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 00736 * @retval The new state of FLASH_FLAG (SET or RESET). 00737 */ 00738 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 00739 (READ_BIT(FLASH->ECCR, (__FLAG__)) != 0U) : \ 00740 (READ_BIT(FLASH->SR, (__FLAG__)) != 0U)) 00741 00742 /** 00743 * @brief Clear the FLASH's pending flags. 00744 * @param __FLAG__ specifies the FLASH flags to clear. 00745 * This parameter can be any combination of the following values: 00746 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 00747 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 00748 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 00749 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 00750 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 00751 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 00752 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 00753 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag 00754 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag 00755 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag 00756 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag 00757 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 00758 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 00759 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 00760 * @retval None 00761 */ 00762 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 00763 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 00764 } while(0) 00765 /** 00766 * @} 00767 */ 00768 00769 /* Include FLASH HAL Extended module */ 00770 #include "stm32l4xx_hal_flash_ex.h" 00771 #include "stm32l4xx_hal_flash_ramfunc.h" 00772 00773 /* Exported functions --------------------------------------------------------*/ 00774 /** @addtogroup FLASH_Exported_Functions 00775 * @{ 00776 */ 00777 00778 /* Program operation functions ***********************************************/ 00779 /** @addtogroup FLASH_Exported_Functions_Group1 00780 * @{ 00781 */ 00782 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 00783 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 00784 /* FLASH IRQ handler method */ 00785 void HAL_FLASH_IRQHandler(void); 00786 /* Callbacks in non blocking modes */ 00787 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 00788 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 00789 /** 00790 * @} 00791 */ 00792 00793 /* Peripheral Control functions **********************************************/ 00794 /** @addtogroup FLASH_Exported_Functions_Group2 00795 * @{ 00796 */ 00797 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 00798 HAL_StatusTypeDef HAL_FLASH_Lock(void); 00799 /* Option bytes control */ 00800 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 00801 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 00802 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 00803 /** 00804 * @} 00805 */ 00806 00807 /* Peripheral State functions ************************************************/ 00808 /** @addtogroup FLASH_Exported_Functions_Group3 00809 * @{ 00810 */ 00811 uint32_t HAL_FLASH_GetError(void); 00812 /** 00813 * @} 00814 */ 00815 00816 /** 00817 * @} 00818 */ 00819 00820 /* Private variables ---------------------------------------------------------*/ 00821 /** @addtogroup FLASH_Private_Variables FLASH Private Variables 00822 * @{ 00823 */ 00824 extern FLASH_ProcessTypeDef pFlash; 00825 /** 00826 * @} 00827 */ 00828 00829 /* Private function ----------------------------------------------------------*/ 00830 /** @addtogroup FLASH_Private_Functions FLASH Private Functions 00831 * @{ 00832 */ 00833 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 00834 /** 00835 * @} 00836 */ 00837 00838 /* Private constants --------------------------------------------------------*/ 00839 /** @defgroup FLASH_Private_Constants FLASH Private Constants 00840 * @{ 00841 */ 00842 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00843 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 00844 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00845 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1U) 00846 #else 00847 #define FLASH_BANK_SIZE (FLASH_SIZE) 00848 #endif 00849 00850 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00851 #define FLASH_PAGE_SIZE ((uint32_t)0x1000) 00852 #define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000) 00853 #else 00854 #define FLASH_PAGE_SIZE ((uint32_t)0x800) 00855 #endif 00856 00857 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ 00858 /** 00859 * @} 00860 */ 00861 00862 /* Private macros ------------------------------------------------------------*/ 00863 /** @defgroup FLASH_Private_Macros FLASH Private Macros 00864 * @{ 00865 */ 00866 00867 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 00868 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 00869 00870 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00871 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 00872 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00873 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ 00874 ((BANK) == FLASH_BANK_2) || \ 00875 ((BANK) == FLASH_BANK_BOTH)) 00876 00877 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ 00878 ((BANK) == FLASH_BANK_2)) 00879 #else 00880 #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) 00881 00882 #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) 00883 #endif 00884 00885 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ 00886 ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ 00887 ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) 00888 00889 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00890 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU))) 00891 #else 00892 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? \ 00893 ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \ 00894 ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \ 00895 ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \ 00896 ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU))))))) 00897 #endif 00898 00899 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU)) 00900 00901 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) 00902 00903 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00904 #define IS_FLASH_PAGE(PAGE) ((PAGE) < 256U) 00905 #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) 00906 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? ((PAGE) < 256U) : \ 00907 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 128U) : \ 00908 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 64U) : \ 00909 ((PAGE) < 256U))))) 00910 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 00911 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 256U) : \ 00912 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ 00913 ((PAGE) < 256U)))) 00914 #else 00915 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ 00916 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? ((PAGE) < 64U) : \ 00917 ((PAGE) < 128U)))) 00918 #endif 00919 00920 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) 00921 00922 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00923 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 00924 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00925 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ 00926 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) 00927 #else 00928 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) 00929 #endif 00930 00931 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 00932 ((LEVEL) == OB_RDP_LEVEL_1)/* ||\ 00933 ((LEVEL) == OB_RDP_LEVEL_2)*/) 00934 00935 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00936 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFFU) && ((TYPE) != 0U)) 00937 #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 00938 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFFU) && ((TYPE) != 0U)) 00939 #else 00940 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7FU) && ((TYPE) != 0U) && (((TYPE)&0x0180U) == 0U)) 00941 #endif 00942 00943 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ 00944 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ 00945 ((LEVEL) == OB_BOR_LEVEL_4)) 00946 00947 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 00948 00949 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 00950 00951 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) 00952 00953 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 00954 00955 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) 00956 00957 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) 00958 00959 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 00960 00961 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00962 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 00963 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00964 #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) 00965 00966 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) 00967 #endif 00968 00969 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00970 #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) 00971 #endif 00972 00973 #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) 00974 00975 #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) 00976 00977 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 00978 00979 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ 00980 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 00981 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 00982 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00983 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) 00984 00985 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET)) 00986 #endif 00987 00988 #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) 00989 00990 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00991 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ 00992 ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ 00993 ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ 00994 ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ 00995 ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ 00996 ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ 00997 ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ 00998 ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) 00999 #else 01000 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ 01001 ((LATENCY) == FLASH_LATENCY_1) || \ 01002 ((LATENCY) == FLASH_LATENCY_2) || \ 01003 ((LATENCY) == FLASH_LATENCY_3) || \ 01004 ((LATENCY) == FLASH_LATENCY_4)) 01005 #endif 01006 /** 01007 * @} 01008 */ 01009 01010 /** 01011 * @} 01012 */ 01013 01014 /** 01015 * @} 01016 */ 01017 01018 /** 01019 * @} 01020 */ 01021 01022 #ifdef __cplusplus 01023 } 01024 #endif 01025 01026 #endif /* STM32L4xx_HAL_FLASH_H */ 01027
1.7.6.1