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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_nand.h 00004 * @author MCD Application Team 00005 * @brief Header file of NAND HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_NAND_H 00021 #define STM32L4xx_HAL_NAND_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 #if defined(FMC_BANK3) 00028 00029 /* Includes ------------------------------------------------------------------*/ 00030 #include "stm32l4xx_ll_fmc.h" 00031 00032 /** @addtogroup STM32L4xx_HAL_Driver 00033 * @{ 00034 */ 00035 00036 /** @addtogroup NAND 00037 * @{ 00038 */ 00039 00040 /* Exported typedef ----------------------------------------------------------*/ 00041 /* Exported types ------------------------------------------------------------*/ 00042 /** @defgroup NAND_Exported_Types NAND Exported Types 00043 * @{ 00044 */ 00045 00046 /** 00047 * @brief HAL NAND State structures definition 00048 */ 00049 typedef enum 00050 { 00051 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ 00052 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ 00053 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ 00054 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ 00055 } HAL_NAND_StateTypeDef; 00056 00057 /** 00058 * @brief NAND Memory electronic signature Structure definition 00059 */ 00060 typedef struct 00061 { 00062 /*<! NAND memory electronic signature maker and device IDs */ 00063 00064 uint8_t Maker_Id; 00065 00066 uint8_t Device_Id; 00067 00068 uint8_t Third_Id; 00069 00070 uint8_t Fourth_Id; 00071 } NAND_IDTypeDef; 00072 00073 /** 00074 * @brief NAND Memory address Structure definition 00075 */ 00076 typedef struct 00077 { 00078 uint16_t Page; /*!< NAND memory Page address */ 00079 00080 uint16_t Plane; /*!< NAND memory Zone address */ 00081 00082 uint16_t Block; /*!< NAND memory Block address */ 00083 00084 } NAND_AddressTypeDef; 00085 00086 /** 00087 * @brief NAND Memory info Structure definition 00088 */ 00089 typedef struct 00090 { 00091 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes 00092 for 8 bits addressing or words for 16 bits addressing */ 00093 00094 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes 00095 for 8 bits addressing or words for 16 bits addressing */ 00096 00097 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ 00098 00099 uint32_t BlockNbr; /*!< NAND memory number of total blocks */ 00100 00101 uint32_t PlaneNbr; /*!< NAND memory number of planes */ 00102 00103 uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ 00104 00105 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This 00106 parameter is mandatory for some NAND parts after the read 00107 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. 00108 Example: Toshiba THTH58BYG3S0HBAI6. 00109 This parameter could be ENABLE or DISABLE 00110 Please check the Read Mode sequnece in the NAND device datasheet */ 00111 } NAND_DeviceConfigTypeDef; 00112 00113 /** 00114 * @brief NAND handle Structure definition 00115 */ 00116 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00117 typedef struct __NAND_HandleTypeDef 00118 #else 00119 typedef struct 00120 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00121 { 00122 FMC_NAND_TypeDef *Instance; /*!< Register base address */ 00123 00124 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ 00125 00126 HAL_LockTypeDef Lock; /*!< NAND locking object */ 00127 00128 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ 00129 00130 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ 00131 00132 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00133 void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ 00134 void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ 00135 void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ 00136 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00137 } NAND_HandleTypeDef; 00138 00139 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00140 /** 00141 * @brief HAL NAND Callback ID enumeration definition 00142 */ 00143 typedef enum 00144 { 00145 HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ 00146 HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ 00147 HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ 00148 } HAL_NAND_CallbackIDTypeDef; 00149 00150 /** 00151 * @brief HAL NAND Callback pointer definition 00152 */ 00153 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); 00154 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00155 00156 /** 00157 * @} 00158 */ 00159 00160 /* Exported constants --------------------------------------------------------*/ 00161 /* Exported macro ------------------------------------------------------------*/ 00162 /** @defgroup NAND_Exported_Macros NAND Exported Macros 00163 * @{ 00164 */ 00165 00166 /** @brief Reset NAND handle state 00167 * @param __HANDLE__ specifies the NAND handle. 00168 * @retval None 00169 */ 00170 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00171 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \ 00172 (__HANDLE__)->State = HAL_NAND_STATE_RESET; \ 00173 (__HANDLE__)->MspInitCallback = NULL; \ 00174 (__HANDLE__)->MspDeInitCallback = NULL; \ 00175 } while(0) 00176 #else 00177 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) 00178 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00179 00180 /** 00181 * @} 00182 */ 00183 00184 /* Exported functions --------------------------------------------------------*/ 00185 /** @addtogroup NAND_Exported_Functions NAND Exported Functions 00186 * @{ 00187 */ 00188 00189 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 00190 * @{ 00191 */ 00192 00193 /* Initialization/de-initialization functions ********************************/ 00194 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, 00195 FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); 00196 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); 00197 00198 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); 00199 00200 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); 00201 00202 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); 00203 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); 00204 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); 00205 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); 00206 00207 /** 00208 * @} 00209 */ 00210 00211 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 00212 * @{ 00213 */ 00214 00215 /* IO operation functions ****************************************************/ 00216 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); 00217 00218 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, 00219 uint32_t NumPageToRead); 00220 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, 00221 uint32_t NumPageToWrite); 00222 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00223 uint8_t *pBuffer, uint32_t NumSpareAreaToRead); 00224 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00225 uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); 00226 00227 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, 00228 uint32_t NumPageToRead); 00229 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, 00230 uint32_t NumPageToWrite); 00231 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00232 uint16_t *pBuffer, uint32_t NumSpareAreaToRead); 00233 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00234 uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); 00235 00236 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 00237 00238 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 00239 00240 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00241 /* NAND callback registering/unregistering */ 00242 HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, 00243 pNAND_CallbackTypeDef pCallback); 00244 HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); 00245 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00246 00247 /** 00248 * @} 00249 */ 00250 00251 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 00252 * @{ 00253 */ 00254 00255 /* NAND Control functions ****************************************************/ 00256 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); 00257 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); 00258 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); 00259 00260 /** 00261 * @} 00262 */ 00263 00264 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 00265 * @{ 00266 */ 00267 /* NAND State functions *******************************************************/ 00268 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); 00269 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); 00270 /** 00271 * @} 00272 */ 00273 00274 /** 00275 * @} 00276 */ 00277 00278 /* Private types -------------------------------------------------------------*/ 00279 /* Private variables ---------------------------------------------------------*/ 00280 /* Private constants ---------------------------------------------------------*/ 00281 /** @defgroup NAND_Private_Constants NAND Private Constants 00282 * @{ 00283 */ 00284 #define NAND_DEVICE 0x80000000UL 00285 #define NAND_WRITE_TIMEOUT 0x01000000UL 00286 00287 #define CMD_AREA (1UL<<16U) /* A16 = CLE high */ 00288 #define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ 00289 00290 #define NAND_CMD_AREA_A ((uint8_t)0x00) 00291 #define NAND_CMD_AREA_B ((uint8_t)0x01) 00292 #define NAND_CMD_AREA_C ((uint8_t)0x50) 00293 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) 00294 00295 #define NAND_CMD_WRITE0 ((uint8_t)0x80) 00296 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) 00297 #define NAND_CMD_ERASE0 ((uint8_t)0x60) 00298 #define NAND_CMD_ERASE1 ((uint8_t)0xD0) 00299 #define NAND_CMD_READID ((uint8_t)0x90) 00300 #define NAND_CMD_STATUS ((uint8_t)0x70) 00301 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) 00302 #define NAND_CMD_RESET ((uint8_t)0xFF) 00303 00304 /* NAND memory status */ 00305 #define NAND_VALID_ADDRESS 0x00000100UL 00306 #define NAND_INVALID_ADDRESS 0x00000200UL 00307 #define NAND_TIMEOUT_ERROR 0x00000400UL 00308 #define NAND_BUSY 0x00000000UL 00309 #define NAND_ERROR 0x00000001UL 00310 #define NAND_READY 0x00000040UL 00311 /** 00312 * @} 00313 */ 00314 00315 /* Private macros ------------------------------------------------------------*/ 00316 /** @defgroup NAND_Private_Macros NAND Private Macros 00317 * @{ 00318 */ 00319 00320 /** 00321 * @brief NAND memory address computation. 00322 * @param __ADDRESS__ NAND memory address. 00323 * @param __HANDLE__ NAND handle. 00324 * @retval NAND Raw address value 00325 */ 00326 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ 00327 (((__ADDRESS__)->Block + \ 00328 (((__ADDRESS__)->Plane) * \ 00329 ((__HANDLE__)->Config.PlaneSize))) * \ 00330 ((__HANDLE__)->Config.BlockSize))) 00331 00332 /** 00333 * @brief NAND memory Column address computation. 00334 * @param __HANDLE__ NAND handle. 00335 * @retval NAND Raw address value 00336 */ 00337 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) 00338 00339 /** 00340 * @brief NAND memory address cycling. 00341 * @param __ADDRESS__ NAND memory address. 00342 * @retval NAND address cycling value. 00343 */ 00344 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ 00345 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ 00346 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ 00347 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ 00348 00349 /** 00350 * @brief NAND memory Columns cycling. 00351 * @param __ADDRESS__ NAND memory address. 00352 * @retval NAND Column address cycling value. 00353 */ 00354 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ 00355 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ 00356 00357 /** 00358 * @} 00359 */ 00360 00361 /** 00362 * @} 00363 */ 00364 00365 /** 00366 * @} 00367 */ 00368 00369 /** 00370 * @} 00371 */ 00372 00373 #endif /* FMC_BANK3 */ 00374 00375 #ifdef __cplusplus 00376 } 00377 #endif 00378 00379 #endif /* STM32L4xx_HAL_NAND_H */
1.7.6.1