STM32L443xx HAL User Manual
stm32l4xx_hal_nor.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_nor.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of NOR HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32L4xx_HAL_NOR_H
00021 #define STM32L4xx_HAL_NOR_H
00022 
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026 
00027 #if defined(FMC_BANK1)
00028 
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32l4xx_ll_fmc.h"
00031 
00032 /** @addtogroup STM32L4xx_HAL_Driver
00033   * @{
00034   */
00035 
00036 /** @addtogroup NOR
00037   * @{
00038   */
00039 
00040 /* Exported typedef ----------------------------------------------------------*/
00041 /** @defgroup NOR_Exported_Types NOR Exported Types
00042   * @{
00043   */
00044 
00045 /**
00046   * @brief  HAL SRAM State structures definition
00047   */
00048 typedef enum
00049 {
00050   HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
00051   HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
00052   HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
00053   HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
00054   HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */
00055 } HAL_NOR_StateTypeDef;
00056 
00057 /**
00058   * @brief  FMC NOR Status typedef
00059   */
00060 typedef enum
00061 {
00062   HAL_NOR_STATUS_SUCCESS  = 0U,
00063   HAL_NOR_STATUS_ONGOING,
00064   HAL_NOR_STATUS_ERROR,
00065   HAL_NOR_STATUS_TIMEOUT
00066 } HAL_NOR_StatusTypeDef;
00067 
00068 /**
00069   * @brief  FMC NOR ID typedef
00070   */
00071 typedef struct
00072 {
00073   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
00074 
00075   uint16_t Device_Code1;
00076 
00077   uint16_t Device_Code2;
00078 
00079   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
00080                                     These codes can be accessed by performing read operations with specific
00081                                     control signals and addresses set.They can also be accessed by issuing
00082                                     an Auto Select command                                                   */
00083 } NOR_IDTypeDef;
00084 
00085 /**
00086   * @brief  FMC NOR CFI typedef
00087   */
00088 typedef struct
00089 {
00090   /*!< Defines the information stored in the memory's Common flash interface
00091        which contains a description of various electrical and timing parameters,
00092        density information and functions supported by the memory                   */
00093 
00094   uint16_t CFI_1;
00095 
00096   uint16_t CFI_2;
00097 
00098   uint16_t CFI_3;
00099 
00100   uint16_t CFI_4;
00101 } NOR_CFITypeDef;
00102 
00103 /**
00104   * @brief  NOR handle Structure definition
00105   */
00106 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00107 typedef struct __NOR_HandleTypeDef
00108 #else
00109 typedef struct
00110 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS  */
00111 
00112 {
00113   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
00114 
00115   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
00116 
00117   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
00118 
00119   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
00120 
00121   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
00122 
00123   uint32_t                      CommandSet;   /*!< NOR algorithm command set and control        */
00124 
00125 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00126   void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor);               /*!< NOR Msp Init callback              */
00127   void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor);             /*!< NOR Msp DeInit callback            */
00128 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
00129 } NOR_HandleTypeDef;
00130 
00131 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00132 /**
00133   * @brief  HAL NOR Callback ID enumeration definition
00134   */
00135 typedef enum
00136 {
00137   HAL_NOR_MSP_INIT_CB_ID       = 0x00U,  /*!< NOR MspInit Callback ID          */
00138   HAL_NOR_MSP_DEINIT_CB_ID     = 0x01U   /*!< NOR MspDeInit Callback ID        */
00139 } HAL_NOR_CallbackIDTypeDef;
00140 
00141 /**
00142   * @brief  HAL NOR Callback pointer definition
00143   */
00144 typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
00145 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
00146 /**
00147   * @}
00148   */
00149 
00150 /* Exported constants --------------------------------------------------------*/
00151 /* Exported macro ------------------------------------------------------------*/
00152 /** @defgroup NOR_Exported_Macros NOR Exported Macros
00153   * @{
00154   */
00155 /** @brief Reset NOR handle state
00156   * @param  __HANDLE__ specifies the NOR handle.
00157   * @retval None
00158   */
00159 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00160 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)          do {                                             \
00161                                                                (__HANDLE__)->State = HAL_NOR_STATE_RESET;  \
00162                                                                (__HANDLE__)->MspInitCallback = NULL;       \
00163                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
00164                                                              } while(0)
00165 #else
00166 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
00167 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
00168 /**
00169   * @}
00170   */
00171 
00172 /* Exported functions --------------------------------------------------------*/
00173 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
00174   * @{
00175   */
00176 
00177 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00178   * @{
00179   */
00180 
00181 /* Initialization/de-initialization functions  ********************************/
00182 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
00183                                FMC_NORSRAM_TimingTypeDef *ExtTiming);
00184 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
00185 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
00186 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
00187 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
00188 /**
00189   * @}
00190   */
00191 
00192 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
00193   * @{
00194   */
00195 
00196 /* I/O operation functions  ***************************************************/
00197 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
00198 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
00199 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00200 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00201 
00202 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
00203                                      uint32_t uwBufferSize);
00204 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
00205                                         uint32_t uwBufferSize);
00206 
00207 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
00208 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
00209 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
00210 
00211 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00212 /* NOR callback registering/unregistering */
00213 HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
00214                                            pNOR_CallbackTypeDef pCallback);
00215 HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
00216 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
00217 /**
00218   * @}
00219   */
00220 
00221 /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
00222   * @{
00223   */
00224 
00225 /* NOR Control functions  *****************************************************/
00226 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
00227 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
00228 /**
00229   * @}
00230   */
00231 
00232 /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
00233   * @{
00234   */
00235 
00236 /* NOR State functions ********************************************************/
00237 HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
00238 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
00239 /**
00240   * @}
00241   */
00242 
00243 /**
00244   * @}
00245   */
00246 
00247 /* Private types -------------------------------------------------------------*/
00248 /* Private variables ---------------------------------------------------------*/
00249 /* Private constants ---------------------------------------------------------*/
00250 /** @defgroup NOR_Private_Constants NOR Private Constants
00251   * @{
00252   */
00253 /* NOR device IDs addresses */
00254 #define MC_ADDRESS               ((uint16_t)0x0000)
00255 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
00256 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
00257 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
00258 
00259 /* NOR CFI IDs addresses */
00260 #define CFI1_ADDRESS             ((uint16_t)0x0061)
00261 #define CFI2_ADDRESS             ((uint16_t)0x0062)
00262 #define CFI3_ADDRESS             ((uint16_t)0x0063)
00263 #define CFI4_ADDRESS             ((uint16_t)0x0064)
00264 
00265 /* NOR operation wait timeout */
00266 #define NOR_TMEOUT               ((uint16_t)0xFFFF)
00267 
00268 /* NOR memory data width */
00269 #define NOR_MEMORY_8B            ((uint8_t)0x00)
00270 #define NOR_MEMORY_16B           ((uint8_t)0x01)
00271 
00272 /* NOR memory device read/write start address */
00273 #define NOR_MEMORY_ADRESS1       (0x60000000U)
00274 #define NOR_MEMORY_ADRESS2       (0x64000000U)
00275 #define NOR_MEMORY_ADRESS3       (0x68000000U)
00276 #define NOR_MEMORY_ADRESS4       (0x6C000000U)
00277 /**
00278   * @}
00279   */
00280 
00281 /* Private macros ------------------------------------------------------------*/
00282 /** @defgroup NOR_Private_Macros NOR Private Macros
00283   * @{
00284   */
00285 /**
00286   * @brief  NOR memory address shifting.
00287   * @param  __NOR_ADDRESS NOR base address
00288   * @param  __NOR_MEMORY_WIDTH_ NOR memory width
00289   * @param  __ADDRESS__ NOR memory address
00290   * @retval NOR shifted address value
00291   */
00292 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)         \
00293   ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?            \
00294               ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
00295               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
00296 
00297 /**
00298   * @brief  NOR memory write data to specified address.
00299   * @param  __ADDRESS__ NOR memory address
00300   * @param  __DATA__ Data to write
00301   * @retval None
00302   */
00303 #define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \
00304                                                (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
00305                                                __DSB();                                                    \
00306                                              } while(0)
00307 
00308 /**
00309   * @}
00310   */
00311 
00312 /**
00313   * @}
00314   */
00315 
00316 /**
00317   * @}
00318   */
00319 
00320 #endif /* FMC_BANK1 */
00321 
00322 #ifdef __cplusplus
00323 }
00324 #endif
00325 
00326 #endif /* STM32L4xx_HAL_NOR_H */