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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_ospi.h 00004 * @author MCD Application Team 00005 * @brief Header file of OSPI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_OSPI_H 00021 #define STM32L4xx_HAL_OSPI_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx_hal_def.h" 00029 00030 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) 00031 00032 /** @addtogroup STM32L4xx_HAL_Driver 00033 * @{ 00034 */ 00035 00036 /** @addtogroup OSPI 00037 * @{ 00038 */ 00039 00040 /* Exported types ------------------------------------------------------------*/ 00041 /** @defgroup OSPI_Exported_Types OSPI Exported Types 00042 * @{ 00043 */ 00044 00045 /** 00046 * @brief OSPI Init structure definition 00047 */ 00048 typedef struct 00049 { 00050 uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt 00051 indicating that data are available in reception or free place 00052 is available in transmission. 00053 This parameter can be a value between 1 and 32 */ 00054 uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to 00055 quad mode on two different devices to increase the throughput. 00056 This parameter can be a value of @ref OSPI_DualQuad */ 00057 uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI. 00058 This parameter can be a value of @ref OSPI_MemoryType */ 00059 uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI, 00060 it corresponds to the number of address bits required to access 00061 the external device. 00062 This parameter can be a value between 1 and 32 */ 00063 uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select 00064 must remain high between commands. 00065 This parameter can be a value between 1 and 8 */ 00066 uint32_t FreeRunningClock; /*!< It enables or not the free running clock. 00067 This parameter can be a value of @ref OSPI_FreeRunningClock */ 00068 uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. 00069 This parameter can be a value of @ref OSPI_ClockMode */ 00070 uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating 00071 the external clock based on the AHB clock. 00072 This parameter can be a value between 1 and 256 */ 00073 uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order 00074 to take in account external signal delays. 00075 This parameter can be a value of @ref OSPI_SampleShifting */ 00076 uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. 00077 This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ 00078 uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and 00079 defines the boundary of bytes to release the chip select. 00080 This parameter can be a value between 0 and 31 */ 00081 uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected 00082 by the delay block. 00083 This parameter can be a value of @ref OSPI_DelayBlockBypass */ 00084 #if defined (OCTOSPI_DCR3_MAXTRAN) 00085 uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is 00086 released every MaxTran+1 bytes when the other OctoSPI request the access 00087 to the bus. 00088 This parameter can be a value between 0 and 255 */ 00089 #endif 00090 #if defined (OCTOSPI_DCR4_REFRESH) 00091 uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every 00092 Refresh+1 clock cycles. 00093 This parameter can be a value between 0 and 0xFFFFFFFF */ 00094 #endif 00095 }OSPI_InitTypeDef; 00096 00097 /** 00098 * @brief HAL OSPI Handle Structure definition 00099 */ 00100 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 00101 typedef struct __OSPI_HandleTypeDef 00102 #else 00103 typedef struct 00104 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 00105 { 00106 OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */ 00107 OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */ 00108 uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */ 00109 __IO uint32_t XferSize; /*!< Number of data to transfer */ 00110 __IO uint32_t XferCount; /*!< Counter of data transferred */ 00111 DMA_HandleTypeDef *hdma; /*!< Handle of the DMA channel used for the transfer */ 00112 __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */ 00113 __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ 00114 uint32_t Timeout; /*!< Timeout used for the OSPI external device access */ 00115 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 00116 void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi); 00117 void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 00118 void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); 00119 void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 00120 void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 00121 void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 00122 void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 00123 void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 00124 void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi); 00125 void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi); 00126 00127 void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi); 00128 void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi); 00129 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 00130 }OSPI_HandleTypeDef; 00131 00132 /** 00133 * @brief HAL OSPI Regular Command Structure definition 00134 */ 00135 typedef struct 00136 { 00137 uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or 00138 to the registers for the write operation (these registers are only 00139 used for memory-mapped mode). 00140 This parameter can be a value of @ref OSPI_OperationType */ 00141 uint32_t FlashId; /*!< It indicates which external device is selected for this command (it 00142 applies only if Dualquad is disabled in the initialization structure). 00143 This parameter can be a value of @ref OSPI_FlashID */ 00144 uint32_t Instruction; /*!< It contains the instruction to be sent to the device. 00145 This parameter can be a value between 0 and 0xFFFFFFFF */ 00146 uint32_t InstructionMode; /*!< It indicates the mode of the instruction. 00147 This parameter can be a value of @ref OSPI_InstructionMode */ 00148 uint32_t InstructionSize; /*!< It indicates the size of the instruction. 00149 This parameter can be a value of @ref OSPI_InstructionSize */ 00150 uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase. 00151 This parameter can be a value of @ref OSPI_InstructionDtrMode */ 00152 uint32_t Address; /*!< It contains the address to be sent to the device. 00153 This parameter can be a value between 0 and 0xFFFFFFFF */ 00154 uint32_t AddressMode; /*!< It indicates the mode of the address. 00155 This parameter can be a value of @ref OSPI_AddressMode */ 00156 uint32_t AddressSize; /*!< It indicates the size of the address. 00157 This parameter can be a value of @ref OSPI_AddressSize */ 00158 uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase. 00159 This parameter can be a value of @ref OSPI_AddressDtrMode */ 00160 uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. 00161 This parameter can be a value between 0 and 0xFFFFFFFF */ 00162 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. 00163 This parameter can be a value of @ref OSPI_AlternateBytesMode */ 00164 uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes. 00165 This parameter can be a value of @ref OSPI_AlternateBytesSize */ 00166 uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase. 00167 This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ 00168 uint32_t DataMode; /*!< It indicates the mode of the data. 00169 This parameter can be a value of @ref OSPI_DataMode */ 00170 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 00171 This field is only used for indirect mode. 00172 This parameter can be a value between 1 and 0xFFFFFFFF */ 00173 uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase. 00174 This parameter can be a value of @ref OSPI_DataDtrMode */ 00175 uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. 00176 This parameter can be a value between 0 and 31 */ 00177 uint32_t DQSMode; /*!< It enables or not the data strobe management. 00178 This parameter can be a value of @ref OSPI_DQSMode */ 00179 uint32_t SIOOMode; /*!< It enables or not the SIOO mode. 00180 This parameter can be a value of @ref OSPI_SIOOMode */ 00181 }OSPI_RegularCmdTypeDef; 00182 00183 /** 00184 * @brief HAL OSPI Hyperbus Configuration Structure definition 00185 */ 00186 typedef struct 00187 { 00188 uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time. 00189 This parameter can be a value between 0 and 255 */ 00190 uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time. 00191 This parameter can be a value between 0 and 255 */ 00192 uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. 00193 This parameter can be a value of @ref OSPI_WriteZeroLatency */ 00194 uint32_t LatencyMode; /*!< It configures the latency mode. 00195 This parameter can be a value of @ref OSPI_LatencyMode */ 00196 }OSPI_HyperbusCfgTypeDef; 00197 00198 /** 00199 * @brief HAL OSPI Hyperbus Command Structure definition 00200 */ 00201 typedef struct 00202 { 00203 uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. 00204 This parameter can be a value of @ref OSPI_AddressSpace */ 00205 uint32_t Address; /*!< It contains the address to be sent tot he device. 00206 This parameter can be a value between 0 and 0xFFFFFFFF */ 00207 uint32_t AddressSize; /*!< It indicates the size of the address. 00208 This parameter can be a value of @ref OSPI_AddressSize */ 00209 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 00210 This field is only used for indirect mode. 00211 This parameter can be a value between 1 and 0xFFFFFFFF 00212 In case of autopolling mode, this parameter can be any value between 1 and 4 */ 00213 uint32_t DQSMode; /*!< It enables or not the data strobe management. 00214 This parameter can be a value of @ref OSPI_DQSMode */ 00215 }OSPI_HyperbusCmdTypeDef; 00216 00217 /** 00218 * @brief HAL OSPI Auto Polling mode configuration structure definition 00219 */ 00220 typedef struct 00221 { 00222 uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match. 00223 This parameter can be any value between 0 and 0xFFFFFFFF */ 00224 uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received. 00225 This parameter can be any value between 0 and 0xFFFFFFFF */ 00226 uint32_t MatchMode; /*!< Specifies the method used for determining a match. 00227 This parameter can be a value of @ref OSPI_MatchMode */ 00228 uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. 00229 This parameter can be a value of @ref OSPI_AutomaticStop */ 00230 uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases. 00231 This parameter can be any value between 0 and 0xFFFF */ 00232 }OSPI_AutoPollingTypeDef; 00233 00234 /** 00235 * @brief HAL OSPI Memory Mapped mode configuration structure definition 00236 */ 00237 typedef struct 00238 { 00239 uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. 00240 This parameter can be a value of @ref OSPI_TimeOutActivation */ 00241 uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select. 00242 This parameter can be any value between 0 and 0xFFFF */ 00243 }OSPI_MemoryMappedTypeDef; 00244 00245 /** 00246 * @brief HAL OSPI IO Manager Configuration structure definition 00247 */ 00248 typedef struct 00249 { 00250 uint32_t ClkPort; /*!< It indicates which port of the OSPI IO Manager is used for the CLK pins. 00251 This parameter can be a value between 1 and 8 */ 00252 uint32_t DQSPort; /*!< It indicates which port of the OSPI IO Manager is used for the DQS pin. 00253 This parameter can be a value between 0 and 8, 0 means that signal not used */ 00254 uint32_t NCSPort; /*!< It indicates which port of the OSPI IO Manager is used for the NCS pin. 00255 This parameter can be a value between 1 and 8 */ 00256 uint32_t IOLowPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. 00257 This parameter can be a value of @ref OSPIM_IOPort */ 00258 uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. 00259 This parameter can be a value of @ref OSPIM_IOPort */ 00260 #if defined (OCTOSPIM_CR_MUXEN) 00261 uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected 00262 if some signals are multiplexed in the OSPI IO Manager with the other OSPI. 00263 This parameter can be a value between 1 and 256 */ 00264 #endif 00265 }OSPIM_CfgTypeDef; 00266 00267 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 00268 /** 00269 * @brief HAL OSPI Callback ID enumeration definition 00270 */ 00271 typedef enum 00272 { 00273 HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */ 00274 HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */ 00275 HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */ 00276 HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */ 00277 HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */ 00278 HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */ 00279 HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */ 00280 HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ 00281 HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ 00282 HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ 00283 00284 HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ 00285 HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ 00286 }HAL_OSPI_CallbackIDTypeDef; 00287 00288 /** 00289 * @brief HAL OSPI Callback pointer definition 00290 */ 00291 typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); 00292 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 00293 /** 00294 * @} 00295 */ 00296 00297 /* Exported constants --------------------------------------------------------*/ 00298 /** @defgroup OSPI_Exported_Constants OSPI Exported Constants 00299 * @{ 00300 */ 00301 00302 /** @defgroup OSPI_State OSPI State 00303 * @{ 00304 */ 00305 #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ 00306 #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ 00307 #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ 00308 #define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ 00309 #define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */ 00310 #define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */ 00311 #define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */ 00312 #define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */ 00313 #define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */ 00314 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */ 00315 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */ 00316 #define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */ 00317 #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ 00318 /** 00319 * @} 00320 */ 00321 00322 /** @defgroup OSPI_ErrorCode OSPI Error Code 00323 * @{ 00324 */ 00325 #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 00326 #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 00327 #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ 00328 #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ 00329 #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ 00330 #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ 00331 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 00332 #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ 00333 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ 00334 /** 00335 * @} 00336 */ 00337 00338 /** @defgroup OSPI_DualQuad OSPI Dual-Quad 00339 * @{ 00340 */ 00341 #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ 00342 #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ 00343 /** 00344 * @} 00345 */ 00346 00347 /** @defgroup OSPI_MemoryType OSPI Memory Type 00348 * @{ 00349 */ 00350 #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ 00351 #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ 00352 #if !defined(STM32L4R5xx)&&!defined(STM32L4R7xx)&&!defined(STM32L4R9xx)&&!defined(STM32L4S5xx)&&!defined(STM32L4S7xx)&&!defined(STM32L4S9xx) 00353 #define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */ 00354 #endif 00355 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ 00356 #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ 00357 /** 00358 * @} 00359 */ 00360 00361 /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock 00362 * @{ 00363 */ 00364 #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ 00365 #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ 00366 /** 00367 * @} 00368 */ 00369 00370 /** @defgroup OSPI_ClockMode OSPI Clock Mode 00371 * @{ 00372 */ 00373 #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ 00374 #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ 00375 /** 00376 * @} 00377 */ 00378 00379 /** @defgroup OSPI_SampleShifting OSPI Sample Shifting 00380 * @{ 00381 */ 00382 #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ 00383 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ 00384 /** 00385 * @} 00386 */ 00387 00388 /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle 00389 * @{ 00390 */ 00391 #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ 00392 #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ 00393 /** 00394 * @} 00395 */ 00396 00397 /** @defgroup OSPI_DelayBlockBypass OSPI Delay Block Bypaas 00398 * @{ 00399 */ 00400 #define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U) /*!< Sampling clock is delayed by the delay block */ 00401 #define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */ 00402 /** 00403 * @} 00404 */ 00405 00406 /** @defgroup OSPI_OperationType OSPI Operation Type 00407 * @{ 00408 */ 00409 #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ 00410 #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ 00411 #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ 00412 /** 00413 * @} 00414 */ 00415 00416 /** @defgroup OSPI_FlashID OSPI Flash Id 00417 * @{ 00418 */ 00419 #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ 00420 #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ 00421 /** 00422 * @} 00423 */ 00424 00425 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode 00426 * @{ 00427 */ 00428 #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ 00429 #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ 00430 #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ 00431 #define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ 00432 #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ 00433 /** 00434 * @} 00435 */ 00436 00437 /** @defgroup OSPI_InstructionSize OSPI Instruction Size 00438 * @{ 00439 */ 00440 #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ 00441 #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ 00442 #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ 00443 #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ 00444 /** 00445 * @} 00446 */ 00447 00448 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode 00449 * @{ 00450 */ 00451 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ 00452 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ 00453 /** 00454 * @} 00455 */ 00456 00457 /** @defgroup OSPI_AddressMode OSPI Address Mode 00458 * @{ 00459 */ 00460 #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ 00461 #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ 00462 #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ 00463 #define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */ 00464 #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ 00465 /** 00466 * @} 00467 */ 00468 00469 /** @defgroup OSPI_AddressSize OSPI Address Size 00470 * @{ 00471 */ 00472 #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ 00473 #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ 00474 #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ 00475 #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ 00476 /** 00477 * @} 00478 */ 00479 00480 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode 00481 * @{ 00482 */ 00483 #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ 00484 #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ 00485 /** 00486 * @} 00487 */ 00488 00489 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode 00490 * @{ 00491 */ 00492 #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ 00493 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ 00494 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ 00495 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ 00496 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ 00497 /** 00498 * @} 00499 */ 00500 00501 /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size 00502 * @{ 00503 */ 00504 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ 00505 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ 00506 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ 00507 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ 00508 /** 00509 * @} 00510 */ 00511 00512 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode 00513 * @{ 00514 */ 00515 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ 00516 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ 00517 /** 00518 * @} 00519 */ 00520 00521 /** @defgroup OSPI_DataMode OSPI Data Mode 00522 * @{ 00523 */ 00524 #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ 00525 #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ 00526 #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ 00527 #define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */ 00528 #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ 00529 /** 00530 * @} 00531 */ 00532 00533 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode 00534 * @{ 00535 */ 00536 #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ 00537 #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ 00538 /** 00539 * @} 00540 */ 00541 00542 /** @defgroup OSPI_DQSMode OSPI DQS Mode 00543 * @{ 00544 */ 00545 #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ 00546 #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ 00547 /** 00548 * @} 00549 */ 00550 00551 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode 00552 * @{ 00553 */ 00554 #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ 00555 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ 00556 /** 00557 * @} 00558 */ 00559 00560 /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation 00561 * @{ 00562 */ 00563 #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ 00564 #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ 00565 /** 00566 * @} 00567 */ 00568 00569 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode 00570 * @{ 00571 */ 00572 #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ 00573 #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ 00574 /** 00575 * @} 00576 */ 00577 00578 /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space 00579 * @{ 00580 */ 00581 #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ 00582 #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ 00583 /** 00584 * @} 00585 */ 00586 00587 /** @defgroup OSPI_MatchMode OSPI Match Mode 00588 * @{ 00589 */ 00590 #define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */ 00591 #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ 00592 /** 00593 * @} 00594 */ 00595 00596 /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop 00597 * @{ 00598 */ 00599 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */ 00600 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ 00601 /** 00602 * @} 00603 */ 00604 00605 /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation 00606 * @{ 00607 */ 00608 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */ 00609 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ 00610 /** 00611 * @} 00612 */ 00613 00614 /** @defgroup OSPI_Flags OSPI Flags 00615 * @{ 00616 */ 00617 #define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ 00618 #define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ 00619 #define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ 00620 #define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ 00621 #define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ 00622 #define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ 00623 /** 00624 * @} 00625 */ 00626 00627 /** @defgroup OSPI_Interrupts OSPI Interrupts 00628 * @{ 00629 */ 00630 #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ 00631 #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ 00632 #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ 00633 #define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ 00634 #define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ 00635 /** 00636 * @} 00637 */ 00638 00639 /** @defgroup OSPI_Timeout_definition OSPI Timeout definition 00640 * @{ 00641 */ 00642 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ 00643 /** 00644 * @} 00645 */ 00646 00647 /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port 00648 * @{ 00649 */ 00650 #define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */ 00651 #define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ 00652 #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ 00653 #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ 00654 #define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */ 00655 /** 00656 * @} 00657 */ 00658 /** 00659 * @} 00660 */ 00661 00662 /* Exported macros -----------------------------------------------------------*/ 00663 /** @defgroup OSPI_Exported_Macros OSPI Exported Macros 00664 * @{ 00665 */ 00666 /** @brief Reset OSPI handle state. 00667 * @param __HANDLE__ specifies the OSPI Handle. 00668 * @retval None 00669 */ 00670 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 00671 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 00672 (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ 00673 (__HANDLE__)->MspInitCallback = NULL; \ 00674 (__HANDLE__)->MspDeInitCallback = NULL; \ 00675 } while(0) 00676 #else 00677 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) 00678 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 00679 00680 /** @brief Enable the OSPI peripheral. 00681 * @param __HANDLE__ specifies the OSPI Handle. 00682 * @retval None 00683 */ 00684 #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 00685 00686 /** @brief Disable the OSPI peripheral. 00687 * @param __HANDLE__ specifies the OSPI Handle. 00688 * @retval None 00689 */ 00690 #define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 00691 00692 /** @brief Enable the specified OSPI interrupt. 00693 * @param __HANDLE__ specifies the OSPI Handle. 00694 * @param __INTERRUPT__ specifies the OSPI interrupt source to enable. 00695 * This parameter can be one of the following values: 00696 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 00697 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 00698 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 00699 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 00700 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 00701 * @retval None 00702 */ 00703 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00704 00705 00706 /** @brief Disable the specified OSPI interrupt. 00707 * @param __HANDLE__ specifies the OSPI Handle. 00708 * @param __INTERRUPT__ specifies the OSPI interrupt source to disable. 00709 * This parameter can be one of the following values: 00710 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 00711 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 00712 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 00713 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 00714 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 00715 * @retval None 00716 */ 00717 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00718 00719 /** @brief Check whether the specified OSPI interrupt source is enabled or not. 00720 * @param __HANDLE__ specifies the OSPI Handle. 00721 * @param __INTERRUPT__ specifies the OSPI interrupt source to check. 00722 * This parameter can be one of the following values: 00723 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 00724 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 00725 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 00726 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 00727 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 00728 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 00729 */ 00730 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ 00731 == (__INTERRUPT__)) 00732 00733 /** 00734 * @brief Check whether the selected OSPI flag is set or not. 00735 * @param __HANDLE__ specifies the OSPI Handle. 00736 * @param __FLAG__ specifies the OSPI flag to check. 00737 * This parameter can be one of the following values: 00738 * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag 00739 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 00740 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 00741 * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag 00742 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 00743 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 00744 * @retval None 00745 */ 00746 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ 00747 != 0U) ? SET : RESET) 00748 00749 /** @brief Clears the specified OSPI's flag status. 00750 * @param __HANDLE__ specifies the OSPI Handle. 00751 * @param __FLAG__ specifies the OSPI clear register flag that needs to be set 00752 * This parameter can be one of the following values: 00753 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 00754 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 00755 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 00756 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 00757 * @retval None 00758 */ 00759 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 00760 00761 /** 00762 * @} 00763 */ 00764 00765 /* Exported functions --------------------------------------------------------*/ 00766 /** @addtogroup OSPI_Exported_Functions 00767 * @{ 00768 */ 00769 00770 /* Initialization/de-initialization functions ********************************/ 00771 /** @addtogroup OSPI_Exported_Functions_Group1 00772 * @{ 00773 */ 00774 HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi); 00775 void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi); 00776 HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi); 00777 void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi); 00778 00779 /** 00780 * @} 00781 */ 00782 00783 /* IO operation functions *****************************************************/ 00784 /** @addtogroup OSPI_Exported_Functions_Group2 00785 * @{ 00786 */ 00787 /* OSPI IRQ handler function */ 00788 void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi); 00789 00790 /* OSPI command configuration functions */ 00791 HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); 00792 HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); 00793 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); 00794 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); 00795 00796 /* OSPI indirect mode functions */ 00797 HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 00798 HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 00799 HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); 00800 HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); 00801 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); 00802 HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); 00803 00804 /* OSPI status flag polling mode functions */ 00805 HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 00806 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); 00807 00808 /* OSPI memory-mapped mode functions */ 00809 HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); 00810 00811 /* Callback functions in non-blocking modes ***********************************/ 00812 void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi); 00813 void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi); 00814 void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi); 00815 00816 /* OSPI indirect mode functions */ 00817 void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi); 00818 void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi); 00819 void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi); 00820 void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi); 00821 void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi); 00822 00823 /* OSPI status flag polling mode functions */ 00824 void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi); 00825 00826 /* OSPI memory-mapped mode functions */ 00827 void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); 00828 00829 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 00830 /* OSPI callback registering/unregistering */ 00831 HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, 00832 pOSPI_CallbackTypeDef pCallback); 00833 HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); 00834 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 00835 /** 00836 * @} 00837 */ 00838 00839 /* Peripheral Control and State functions ************************************/ 00840 /** @addtogroup OSPI_Exported_Functions_Group3 00841 * @{ 00842 */ 00843 HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi); 00844 HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi); 00845 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold); 00846 uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi); 00847 HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout); 00848 uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi); 00849 uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi); 00850 00851 /** 00852 * @} 00853 */ 00854 00855 /* OSPI IO Manager configuration function ************************************/ 00856 /** @addtogroup OSPI_Exported_Functions_Group4 00857 * @{ 00858 */ 00859 HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); 00860 00861 /** 00862 * @} 00863 */ 00864 00865 /** 00866 * @} 00867 */ 00868 /* End of exported functions -------------------------------------------------*/ 00869 00870 /* Private macros ------------------------------------------------------------*/ 00871 /** 00872 @cond 0 00873 */ 00874 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U)) 00875 00876 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ 00877 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) 00878 00879 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00880 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ 00881 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ 00882 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ 00883 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) 00884 #else 00885 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ 00886 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ 00887 ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \ 00888 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ 00889 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) 00890 #endif 00891 00892 #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) 00893 00894 #define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) 00895 00896 #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ 00897 ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) 00898 00899 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ 00900 ((MODE) == HAL_OSPI_CLOCK_MODE_3)) 00901 00902 #define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U)) 00903 00904 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ 00905 ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) 00906 00907 #define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \ 00908 ((CYCLE) == HAL_OSPI_DHQC_ENABLE)) 00909 00910 #define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ 00911 ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ 00912 ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG)) 00913 00914 #define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \ 00915 ((FLASHID) == HAL_OSPI_FLASH_ID_2)) 00916 00917 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ 00918 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ 00919 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \ 00920 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \ 00921 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES)) 00922 00923 #define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \ 00924 ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \ 00925 ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \ 00926 ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS)) 00927 00928 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ 00929 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) 00930 00931 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ 00932 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \ 00933 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \ 00934 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \ 00935 ((MODE) == HAL_OSPI_ADDRESS_8_LINES)) 00936 00937 #define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \ 00938 ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \ 00939 ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \ 00940 ((SIZE) == HAL_OSPI_ADDRESS_32_BITS)) 00941 00942 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ 00943 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE)) 00944 00945 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ 00946 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \ 00947 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \ 00948 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \ 00949 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES)) 00950 00951 #define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \ 00952 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \ 00953 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \ 00954 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS)) 00955 00956 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ 00957 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE)) 00958 00959 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ 00960 ((MODE) == HAL_OSPI_DATA_1_LINE) || \ 00961 ((MODE) == HAL_OSPI_DATA_2_LINES) || \ 00962 ((MODE) == HAL_OSPI_DATA_4_LINES) || \ 00963 ((MODE) == HAL_OSPI_DATA_8_LINES)) 00964 00965 #define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U) 00966 00967 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ 00968 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) 00969 00970 #define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) 00971 00972 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ 00973 ((MODE) == HAL_OSPI_DQS_ENABLE)) 00974 00975 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ 00976 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) 00977 00978 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U) 00979 00980 #define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U) 00981 00982 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ 00983 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) 00984 00985 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ 00986 ((MODE) == HAL_OSPI_FIXED_LATENCY)) 00987 00988 #define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \ 00989 ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE)) 00990 00991 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ 00992 ((MODE) == HAL_OSPI_MATCH_MODE_OR)) 00993 00994 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ 00995 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) 00996 00997 #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) 00998 00999 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 01000 01001 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ 01002 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) 01003 01004 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 01005 01006 #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) 01007 #if defined (OCTOSPI_DCR3_MAXTRAN) 01008 01009 #define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) 01010 #endif 01011 01012 #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 2U)) 01013 01014 #define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 2U) 01015 01016 #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \ 01017 ((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ 01018 ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ 01019 ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ 01020 ((PORT) == HAL_OSPIM_IOPORT_2_HIGH)) 01021 01022 #if defined (OCTOSPIM_CR_MUXEN) 01023 #define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) 01024 #endif /*(OCTOSPIM_CR_MUXEN)*/ 01025 /** 01026 @endcond 01027 */ 01028 01029 /* End of private macros -----------------------------------------------------*/ 01030 01031 /** 01032 * @} 01033 */ 01034 01035 /** 01036 * @} 01037 */ 01038 01039 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ 01040 01041 #ifdef __cplusplus 01042 } 01043 #endif 01044 01045 #endif /* STM32L4xx_HAL_OSPI_H */
1.7.6.1