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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_pssi.h 00004 * @author MCD Application Team 00005 * @brief Header file of PSSI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2019 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_PSSI_H 00021 #define STM32L4xx_HAL_PSSI_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx_hal_def.h" 00029 00030 /** @addtogroup STM32L4xx_HAL_Driver 00031 * @{ 00032 */ 00033 #if defined(PSSI) 00034 /** @defgroup PSSI PSSI 00035 * @brief PSSI HAL module driver 00036 * @{ 00037 */ 00038 00039 #ifdef HAL_PSSI_MODULE_ENABLED 00040 00041 /* Exported types ------------------------------------------------------------*/ 00042 /** @defgroup PSSI_Exported_Types PSSI Exported Types 00043 * @{ 00044 */ 00045 00046 00047 /** 00048 * @brief PSSI Init structure definition 00049 */ 00050 typedef struct 00051 { 00052 uint32_t DataWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */ 00053 uint32_t BusWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */ 00054 uint32_t ControlSignal; /* !< Configures Data enable and Data ready */ 00055 uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity */ 00056 uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */ 00057 uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity */ 00058 00059 } PSSI_InitTypeDef; 00060 00061 00062 /** 00063 * @brief HAL PSSI State structures definition 00064 */ 00065 typedef enum 00066 { 00067 HAL_PSSI_STATE_RESET = 0x00U, /* !< PSSI not yet initialized or disabled */ 00068 HAL_PSSI_STATE_READY = 0x01U, /* !< Peripheral initialized and ready for use */ 00069 HAL_PSSI_STATE_BUSY = 0x02U, /* !< An internal process is ongoing */ 00070 HAL_PSSI_STATE_BUSY_TX = 0x03U, /* !< Transmit process is ongoing */ 00071 HAL_PSSI_STATE_BUSY_RX = 0x04U, /* !< Receive process is ongoing */ 00072 HAL_PSSI_STATE_TIMEOUT = 0x05U, /* !< Timeout state */ 00073 HAL_PSSI_STATE_ERROR = 0x06U, /* !< PSSI state error */ 00074 HAL_PSSI_STATE_ABORT = 0x07U, /* !< PSSI process is aborted */ 00075 00076 } HAL_PSSI_StateTypeDef; 00077 00078 /** 00079 * @brief PSSI handle Structure definition 00080 */ 00081 typedef struct __PSSI_HandleTypeDef 00082 { 00083 PSSI_TypeDef *Instance; /*!< PSSI register base address */ 00084 PSSI_InitTypeDef Init; /*!< PSSI Initialization Structure */ 00085 uint32_t *pBuffPtr; /*!< PSSI Data buffer */ 00086 uint32_t XferCount; /*!< PSSI transfer count */ 00087 uint32_t XferSize; /*!< PSSI transfer size */ 00088 DMA_HandleTypeDef *hdmatx; /*!< PSSI Tx DMA Handle parameters */ 00089 DMA_HandleTypeDef *hdmarx; /*!< PSSI Rx DMA Handle parameters */ 00090 00091 void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback */ 00092 void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback */ 00093 void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback */ 00094 void (* AbortCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer error callback */ 00095 00096 void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp Init callback */ 00097 void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback */ 00098 00099 HAL_LockTypeDef Lock; /*!< PSSI lock */ 00100 __IO HAL_PSSI_StateTypeDef State; /*!< PSSI transfer state */ 00101 __IO uint32_t ErrorCode; /*!< PSSI error code */ 00102 00103 } PSSI_HandleTypeDef; 00104 00105 00106 /** 00107 * @brief HAL PSSI Callback pointer definition 00108 */ 00109 typedef void (*pPSSI_CallbackTypeDef)(PSSI_HandleTypeDef *hpssi); /*!< Pointer to a PSSI common callback function */ 00110 00111 00112 /** 00113 * @brief HAL PSSI Callback ID enumeration definition 00114 */ 00115 typedef enum 00116 { 00117 HAL_PSSI_TX_COMPLETE_CB_ID = 0x00U, /*!< PSSI Tx Transfer completed callback ID */ 00118 HAL_PSSI_RX_COMPLETE_CB_ID = 0x01U, /*!< PSSI Rx Transfer completed callback ID */ 00119 HAL_PSSI_ERROR_CB_ID = 0x03U, /*!< PSSI Error callback ID */ 00120 HAL_PSSI_ABORT_CB_ID = 0x04U, /*!< PSSI Abort callback ID */ 00121 00122 HAL_PSSI_MSPINIT_CB_ID = 0x05U, /*!< PSSI Msp Init callback ID */ 00123 HAL_PSSI_MSPDEINIT_CB_ID = 0x06U /*!< PSSI Msp DeInit callback ID */ 00124 00125 } HAL_PSSI_CallbackIDTypeDef; 00126 00127 /** 00128 * @} 00129 */ 00130 00131 /* Exported constants --------------------------------------------------------*/ 00132 /** @defgroup PSSI_Exported_Constants PSSI Exported Constants 00133 * @{ 00134 */ 00135 00136 /** @defgroup PSSI_ERROR_CODE PSSI Error Code 00137 * @{ 00138 */ 00139 #define HAL_PSSI_ERROR_NONE 0x00000000U /*!< No error */ 00140 #define HAL_PSSI_ERROR_NOT_SUPPORTED 0x00000001U /*!< Not supported operation */ 00141 #define HAL_PSSI_ERROR_UNDER_RUN 0x00000002U /*!< FIFO Under-run error */ 00142 #define HAL_PSSI_ERROR_OVER_RUN 0x00000004U /*!< FIFO Over-run error */ 00143 #define HAL_PSSI_ERROR_DMA 0x00000008U /*!< Dma error */ 00144 #define HAL_PSSI_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ 00145 #define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */ 00146 00147 00148 /** 00149 * @} 00150 */ 00151 00152 /** @defgroup PSSI_DATA_WIDTH PSSI Data Width 00153 * @{ 00154 */ 00155 00156 #define HAL_PSSI_8BITS 0x00000000U /*!< 8 Bits */ 00157 #define HAL_PSSI_16BITS 0x00000001U /*!< 16 Bits */ 00158 #define HAL_PSSI_32BITS 0x00000002U /*!< 32 Bits */ 00159 /** 00160 * @} 00161 */ 00162 00163 /** @defgroup PSSI_BUS_WIDTH PSSI Bus Width 00164 * @{ 00165 */ 00166 00167 #define HAL_PSSI_8LINES 0x00000000U /*!< 8 data lines */ 00168 #define HAL_PSSI_16LINES PSSI_CR_EDM /*!< 16 data lines */ 00169 /** 00170 * @} 00171 */ 00172 /** @defgroup PSSI_MODE PSSI mode 00173 * @{ 00174 */ 00175 #define HAL_PSSI_UNIDIRECTIONAL 0x00000000U /*!< Uni-directional mode */ 00176 #define HAL_PSSI_BIDIRECTIONAL 0x00000001U /*!< Bi-directional mode */ 00177 /** 00178 * @} 00179 */ 00180 00181 /** @defgroup PSSI_CONTROL_SIGNAL PSSI Control Signal Configuration 00182 * @{ 00183 */ 00184 #define HAL_PSSI_DE_RDY_DISABLE (0x0U << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */ 00185 #define HAL_PSSI_RDY_ENABLE (0x1U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled */ 00186 #define HAL_PSSI_DE_ENABLE (0x2U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled */ 00187 #define HAL_PSSI_DE_RDY_ALT_ENABLE (0x3U << PSSI_CR_DERDYCFG_Pos) /*!< Both RDY and DE alternate functions enabled */ 00188 #define HAL_PSSI_MAP_RDY_BIDIR_ENABLE (0x4U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on RDY pin */ 00189 #define HAL_PSSI_RDY_MAP_ENABLE (0x5U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled, mapped to DE pin */ 00190 #define HAL_PSSI_DE_MAP_ENABLE (0x6U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled, mapped to RDY pin */ 00191 #define HAL_PSSI_MAP_DE_BIDIR_ENABLE (0x7U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on DE pin */ 00192 00193 /** 00194 * @} 00195 */ 00196 00197 00198 /** @defgroup PSSI_DATA_ENABLE_POLARITY PSSI Data Enable Polarity 00199 * @{ 00200 */ 00201 #define HAL_PSSI_DEPOL_ACTIVE_LOW 0x0U /*!< Active Low */ 00202 #define HAL_PSSI_DEPOL_ACTIVE_HIGH PSSI_CR_DEPOL /*!< Active High */ 00203 /** 00204 * @} 00205 */ 00206 /** @defgroup PSSI_READY_POLARITY PSSI Ready Polarity 00207 * @{ 00208 */ 00209 #define HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U /*!< Active Low */ 00210 #define HAL_PSSI_RDYPOL_ACTIVE_HIGH PSSI_CR_RDYPOL /*!< Active High */ 00211 /** 00212 * @} 00213 */ 00214 00215 /** @defgroup PSSI_CLOCK_POLARITY PSSI Clock Polarity 00216 * @{ 00217 */ 00218 #define HAL_PSSI_FALLING_EDGE 0x0U /*!< Falling Edge */ 00219 #define HAL_PSSI_RISING_EDGE 0x1U /*!< Rising Edge */ 00220 00221 00222 /** 00223 * @} 00224 */ 00225 00226 00227 /** @defgroup PSSI_DEFINITION PSSI definitions 00228 * @{ 00229 */ 00230 00231 #define PSSI_MAX_NBYTE_SIZE 0x10000U /* 64 KB */ 00232 #define PSSI_TIMEOUT_TRANSMIT 0x0000FFFFU /*!< Timeout Value */ 00233 00234 #define PSSI_CR_OUTEN_INPUT 0x00000000U /*!< Input Mode */ 00235 #define PSSI_CR_OUTEN_OUTPUT PSSI_CR_OUTEN /*!< Output Mode */ 00236 00237 #define PSSI_CR_DMA_ENABLE PSSI_CR_DMAEN /*!< DMA Mode Enable */ 00238 #define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN) /*!< DMA Mode Disble */ 00239 00240 #define PSSI_CR_16BITS PSSI_CR_EDM /*!< 16 Lines Mode */ 00241 #define PSSI_CR_8BITS (~PSSI_CR_EDM) /*!< 8 Lines Mode */ 00242 00243 #define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag*/ 00244 #define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/ 00245 00246 00247 00248 /** 00249 * @} 00250 */ 00251 00252 /** @defgroup PSSI_INTERRUPTS PSSI Interrupts 00253 * @{ 00254 */ 00255 00256 #define PSSI_FLAG_OVR_RIS PSSI_RIS_OVR_RIS /*!< Overrun, Underrun errors flag */ 00257 #define PSSI_FLAG_MASK PSSI_RIS_OVR_RIS_Msk /*!< Overrun, Underrun errors Mask */ 00258 #define PSSI_FLAG_OVR_MIS PSSI_MIS_OVR_MIS /*!< Overrun, Underrun masked errors flag */ 00259 /** 00260 * @} 00261 */ 00262 00263 00264 00265 /** 00266 * @} 00267 */ 00268 /* Exported macros ------------------------------------------------------------*/ 00269 /** @defgroup PSSI_Exported_Macros PSSI Exported Macros 00270 * @{ 00271 */ 00272 00273 /** @brief Reset PSSI handle state 00274 * @param __HANDLE__ specifies the PSSI handle. 00275 * @retval None 00276 */ 00277 00278 #define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00279 (__HANDLE__)->State = HAL_PSSI_STATE_RESET;\ 00280 (__HANDLE__)->MspInitCallback = NULL; \ 00281 (__HANDLE__)->MspDeInitCallback = NULL; \ 00282 }while(0) 00283 00284 00285 /** 00286 * @brief Enable the PSSI. 00287 * @param __HANDLE__ PSSI handle 00288 * @retval None. 00289 */ 00290 #define HAL_PSSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= PSSI_CR_ENABLE) 00291 /** 00292 * @brief Disable the PSSI. 00293 * @param __HANDLE__ PSSI handle 00294 * @retval None. 00295 */ 00296 #define HAL_PSSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~PSSI_CR_ENABLE)) 00297 00298 /* PSSI pripheral STATUS */ 00299 /** 00300 * @brief Get the PSSI pending flags. 00301 * @param __HANDLE__ PSSI handle 00302 * @param __FLAG__ flag to check. 00303 * This parameter can be any combination of the following values: 00304 * @arg PSSI_FLAG_RTT1B: FIFO is ready to transfer one byte 00305 * @arg PSSI_FLAG_RTT4B: FIFO is ready to transfer four bytes 00306 * @retval The state of FLAG. 00307 */ 00308 00309 #define HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__)) 00310 00311 00312 00313 /* Interrupt & Flag management */ 00314 /** 00315 * @brief Get the PSSI pending flags. 00316 * @param __HANDLE__ PSSI handle 00317 * @param __FLAG__ flag to check. 00318 * This parameter can be any combination of the following values: 00319 * @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag 00320 * @retval The state of FLAG. 00321 */ 00322 #define HAL_PSSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RIS & (__FLAG__)) 00323 00324 /** 00325 * @brief Clear the PSSI pending flags. 00326 * @param __HANDLE__ PSSI handle 00327 * @param __FLAG__ specifies the flag to clear. 00328 * This parameter can be any combination of the following values: 00329 * @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag 00330 * @retval None 00331 */ 00332 #define HAL_PSSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 00333 00334 /** 00335 * @brief Enable the specified PSSI interrupts. 00336 * @param __HANDLE__ PSSI handle 00337 * @param __INTERRUPT__ specifies the PSSI interrupt sources to be enabled. 00338 * This parameter can be any combination of the following values: 00339 * @arg PSSI_FLAG_OVR_RIS: Configuration error mask 00340 * @retval None 00341 */ 00342 #define HAL_PSSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 00343 00344 /** 00345 * @brief Disable the specified PSSI interrupts. 00346 * @param __HANDLE__ PSSI handle 00347 * @param __INTERRUPT__ specifies the PSSI interrupt sources to be disabled. 00348 * This parameter can be any combination of the following values: 00349 * @arg PSSI_IT_OVR_IE: Configuration error mask 00350 * @retval None 00351 */ 00352 #define HAL_PSSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) 00353 00354 /** 00355 * @brief Check whether the specified PSSI interrupt source is enabled or not. 00356 * @param __HANDLE__ PSSI handle 00357 * @param __INTERRUPT__ specifies the PSSI interrupt source to check. 00358 * This parameter can be one of the following values: 00359 * @arg PSSI_IT_OVR_IE: Data Buffer overrun/underrun error interrupt mask 00360 * @retval The state of INTERRUPT source. 00361 */ 00362 #define HAL_PSSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) 00363 00364 00365 /** 00366 * @brief Check whether the PSSI Control signal is valid. 00367 * @param __CONTROL__ Control signals configuration 00368 * @retval Valid or not. 00369 */ 00370 00371 #define IS_PSSI_CONTROL_SIGNAL(__CONTROL__) (((__CONTROL__) == HAL_PSSI_DE_RDY_DISABLE ) || \ 00372 ((__CONTROL__) == HAL_PSSI_RDY_ENABLE ) || \ 00373 ((__CONTROL__) == HAL_PSSI_DE_ENABLE ) || \ 00374 ((__CONTROL__) == HAL_PSSI_DE_RDY_ALT_ENABLE ) || \ 00375 ((__CONTROL__) == HAL_PSSI_MAP_RDY_BIDIR_ENABLE ) || \ 00376 ((__CONTROL__) == HAL_PSSI_RDY_MAP_ENABLE ) || \ 00377 ((__CONTROL__) == HAL_PSSI_DE_MAP_ENABLE ) || \ 00378 ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE )) 00379 00380 /** 00381 * @brief Check whether the PSSI Bus Width is valid. 00382 * @param __BUSWIDTH__ PSSI Bush width 00383 * @retval Valid or not. 00384 */ 00385 00386 #define IS_PSSI_BUSWIDTH(__BUSWIDTH__) (((__BUSWIDTH__) == HAL_PSSI_8LINES ) || \ 00387 ((__BUSWIDTH__) == HAL_PSSI_16LINES )) 00388 00389 00390 /** 00391 * @brief Check whether the PSSI Clock Polarity is valid. 00392 * @param __CLOCKPOL__ PSSI Clock Polarity 00393 * @retval Valid or not. 00394 */ 00395 00396 #define IS_PSSI_CLOCK_POLARITY(__CLOCKPOL__) (((__CLOCKPOL__) == HAL_PSSI_FALLING_EDGE ) || \ 00397 ((__CLOCKPOL__) == HAL_PSSI_RISING_EDGE )) 00398 00399 /** 00400 * @brief Check whether the PSSI Data Enable Polarity is valid. 00401 * @param __DEPOL__ PSSI DE Polarity 00402 * @retval Valid or not. 00403 */ 00404 00405 #define IS_PSSI_DE_POLARITY(__DEPOL__) (((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_LOW ) || \ 00406 ((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_HIGH )) 00407 00408 /** 00409 * @brief Check whether the PSSI Ready Polarity is valid. 00410 * @param __RDYPOL__ PSSI RDY Polarity 00411 * @retval Valid or not. 00412 */ 00413 00414 #define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW ) || \ 00415 ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH )) 00416 /** 00417 * @} 00418 */ 00419 00420 00421 /* Exported functions --------------------------------------------------------*/ 00422 /** @defgroup PSSI_Exported_Functions PSSI Exported Functions 00423 * @{ 00424 */ 00425 00426 /** @defgroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions 00427 * @{ 00428 */ 00429 00430 /* Initialization and de-initialization functions *******************************/ 00431 HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi); 00432 HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi); 00433 void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi); 00434 void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi); 00435 /* Callbacks Register/UnRegister functions ***********************************/ 00436 00437 HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback); 00438 HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID); 00439 00440 00441 /** 00442 * @} 00443 */ 00444 00445 00446 /** @defgroup PSSI_Exported_Functions_Group2 IO operation functions 00447 * @{ 00448 */ 00449 00450 /* IO operation functions *******************************************************/ 00451 HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout); 00452 HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout); 00453 HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); 00454 HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); 00455 HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi); 00456 void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi); 00457 00458 /** 00459 * @} 00460 */ 00461 00462 /** @defgroup PSSI_Exported_Functions_Group3 Peripheral Control functions 00463 * @{ 00464 */ 00465 00466 void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi); 00467 void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi); 00468 void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi); 00469 void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi); 00470 00471 00472 /** 00473 * @} 00474 */ 00475 00476 /** @defgroup PSSI_Exported_Functions_Group4 Peripheral State and Error functions 00477 * @{ 00478 */ 00479 00480 /* Peripheral State functions ***************************************************/ 00481 HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi); 00482 uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi); 00483 00484 /** 00485 * @} 00486 */ 00487 00488 /** 00489 * @} 00490 */ 00491 00492 /* Private constants ---------------------------------------------------------*/ 00493 00494 00495 /* Private macros ------------------------------------------------------------*/ 00496 00497 #endif /* HAL_PSSI_MODULE_ENABLED */ 00498 /** 00499 * @} 00500 */ 00501 #endif /* PSSI */ 00502 00503 /** 00504 * @} 00505 */ 00506 00507 00508 #ifdef __cplusplus 00509 } 00510 #endif 00511 00512 #endif /* STM32L4xx_HAL_PSSI_H */
1.7.6.1