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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_pwr_ex.h 00004 * @author MCD Application Team 00005 * @brief Header file of PWR HAL Extended module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_PWR_EX_H 00021 #define STM32L4xx_HAL_PWR_EX_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx_hal_def.h" 00029 00030 /** @addtogroup STM32L4xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup PWREx 00035 * @{ 00036 */ 00037 00038 00039 /* Exported types ------------------------------------------------------------*/ 00040 00041 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 00042 * @{ 00043 */ 00044 00045 00046 /** 00047 * @brief PWR PVM configuration structure definition 00048 */ 00049 typedef struct 00050 { 00051 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. 00052 This parameter can be a value of @ref PWREx_PVM_Type. 00053 @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 00054 @if STM32L486xx 00055 @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). 00056 @endif 00057 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 00058 @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */ 00059 00060 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 00061 This parameter can be a value of @ref PWREx_PVM_Mode. */ 00062 }PWR_PVMTypeDef; 00063 00064 /** 00065 * @} 00066 */ 00067 00068 /* Exported constants --------------------------------------------------------*/ 00069 00070 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 00071 * @{ 00072 */ 00073 00074 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants 00075 * @{ 00076 */ 00077 #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */ 00078 /** 00079 * @} 00080 */ 00081 00082 00083 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins 00084 * @{ 00085 */ 00086 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 00087 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 00088 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 00089 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 00090 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 00091 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 00092 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 00093 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 00094 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 00095 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 00096 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ 00097 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ 00098 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ 00099 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ 00100 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ 00101 /** 00102 * @} 00103 */ 00104 00105 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type 00106 * @{ 00107 */ 00108 #if defined(PWR_CR2_PVME1) 00109 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ 00110 #endif /* PWR_CR2_PVME1 */ 00111 #if defined(PWR_CR2_PVME2) 00112 #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */ 00113 #endif /* PWR_CR2_PVME2 */ 00114 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ 00115 #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */ 00116 /** 00117 * @} 00118 */ 00119 00120 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode 00121 * @{ 00122 */ 00123 #define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ 00124 #define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ 00125 #define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ 00126 #define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 00127 #define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ 00128 #define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ 00129 #define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ 00130 /** 00131 * @} 00132 */ 00133 00134 00135 00136 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale 00137 * @{ 00138 */ 00139 #if defined(PWR_CR5_R1MODE) 00140 #define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */ 00141 #endif 00142 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */ 00143 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ 00144 /** 00145 * @} 00146 */ 00147 00148 00149 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection 00150 * @{ 00151 */ 00152 #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */ 00153 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 00154 /** 00155 * @} 00156 */ 00157 00158 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging 00159 * @{ 00160 */ 00161 #define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000) 00162 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE 00163 /** 00164 * @} 00165 */ 00166 00167 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode 00168 * @{ 00169 */ 00170 #define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */ 00171 #define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */ 00172 #define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */ 00173 #define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */ 00174 #define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */ 00175 #define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */ 00176 #define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */ 00177 #define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */ 00178 #define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */ 00179 #define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */ 00180 #define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */ 00181 #define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */ 00182 #define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */ 00183 #define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */ 00184 #define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */ 00185 #define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */ 00186 /** 00187 * @} 00188 */ 00189 00190 /** @defgroup PWREx_GPIO GPIO port 00191 * @{ 00192 */ 00193 #define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ 00194 #define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ 00195 #define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ 00196 #if defined(GPIOD_BASE) 00197 #define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ 00198 #endif 00199 #if defined(GPIOE_BASE) 00200 #define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ 00201 #endif 00202 #if defined(GPIOF_BASE) 00203 #define PWR_GPIO_F 0x00000005U /*!< GPIO port F */ 00204 #endif 00205 #if defined(GPIOG_BASE) 00206 #define PWR_GPIO_G 0x00000006U /*!< GPIO port G */ 00207 #endif 00208 #define PWR_GPIO_H 0x00000007U /*!< GPIO port H */ 00209 #if defined(GPIOI_BASE) 00210 #define PWR_GPIO_I 0x00000008U /*!< GPIO port I */ 00211 #endif 00212 /** 00213 * @} 00214 */ 00215 00216 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines 00217 * @{ 00218 */ 00219 #if defined(PWR_CR2_PVME1) 00220 #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */ 00221 #endif /* PWR_CR2_PVME1 */ 00222 #if defined(PWR_CR2_PVME2) 00223 #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */ 00224 #endif /* PWR_CR2_PVME2 */ 00225 #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */ 00226 #define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ 00227 /** 00228 * @} 00229 */ 00230 00231 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines 00232 * @{ 00233 */ 00234 #if defined(PWR_CR2_PVME1) 00235 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */ 00236 #endif /* PWR_CR2_PVME1 */ 00237 #if defined(PWR_CR2_PVME2) 00238 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */ 00239 #endif /* PWR_CR2_PVME2 */ 00240 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */ 00241 #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */ 00242 /** 00243 * @} 00244 */ 00245 00246 /** @defgroup PWREx_Flag PWR Status Flags 00247 * Elements values convention: 0000 0000 0XXY YYYYb 00248 * - Y YYYY : Flag position in the XX register (5 bits) 00249 * - XX : Status register (2 bits) 00250 * - 01: SR1 register 00251 * - 10: SR2 register 00252 * The only exception is PWR_FLAG_WU, encompassing all 00253 * wake-up flags and set to PWR_SR1_WUF. 00254 * @{ 00255 */ 00256 #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */ 00257 #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */ 00258 #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */ 00259 #define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */ 00260 #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */ 00261 #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ 00262 #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */ 00263 #if defined(PWR_SR1_EXT_SMPS_RDY) 00264 #define PWR_FLAG_EXT_SMPS ((uint32_t)0x002D) /*!< Switching to external SMPS ready flag */ 00265 #endif /* PWR_SR1_EXT_SMPS_RDY */ 00266 #define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */ 00267 00268 #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */ 00269 #define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */ 00270 #define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */ 00271 #define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */ 00272 #if defined(PWR_CR2_PVME1) 00273 #define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */ 00274 #endif /* PWR_CR2_PVME1 */ 00275 #if defined(PWR_CR2_PVME2) 00276 #define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */ 00277 #endif /* PWR_CR2_PVME2 */ 00278 #define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */ 00279 #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */ 00280 /** 00281 * @} 00282 */ 00283 00284 /** @defgroup PWREx_SRAM2_Retention PWR SRAM2 Retention in Standby mode 00285 * @{ 00286 */ 00287 #define PWR_NO_SRAM2_RETENTION ((uint32_t)0x00000000) /*!< SRAM2 is powered off in Standby mode (SRAM2 content is lost) */ 00288 #if defined(PWR_CR3_RRS_1) 00289 #define PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS_0 /*!< Full SRAM2 is powered by the low-power regulator in Standby mode */ 00290 #define PWR_4KBYTES_SRAM2_RETENTION PWR_CR3_RRS_1 /*!< Only 4 Kbytes of SRAM2 is powered by the low-power regulator in Standby mode */ 00291 #else 00292 #define PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS /*!< Full SRAM2 is powered by the low-power regulator in Standby mode */ 00293 #endif /* PWR_CR3_RRS_1 */ 00294 /** 00295 * @} 00296 */ 00297 00298 /** 00299 * @} 00300 */ 00301 00302 /* Exported macros -----------------------------------------------------------*/ 00303 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 00304 * @{ 00305 */ 00306 00307 #if defined(PWR_CR2_PVME1) 00308 /** 00309 * @brief Enable the PVM1 Extended Interrupt Line. 00310 * @retval None 00311 */ 00312 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 00313 00314 /** 00315 * @brief Disable the PVM1 Extended Interrupt Line. 00316 * @retval None 00317 */ 00318 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 00319 00320 /** 00321 * @brief Enable the PVM1 Event Line. 00322 * @retval None 00323 */ 00324 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 00325 00326 /** 00327 * @brief Disable the PVM1 Event Line. 00328 * @retval None 00329 */ 00330 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 00331 00332 /** 00333 * @brief Enable the PVM1 Extended Interrupt Rising Trigger. 00334 * @retval None 00335 */ 00336 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 00337 00338 /** 00339 * @brief Disable the PVM1 Extended Interrupt Rising Trigger. 00340 * @retval None 00341 */ 00342 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 00343 00344 /** 00345 * @brief Enable the PVM1 Extended Interrupt Falling Trigger. 00346 * @retval None 00347 */ 00348 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 00349 00350 00351 /** 00352 * @brief Disable the PVM1 Extended Interrupt Falling Trigger. 00353 * @retval None 00354 */ 00355 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 00356 00357 00358 /** 00359 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. 00360 * @retval None 00361 */ 00362 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ 00363 do { \ 00364 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ 00365 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ 00366 } while(0) 00367 00368 /** 00369 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. 00370 * @retval None 00371 */ 00372 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ 00373 do { \ 00374 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ 00375 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ 00376 } while(0) 00377 00378 /** 00379 * @brief Generate a Software interrupt on selected EXTI line. 00380 * @retval None 00381 */ 00382 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) 00383 00384 /** 00385 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. 00386 * @retval EXTI PVM1 Line Status. 00387 */ 00388 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1) 00389 00390 /** 00391 * @brief Clear the PVM1 EXTI flag. 00392 * @retval None 00393 */ 00394 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1) 00395 00396 #endif /* PWR_CR2_PVME1 */ 00397 00398 00399 #if defined(PWR_CR2_PVME2) 00400 /** 00401 * @brief Enable the PVM2 Extended Interrupt Line. 00402 * @retval None 00403 */ 00404 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 00405 00406 /** 00407 * @brief Disable the PVM2 Extended Interrupt Line. 00408 * @retval None 00409 */ 00410 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 00411 00412 /** 00413 * @brief Enable the PVM2 Event Line. 00414 * @retval None 00415 */ 00416 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 00417 00418 /** 00419 * @brief Disable the PVM2 Event Line. 00420 * @retval None 00421 */ 00422 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 00423 00424 /** 00425 * @brief Enable the PVM2 Extended Interrupt Rising Trigger. 00426 * @retval None 00427 */ 00428 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 00429 00430 /** 00431 * @brief Disable the PVM2 Extended Interrupt Rising Trigger. 00432 * @retval None 00433 */ 00434 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 00435 00436 /** 00437 * @brief Enable the PVM2 Extended Interrupt Falling Trigger. 00438 * @retval None 00439 */ 00440 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 00441 00442 00443 /** 00444 * @brief Disable the PVM2 Extended Interrupt Falling Trigger. 00445 * @retval None 00446 */ 00447 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 00448 00449 00450 /** 00451 * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. 00452 * @retval None 00453 */ 00454 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ 00455 do { \ 00456 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ 00457 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ 00458 } while(0) 00459 00460 /** 00461 * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. 00462 * @retval None 00463 */ 00464 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ 00465 do { \ 00466 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ 00467 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ 00468 } while(0) 00469 00470 /** 00471 * @brief Generate a Software interrupt on selected EXTI line. 00472 * @retval None 00473 */ 00474 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) 00475 00476 /** 00477 * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. 00478 * @retval EXTI PVM2 Line Status. 00479 */ 00480 #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2) 00481 00482 /** 00483 * @brief Clear the PVM2 EXTI flag. 00484 * @retval None 00485 */ 00486 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2) 00487 00488 #endif /* PWR_CR2_PVME2 */ 00489 00490 00491 /** 00492 * @brief Enable the PVM3 Extended Interrupt Line. 00493 * @retval None 00494 */ 00495 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 00496 00497 /** 00498 * @brief Disable the PVM3 Extended Interrupt Line. 00499 * @retval None 00500 */ 00501 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 00502 00503 /** 00504 * @brief Enable the PVM3 Event Line. 00505 * @retval None 00506 */ 00507 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 00508 00509 /** 00510 * @brief Disable the PVM3 Event Line. 00511 * @retval None 00512 */ 00513 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 00514 00515 /** 00516 * @brief Enable the PVM3 Extended Interrupt Rising Trigger. 00517 * @retval None 00518 */ 00519 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 00520 00521 /** 00522 * @brief Disable the PVM3 Extended Interrupt Rising Trigger. 00523 * @retval None 00524 */ 00525 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 00526 00527 /** 00528 * @brief Enable the PVM3 Extended Interrupt Falling Trigger. 00529 * @retval None 00530 */ 00531 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 00532 00533 00534 /** 00535 * @brief Disable the PVM3 Extended Interrupt Falling Trigger. 00536 * @retval None 00537 */ 00538 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 00539 00540 00541 /** 00542 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. 00543 * @retval None 00544 */ 00545 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ 00546 do { \ 00547 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ 00548 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ 00549 } while(0) 00550 00551 /** 00552 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. 00553 * @retval None 00554 */ 00555 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ 00556 do { \ 00557 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ 00558 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ 00559 } while(0) 00560 00561 /** 00562 * @brief Generate a Software interrupt on selected EXTI line. 00563 * @retval None 00564 */ 00565 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) 00566 00567 /** 00568 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. 00569 * @retval EXTI PVM3 Line Status. 00570 */ 00571 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3) 00572 00573 /** 00574 * @brief Clear the PVM3 EXTI flag. 00575 * @retval None 00576 */ 00577 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3) 00578 00579 00580 00581 00582 /** 00583 * @brief Enable the PVM4 Extended Interrupt Line. 00584 * @retval None 00585 */ 00586 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 00587 00588 /** 00589 * @brief Disable the PVM4 Extended Interrupt Line. 00590 * @retval None 00591 */ 00592 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 00593 00594 /** 00595 * @brief Enable the PVM4 Event Line. 00596 * @retval None 00597 */ 00598 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 00599 00600 /** 00601 * @brief Disable the PVM4 Event Line. 00602 * @retval None 00603 */ 00604 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 00605 00606 /** 00607 * @brief Enable the PVM4 Extended Interrupt Rising Trigger. 00608 * @retval None 00609 */ 00610 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 00611 00612 /** 00613 * @brief Disable the PVM4 Extended Interrupt Rising Trigger. 00614 * @retval None 00615 */ 00616 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 00617 00618 /** 00619 * @brief Enable the PVM4 Extended Interrupt Falling Trigger. 00620 * @retval None 00621 */ 00622 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 00623 00624 00625 /** 00626 * @brief Disable the PVM4 Extended Interrupt Falling Trigger. 00627 * @retval None 00628 */ 00629 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 00630 00631 00632 /** 00633 * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. 00634 * @retval None 00635 */ 00636 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ 00637 do { \ 00638 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ 00639 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ 00640 } while(0) 00641 00642 /** 00643 * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. 00644 * @retval None 00645 */ 00646 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ 00647 do { \ 00648 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ 00649 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ 00650 } while(0) 00651 00652 /** 00653 * @brief Generate a Software interrupt on selected EXTI line. 00654 * @retval None 00655 */ 00656 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) 00657 00658 /** 00659 * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. 00660 * @retval EXTI PVM4 Line Status. 00661 */ 00662 #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4) 00663 00664 /** 00665 * @brief Clear the PVM4 EXTI flag. 00666 * @retval None 00667 */ 00668 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4) 00669 00670 00671 /** 00672 * @brief Configure the main internal regulator output voltage. 00673 * @param __REGULATOR__ specifies the regulator output voltage to achieve 00674 * a tradeoff between performance and power consumption. 00675 * This parameter can be one of the following values: 00676 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, 00677 * typical output voltage at 1.2 V, 00678 * system frequency up to 80 MHz. 00679 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, 00680 * typical output voltage at 1.0 V, 00681 * system frequency up to 26 MHz. 00682 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check 00683 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User 00684 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. 00685 * @retval None 00686 */ 00687 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ 00688 __IO uint32_t tmpreg; \ 00689 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ 00690 /* Delay after an RCC peripheral clock enabling */ \ 00691 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ 00692 UNUSED(tmpreg); \ 00693 } while(0) 00694 00695 /** 00696 * @} 00697 */ 00698 00699 /* Private macros --------------------------------------------------------*/ 00700 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 00701 * @{ 00702 */ 00703 00704 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 00705 ((PIN) == PWR_WAKEUP_PIN2) || \ 00706 ((PIN) == PWR_WAKEUP_PIN3) || \ 00707 ((PIN) == PWR_WAKEUP_PIN4) || \ 00708 ((PIN) == PWR_WAKEUP_PIN5) || \ 00709 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 00710 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ 00711 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ 00712 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ 00713 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ 00714 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 00715 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ 00716 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ 00717 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ 00718 ((PIN) == PWR_WAKEUP_PIN5_LOW)) 00719 00720 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00721 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00722 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 00723 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00724 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ 00725 ((TYPE) == PWR_PVM_2) ||\ 00726 ((TYPE) == PWR_PVM_3) ||\ 00727 ((TYPE) == PWR_PVM_4)) 00728 #elif defined (STM32L471xx) 00729 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\ 00730 ((TYPE) == PWR_PVM_3) ||\ 00731 ((TYPE) == PWR_PVM_4)) 00732 #endif 00733 00734 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx) 00735 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ 00736 ((TYPE) == PWR_PVM_3) ||\ 00737 ((TYPE) == PWR_PVM_4)) 00738 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx) 00739 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\ 00740 ((TYPE) == PWR_PVM_4)) 00741 #endif 00742 00743 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ 00744 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ 00745 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ 00746 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ 00747 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ 00748 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ 00749 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) 00750 00751 #if defined(PWR_CR5_R1MODE) 00752 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ 00753 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 00754 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 00755 #else 00756 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 00757 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 00758 #endif 00759 00760 00761 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 00762 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 00763 00764 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ 00765 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 00766 00767 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) 00768 00769 00770 #if defined (STM32L412xx) || defined (STM32L422xx) 00771 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 00772 ((GPIO) == PWR_GPIO_B) ||\ 00773 ((GPIO) == PWR_GPIO_C) ||\ 00774 ((GPIO) == PWR_GPIO_D) ||\ 00775 ((GPIO) == PWR_GPIO_H)) 00776 #elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \ 00777 defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 00778 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 00779 ((GPIO) == PWR_GPIO_B) ||\ 00780 ((GPIO) == PWR_GPIO_C) ||\ 00781 ((GPIO) == PWR_GPIO_D) ||\ 00782 ((GPIO) == PWR_GPIO_E) ||\ 00783 ((GPIO) == PWR_GPIO_H)) 00784 #elif defined (STM32L432xx) || defined (STM32L442xx) 00785 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 00786 ((GPIO) == PWR_GPIO_B) ||\ 00787 ((GPIO) == PWR_GPIO_C) ||\ 00788 ((GPIO) == PWR_GPIO_H)) 00789 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00790 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 00791 ((GPIO) == PWR_GPIO_B) ||\ 00792 ((GPIO) == PWR_GPIO_C) ||\ 00793 ((GPIO) == PWR_GPIO_D) ||\ 00794 ((GPIO) == PWR_GPIO_E) ||\ 00795 ((GPIO) == PWR_GPIO_F) ||\ 00796 ((GPIO) == PWR_GPIO_G) ||\ 00797 ((GPIO) == PWR_GPIO_H)) 00798 #elif defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00799 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 00800 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00801 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 00802 ((GPIO) == PWR_GPIO_B) ||\ 00803 ((GPIO) == PWR_GPIO_C) ||\ 00804 ((GPIO) == PWR_GPIO_D) ||\ 00805 ((GPIO) == PWR_GPIO_E) ||\ 00806 ((GPIO) == PWR_GPIO_F) ||\ 00807 ((GPIO) == PWR_GPIO_G) ||\ 00808 ((GPIO) == PWR_GPIO_H) ||\ 00809 ((GPIO) == PWR_GPIO_I)) 00810 #endif 00811 00812 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) 00813 #define IS_PWR_SRAM2_RETENTION(SRAM2) (((SRAM2) == PWR_NO_SRAM2_RETENTION) ||\ 00814 ((SRAM2) == PWR_FULL_SRAM2_RETENTION) ||\ 00815 ((SRAM2) == PWR_4KBYTES_SRAM2_RETENTION)) 00816 #else 00817 #define IS_PWR_SRAM2_RETENTION(SRAM2) (((SRAM2) == PWR_NO_SRAM2_RETENTION) ||\ 00818 ((SRAM2) == PWR_FULL_SRAM2_RETENTION)) 00819 #endif 00820 00821 /** 00822 * @} 00823 */ 00824 00825 00826 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 00827 * @{ 00828 */ 00829 00830 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 00831 * @{ 00832 */ 00833 00834 00835 /* Peripheral Control functions **********************************************/ 00836 uint32_t HAL_PWREx_GetVoltageRange(void); 00837 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 00838 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); 00839 void HAL_PWREx_DisableBatteryCharging(void); 00840 #if defined(PWR_CR2_USV) 00841 void HAL_PWREx_EnableVddUSB(void); 00842 void HAL_PWREx_DisableVddUSB(void); 00843 #endif /* PWR_CR2_USV */ 00844 #if defined(PWR_CR2_IOSV) 00845 void HAL_PWREx_EnableVddIO2(void); 00846 void HAL_PWREx_DisableVddIO2(void); 00847 #endif /* PWR_CR2_IOSV */ 00848 void HAL_PWREx_EnableInternalWakeUpLine(void); 00849 void HAL_PWREx_DisableInternalWakeUpLine(void); 00850 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 00851 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 00852 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 00853 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 00854 void HAL_PWREx_EnablePullUpPullDownConfig(void); 00855 void HAL_PWREx_DisablePullUpPullDownConfig(void); 00856 void HAL_PWREx_EnableSRAM2ContentRetention(void); 00857 void HAL_PWREx_DisableSRAM2ContentRetention(void); 00858 HAL_StatusTypeDef HAL_PWREx_SetSRAM2ContentRetention(uint32_t SRAM2Size); 00859 #if defined(PWR_CR1_RRSTP) 00860 void HAL_PWREx_EnableSRAM3ContentRetention(void); 00861 void HAL_PWREx_DisableSRAM3ContentRetention(void); 00862 #endif /* PWR_CR1_RRSTP */ 00863 #if defined(PWR_CR3_DSIPDEN) 00864 void HAL_PWREx_EnableDSIPinsPDActivation(void); 00865 void HAL_PWREx_DisableDSIPinsPDActivation(void); 00866 #endif /* PWR_CR3_DSIPDEN */ 00867 #if defined(PWR_CR2_PVME1) 00868 void HAL_PWREx_EnablePVM1(void); 00869 void HAL_PWREx_DisablePVM1(void); 00870 #endif /* PWR_CR2_PVME1 */ 00871 #if defined(PWR_CR2_PVME2) 00872 void HAL_PWREx_EnablePVM2(void); 00873 void HAL_PWREx_DisablePVM2(void); 00874 #endif /* PWR_CR2_PVME2 */ 00875 void HAL_PWREx_EnablePVM3(void); 00876 void HAL_PWREx_DisablePVM3(void); 00877 void HAL_PWREx_EnablePVM4(void); 00878 void HAL_PWREx_DisablePVM4(void); 00879 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); 00880 #if defined(PWR_CR3_ENULP) 00881 void HAL_PWREx_EnableBORPVD_ULP(void); 00882 void HAL_PWREx_DisableBORPVD_ULP(void); 00883 #endif /* PWR_CR3_ENULP */ 00884 #if defined(PWR_CR4_EXT_SMPS_ON) 00885 void HAL_PWREx_EnableExtSMPS_0V95(void); 00886 void HAL_PWREx_DisableExtSMPS_0V95(void); 00887 #endif /* PWR_CR4_EXT_SMPS_ON */ 00888 00889 00890 /* Low Power modes configuration functions ************************************/ 00891 void HAL_PWREx_EnableLowPowerRunMode(void); 00892 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); 00893 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); 00894 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); 00895 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); 00896 void HAL_PWREx_EnterSHUTDOWNMode(void); 00897 00898 void HAL_PWREx_PVD_PVM_IRQHandler(void); 00899 #if defined(PWR_CR2_PVME1) 00900 void HAL_PWREx_PVM1Callback(void); 00901 #endif /* PWR_CR2_PVME1 */ 00902 #if defined(PWR_CR2_PVME2) 00903 void HAL_PWREx_PVM2Callback(void); 00904 #endif /* PWR_CR2_PVME2 */ 00905 void HAL_PWREx_PVM3Callback(void); 00906 void HAL_PWREx_PVM4Callback(void); 00907 00908 /** 00909 * @} 00910 */ 00911 00912 /** 00913 * @} 00914 */ 00915 00916 /** 00917 * @} 00918 */ 00919 00920 /** 00921 * @} 00922 */ 00923 00924 #ifdef __cplusplus 00925 } 00926 #endif 00927 00928 00929 #endif /* STM32L4xx_HAL_PWR_EX_H */
1.7.6.1