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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_tsc.h 00004 * @author MCD Application Team 00005 * @brief Header file of TSC HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_TSC_H 00021 #define STM32L4xx_HAL_TSC_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx_hal_def.h" 00029 00030 00031 /** @addtogroup STM32L4xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup TSC 00036 * @{ 00037 */ 00038 00039 /* Exported types ------------------------------------------------------------*/ 00040 /** @defgroup TSC_Exported_Types TSC Exported Types 00041 * @{ 00042 */ 00043 00044 /** 00045 * @brief TSC state structure definition 00046 */ 00047 typedef enum 00048 { 00049 HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ 00050 HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ 00051 HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ 00052 HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ 00053 } HAL_TSC_StateTypeDef; 00054 00055 /** 00056 * @brief TSC group status structure definition 00057 */ 00058 typedef enum 00059 { 00060 TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ 00061 TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ 00062 } TSC_GroupStatusTypeDef; 00063 00064 /** 00065 * @brief TSC init structure definition 00066 */ 00067 typedef struct 00068 { 00069 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length 00070 This parameter can be a value of @ref TSC_CTPulseHL_Config */ 00071 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length 00072 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 00073 FunctionalState SpreadSpectrum; /*!< Spread spectrum activation 00074 This parameter can be set to ENABLE or DISABLE. */ 00075 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation 00076 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 00077 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler 00078 This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ 00079 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler 00080 This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ 00081 uint32_t MaxCountValue; /*!< Max count value 00082 This parameter can be a value of @ref TSC_MaxCount_Value */ 00083 uint32_t IODefaultMode; /*!< IO default mode 00084 This parameter can be a value of @ref TSC_IO_Default_Mode */ 00085 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity 00086 This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ 00087 uint32_t AcquisitionMode; /*!< Acquisition mode 00088 This parameter can be a value of @ref TSC_Acquisition_Mode */ 00089 FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation 00090 This parameter can be set to ENABLE or DISABLE. */ 00091 uint32_t ChannelIOs; /*!< Channel IOs mask */ 00092 uint32_t ShieldIOs; /*!< Shield IOs mask */ 00093 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 00094 } TSC_InitTypeDef; 00095 00096 /** 00097 * @brief TSC IOs configuration structure definition 00098 */ 00099 typedef struct 00100 { 00101 uint32_t ChannelIOs; /*!< Channel IOs mask */ 00102 uint32_t ShieldIOs; /*!< Shield IOs mask */ 00103 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 00104 } TSC_IOConfigTypeDef; 00105 00106 /** 00107 * @brief TSC handle Structure definition 00108 */ 00109 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 00110 typedef struct __TSC_HandleTypeDef 00111 #else 00112 typedef struct 00113 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 00114 { 00115 TSC_TypeDef *Instance; /*!< Register base address */ 00116 TSC_InitTypeDef Init; /*!< Initialization parameters */ 00117 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ 00118 HAL_LockTypeDef Lock; /*!< Lock feature */ 00119 __IO uint32_t ErrorCode; /*!< TSC Error code */ 00120 00121 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 00122 void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ 00123 void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ 00124 00125 void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ 00126 void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ 00127 00128 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 00129 } TSC_HandleTypeDef; 00130 00131 enum 00132 { 00133 TSC_GROUP1_IDX = 0x00UL, 00134 TSC_GROUP2_IDX, 00135 TSC_GROUP3_IDX, 00136 TSC_GROUP4_IDX, 00137 #if defined(TSC_IOCCR_G5_IO1) 00138 TSC_GROUP5_IDX, 00139 #endif /* TSC_IOCCR_G5_IO1 */ 00140 #if defined(TSC_IOCCR_G6_IO1) 00141 TSC_GROUP6_IDX, 00142 #endif /* TSC_IOCCR_G6_IO1 */ 00143 #if defined(TSC_IOCCR_G7_IO1) 00144 TSC_GROUP7_IDX, 00145 #endif /* TSC_IOCCR_G7_IO1 */ 00146 #if defined(TSC_IOCCR_G8_IO1) 00147 TSC_GROUP8_IDX, 00148 #endif /* TSC_IOCCR_G8_IO1 */ 00149 TSC_NB_OF_GROUPS 00150 }; 00151 00152 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 00153 /** 00154 * @brief HAL TSC Callback ID enumeration definition 00155 */ 00156 typedef enum 00157 { 00158 HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ 00159 HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ 00160 00161 HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ 00162 HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ 00163 00164 } HAL_TSC_CallbackIDTypeDef; 00165 00166 /** 00167 * @brief HAL TSC Callback pointer definition 00168 */ 00169 typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ 00170 00171 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 00172 00173 /** 00174 * @} 00175 */ 00176 00177 /* Exported constants --------------------------------------------------------*/ 00178 /** @defgroup TSC_Exported_Constants TSC Exported Constants 00179 * @{ 00180 */ 00181 00182 /** @defgroup TSC_Error_Code_definition TSC Error Code definition 00183 * @brief TSC Error Code definition 00184 * @{ 00185 */ 00186 #define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ 00187 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 00188 #define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ 00189 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 00190 /** 00191 * @} 00192 */ 00193 00194 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length 00195 * @{ 00196 */ 00197 #define TSC_CTPH_1CYCLE 0x00000000UL 00198 /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ 00199 #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 00200 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ 00201 #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 00202 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ 00203 #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 00204 /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ 00205 #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 00206 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ 00207 #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 00208 /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ 00209 #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 00210 /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ 00211 #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 00212 /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ 00213 #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 00214 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ 00215 #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) 00216 /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ 00217 #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) 00218 /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ 00219 #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 00220 /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ 00221 #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) 00222 /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ 00223 #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 00224 /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ 00225 #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 00226 /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ 00227 #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 00228 /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ 00229 /** 00230 * @} 00231 */ 00232 00233 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length 00234 * @{ 00235 */ 00236 #define TSC_CTPL_1CYCLE 0x00000000UL 00237 /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ 00238 #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 00239 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ 00240 #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 00241 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ 00242 #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 00243 /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ 00244 #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 00245 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ 00246 #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 00247 /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ 00248 #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 00249 /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ 00250 #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 00251 /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ 00252 #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 00253 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ 00254 #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) 00255 /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ 00256 #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) 00257 /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ 00258 #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 00259 /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ 00260 #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) 00261 /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ 00262 #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 00263 /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ 00264 #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 00265 /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ 00266 #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 00267 /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ 00268 /** 00269 * @} 00270 */ 00271 00272 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler 00273 * @{ 00274 */ 00275 #define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ 00276 #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ 00277 /** 00278 * @} 00279 */ 00280 00281 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler 00282 * @{ 00283 */ 00284 #define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ 00285 #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ 00286 #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ 00287 #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ 00288 #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ 00289 #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ 00290 #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ 00291 #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ 00292 /** 00293 * @} 00294 */ 00295 00296 /** @defgroup TSC_MaxCount_Value Max Count Value 00297 * @{ 00298 */ 00299 #define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ 00300 #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ 00301 #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ 00302 #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ 00303 #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ 00304 #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ 00305 #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ 00306 /** 00307 * @} 00308 */ 00309 00310 /** @defgroup TSC_IO_Default_Mode IO Default Mode 00311 * @{ 00312 */ 00313 #define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ 00314 #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ 00315 /** 00316 * @} 00317 */ 00318 00319 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity 00320 * @{ 00321 */ 00322 #define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ 00323 #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ 00324 /** 00325 * @} 00326 */ 00327 00328 /** @defgroup TSC_Acquisition_Mode Acquisition Mode 00329 * @{ 00330 */ 00331 #define TSC_ACQ_MODE_NORMAL 0x00000000UL 00332 /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ 00333 #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM 00334 /*!< Synchronized acquisition mode (acquisition starts if START bit is set and 00335 when the selected signal is detected on the SYNC input pin) */ 00336 /** 00337 * @} 00338 */ 00339 00340 /** @defgroup TSC_interrupts_definition Interrupts definition 00341 * @{ 00342 */ 00343 #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ 00344 #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ 00345 /** 00346 * @} 00347 */ 00348 00349 /** @defgroup TSC_flags_definition Flags definition 00350 * @{ 00351 */ 00352 #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ 00353 #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ 00354 /** 00355 * @} 00356 */ 00357 00358 /** @defgroup TSC_Group_definition Group definition 00359 * @{ 00360 */ 00361 #define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) 00362 #define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) 00363 #define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) 00364 #define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) 00365 #if defined(TSC_IOCCR_G5_IO1) 00366 #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) 00367 #endif /* TSC_IOCCR_G5_IO1 */ 00368 #if defined(TSC_IOCCR_G6_IO1) 00369 #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) 00370 #endif /* TSC_IOCCR_G6_IO1 */ 00371 #if defined(TSC_IOCCR_G7_IO1) 00372 #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) 00373 #endif /* TSC_IOCCR_G7_IO1 */ 00374 #if defined(TSC_IOCCR_G8_IO1) 00375 #define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) 00376 #endif /* TSC_IOCCR_G8_IO1 */ 00377 00378 #define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */ 00379 00380 #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ 00381 #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ 00382 #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ 00383 #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ 00384 00385 #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ 00386 #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ 00387 #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ 00388 #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ 00389 00390 #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ 00391 #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ 00392 #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ 00393 #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ 00394 00395 #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ 00396 #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ 00397 #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ 00398 #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ 00399 #if defined(TSC_IOCCR_G5_IO1) 00400 00401 #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ 00402 #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ 00403 #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ 00404 #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ 00405 #else 00406 00407 #define TSC_GROUP5_IO1 (uint32_t)(0x00000010UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group5 IO1 not supported */ 00408 #define TSC_GROUP5_IO2 TSC_GROUP5_IO1 /*!< TSC Group5 IO2 not supported */ 00409 #define TSC_GROUP5_IO3 TSC_GROUP5_IO1 /*!< TSC Group5 IO3 not supported */ 00410 #define TSC_GROUP5_IO4 TSC_GROUP5_IO1 /*!< TSC Group5 IO4 not supported */ 00411 #endif /* TSC_IOCCR_G5_IO1 */ 00412 #if defined(TSC_IOCCR_G6_IO1) 00413 00414 #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ 00415 #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ 00416 #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ 00417 #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ 00418 #else 00419 00420 #define TSC_GROUP6_IO1 (uint32_t)(0x00000020UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group6 IO1 not supported */ 00421 #define TSC_GROUP6_IO2 TSC_GROUP6_IO1 /*!< TSC Group6 IO2 not supported */ 00422 #define TSC_GROUP6_IO3 TSC_GROUP6_IO1 /*!< TSC Group6 IO3 not supported */ 00423 #define TSC_GROUP6_IO4 TSC_GROUP6_IO1 /*!< TSC Group6 IO4 not supported */ 00424 #endif /* TSC_IOCCR_G6_IO1 */ 00425 #if defined(TSC_IOCCR_G7_IO1) 00426 00427 #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ 00428 #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ 00429 #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ 00430 #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ 00431 #else 00432 00433 #define TSC_GROUP7_IO1 (uint32_t)(0x00000040UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group7 IO1 not supported */ 00434 #define TSC_GROUP7_IO2 TSC_GROUP7_IO1 /*!< TSC Group7 IO2 not supported */ 00435 #define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */ 00436 #define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */ 00437 #endif /* TSC_IOCCR_G7_IO1 */ 00438 #if defined(TSC_IOCCR_G8_IO1) 00439 00440 #define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ 00441 #define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ 00442 #define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ 00443 #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ 00444 #else 00445 00446 #define TSC_GROUP8_IO1 (uint32_t)(0x00000080UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ 00447 #define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ 00448 #define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ 00449 #define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ 00450 #endif /* TSC_IOCCR_G8_IO1 */ 00451 /** 00452 * @} 00453 */ 00454 00455 /** 00456 * @} 00457 */ 00458 00459 /* Exported macros -----------------------------------------------------------*/ 00460 00461 /** @defgroup TSC_Exported_Macros TSC Exported Macros 00462 * @{ 00463 */ 00464 00465 /** @brief Reset TSC handle state. 00466 * @param __HANDLE__ TSC handle 00467 * @retval None 00468 */ 00469 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 00470 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00471 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ 00472 (__HANDLE__)->MspInitCallback = NULL; \ 00473 (__HANDLE__)->MspDeInitCallback = NULL; \ 00474 } while(0) 00475 #else 00476 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 00477 #endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */ 00478 00479 /** 00480 * @brief Enable the TSC peripheral. 00481 * @param __HANDLE__ TSC handle 00482 * @retval None 00483 */ 00484 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 00485 00486 /** 00487 * @brief Disable the TSC peripheral. 00488 * @param __HANDLE__ TSC handle 00489 * @retval None 00490 */ 00491 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) 00492 00493 /** 00494 * @brief Start acquisition. 00495 * @param __HANDLE__ TSC handle 00496 * @retval None 00497 */ 00498 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 00499 00500 /** 00501 * @brief Stop acquisition. 00502 * @param __HANDLE__ TSC handle 00503 * @retval None 00504 */ 00505 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) 00506 00507 /** 00508 * @brief Set IO default mode to output push-pull low. 00509 * @param __HANDLE__ TSC handle 00510 * @retval None 00511 */ 00512 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) 00513 00514 /** 00515 * @brief Set IO default mode to input floating. 00516 * @param __HANDLE__ TSC handle 00517 * @retval None 00518 */ 00519 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 00520 00521 /** 00522 * @brief Set synchronization polarity to falling edge. 00523 * @param __HANDLE__ TSC handle 00524 * @retval None 00525 */ 00526 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) 00527 00528 /** 00529 * @brief Set synchronization polarity to rising edge and high level. 00530 * @param __HANDLE__ TSC handle 00531 * @retval None 00532 */ 00533 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 00534 00535 /** 00536 * @brief Enable TSC interrupt. 00537 * @param __HANDLE__ TSC handle 00538 * @param __INTERRUPT__ TSC interrupt 00539 * @retval None 00540 */ 00541 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 00542 00543 /** 00544 * @brief Disable TSC interrupt. 00545 * @param __HANDLE__ TSC handle 00546 * @param __INTERRUPT__ TSC interrupt 00547 * @retval None 00548 */ 00549 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 00550 00551 /** @brief Check whether the specified TSC interrupt source is enabled or not. 00552 * @param __HANDLE__ TSC Handle 00553 * @param __INTERRUPT__ TSC interrupt 00554 * @retval SET or RESET 00555 */ 00556 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ 00557 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\ 00558 RESET) 00559 00560 /** 00561 * @brief Check whether the specified TSC flag is set or not. 00562 * @param __HANDLE__ TSC handle 00563 * @param __FLAG__ TSC flag 00564 * @retval SET or RESET 00565 */ 00566 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\ 00567 & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 00568 00569 /** 00570 * @brief Clear the TSC's pending flag. 00571 * @param __HANDLE__ TSC handle 00572 * @param __FLAG__ TSC flag 00573 * @retval None 00574 */ 00575 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 00576 00577 /** 00578 * @brief Enable schmitt trigger hysteresis on a group of IOs. 00579 * @param __HANDLE__ TSC handle 00580 * @param __GX_IOY_MASK__ IOs mask 00581 * @retval None 00582 */ 00583 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 00584 00585 /** 00586 * @brief Disable schmitt trigger hysteresis on a group of IOs. 00587 * @param __HANDLE__ TSC handle 00588 * @param __GX_IOY_MASK__ IOs mask 00589 * @retval None 00590 */ 00591 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\ 00592 &= (~(__GX_IOY_MASK__))) 00593 00594 /** 00595 * @brief Open analog switch on a group of IOs. 00596 * @param __HANDLE__ TSC handle 00597 * @param __GX_IOY_MASK__ IOs mask 00598 * @retval None 00599 */ 00600 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\ 00601 &= (~(__GX_IOY_MASK__))) 00602 00603 /** 00604 * @brief Close analog switch on a group of IOs. 00605 * @param __HANDLE__ TSC handle 00606 * @param __GX_IOY_MASK__ IOs mask 00607 * @retval None 00608 */ 00609 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 00610 00611 /** 00612 * @brief Enable a group of IOs in channel mode. 00613 * @param __HANDLE__ TSC handle 00614 * @param __GX_IOY_MASK__ IOs mask 00615 * @retval None 00616 */ 00617 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 00618 00619 /** 00620 * @brief Disable a group of channel IOs. 00621 * @param __HANDLE__ TSC handle 00622 * @param __GX_IOY_MASK__ IOs mask 00623 * @retval None 00624 */ 00625 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\ 00626 &= (~(__GX_IOY_MASK__))) 00627 00628 /** 00629 * @brief Enable a group of IOs in sampling mode. 00630 * @param __HANDLE__ TSC handle 00631 * @param __GX_IOY_MASK__ IOs mask 00632 * @retval None 00633 */ 00634 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 00635 00636 /** 00637 * @brief Disable a group of sampling IOs. 00638 * @param __HANDLE__ TSC handle 00639 * @param __GX_IOY_MASK__ IOs mask 00640 * @retval None 00641 */ 00642 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) 00643 00644 /** 00645 * @brief Enable acquisition groups. 00646 * @param __HANDLE__ TSC handle 00647 * @param __GX_MASK__ Groups mask 00648 * @retval None 00649 */ 00650 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 00651 00652 /** 00653 * @brief Disable acquisition groups. 00654 * @param __HANDLE__ TSC handle 00655 * @param __GX_MASK__ Groups mask 00656 * @retval None 00657 */ 00658 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) 00659 00660 /** @brief Gets acquisition group status. 00661 * @param __HANDLE__ TSC Handle 00662 * @param __GX_INDEX__ Group index 00663 * @retval SET or RESET 00664 */ 00665 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 00666 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \ 00667 (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 00668 00669 /** 00670 * @} 00671 */ 00672 00673 /* Private macros ------------------------------------------------------------*/ 00674 00675 /** @defgroup TSC_Private_Macros TSC Private Macros 00676 * @{ 00677 */ 00678 00679 #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ 00680 ((__VALUE__) == TSC_CTPH_2CYCLES) || \ 00681 ((__VALUE__) == TSC_CTPH_3CYCLES) || \ 00682 ((__VALUE__) == TSC_CTPH_4CYCLES) || \ 00683 ((__VALUE__) == TSC_CTPH_5CYCLES) || \ 00684 ((__VALUE__) == TSC_CTPH_6CYCLES) || \ 00685 ((__VALUE__) == TSC_CTPH_7CYCLES) || \ 00686 ((__VALUE__) == TSC_CTPH_8CYCLES) || \ 00687 ((__VALUE__) == TSC_CTPH_9CYCLES) || \ 00688 ((__VALUE__) == TSC_CTPH_10CYCLES) || \ 00689 ((__VALUE__) == TSC_CTPH_11CYCLES) || \ 00690 ((__VALUE__) == TSC_CTPH_12CYCLES) || \ 00691 ((__VALUE__) == TSC_CTPH_13CYCLES) || \ 00692 ((__VALUE__) == TSC_CTPH_14CYCLES) || \ 00693 ((__VALUE__) == TSC_CTPH_15CYCLES) || \ 00694 ((__VALUE__) == TSC_CTPH_16CYCLES)) 00695 00696 #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ 00697 ((__VALUE__) == TSC_CTPL_2CYCLES) || \ 00698 ((__VALUE__) == TSC_CTPL_3CYCLES) || \ 00699 ((__VALUE__) == TSC_CTPL_4CYCLES) || \ 00700 ((__VALUE__) == TSC_CTPL_5CYCLES) || \ 00701 ((__VALUE__) == TSC_CTPL_6CYCLES) || \ 00702 ((__VALUE__) == TSC_CTPL_7CYCLES) || \ 00703 ((__VALUE__) == TSC_CTPL_8CYCLES) || \ 00704 ((__VALUE__) == TSC_CTPL_9CYCLES) || \ 00705 ((__VALUE__) == TSC_CTPL_10CYCLES) || \ 00706 ((__VALUE__) == TSC_CTPL_11CYCLES) || \ 00707 ((__VALUE__) == TSC_CTPL_12CYCLES) || \ 00708 ((__VALUE__) == TSC_CTPL_13CYCLES) || \ 00709 ((__VALUE__) == TSC_CTPL_14CYCLES) || \ 00710 ((__VALUE__) == TSC_CTPL_15CYCLES) || \ 00711 ((__VALUE__) == TSC_CTPL_16CYCLES)) 00712 00713 #define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 00714 || ((FunctionalState)(__VALUE__) == ENABLE)) 00715 00716 #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) 00717 00718 #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) 00719 00720 #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ 00721 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ 00722 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ 00723 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ 00724 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ 00725 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ 00726 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ 00727 ((__VALUE__) == TSC_PG_PRESC_DIV128)) 00728 00729 #define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \ 00730 ((__CTPL__) > TSC_CTPL_2CYCLES)) || \ 00731 (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \ 00732 ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ 00733 (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \ 00734 (((__CTPL__) == TSC_CTPL_1CYCLE) || \ 00735 ((__CTPL__) > TSC_CTPL_1CYCLE)))) 00736 00737 #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ 00738 ((__VALUE__) == TSC_MCV_511) || \ 00739 ((__VALUE__) == TSC_MCV_1023) || \ 00740 ((__VALUE__) == TSC_MCV_2047) || \ 00741 ((__VALUE__) == TSC_MCV_4095) || \ 00742 ((__VALUE__) == TSC_MCV_8191) || \ 00743 ((__VALUE__) == TSC_MCV_16383)) 00744 00745 #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) 00746 00747 #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\ 00748 || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) 00749 00750 #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) 00751 00752 #define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 00753 || ((FunctionalState)(__VALUE__) == ENABLE)) 00754 00755 #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ 00756 || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) 00757 00758 00759 #define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ 00760 (((__VALUE__) == 0UL) ||\ 00761 (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ 00762 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ 00763 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ 00764 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ 00765 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ 00766 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ 00767 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ 00768 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ 00769 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ 00770 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ 00771 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ 00772 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ 00773 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ 00774 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ 00775 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ 00776 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ 00777 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ 00778 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ 00779 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ 00780 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ 00781 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ 00782 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ 00783 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ 00784 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ 00785 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ 00786 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ 00787 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ 00788 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ 00789 (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ 00790 (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ 00791 (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ 00792 (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) 00793 00794 /** 00795 * @} 00796 */ 00797 00798 /* Exported functions --------------------------------------------------------*/ 00799 /** @addtogroup TSC_Exported_Functions 00800 * @{ 00801 */ 00802 00803 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions 00804 * @{ 00805 */ 00806 /* Initialization and de-initialization functions *****************************/ 00807 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); 00808 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); 00809 void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); 00810 void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); 00811 00812 /* Callbacks Register/UnRegister functions ***********************************/ 00813 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 00814 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, 00815 pTSC_CallbackTypeDef pCallback); 00816 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); 00817 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 00818 /** 00819 * @} 00820 */ 00821 00822 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions 00823 * @{ 00824 */ 00825 /* IO operation functions *****************************************************/ 00826 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); 00827 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); 00828 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); 00829 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); 00830 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); 00831 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index); 00832 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); 00833 /** 00834 * @} 00835 */ 00836 00837 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions 00838 * @{ 00839 */ 00840 /* Peripheral Control functions ***********************************************/ 00841 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config); 00842 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); 00843 /** 00844 * @} 00845 */ 00846 00847 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions 00848 * @{ 00849 */ 00850 /* Peripheral State and Error functions ***************************************/ 00851 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); 00852 /** 00853 * @} 00854 */ 00855 00856 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 00857 * @{ 00858 */ 00859 /******* TSC IRQHandler and Callbacks used in Interrupt mode */ 00860 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); 00861 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); 00862 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); 00863 /** 00864 * @} 00865 */ 00866 00867 /** 00868 * @} 00869 */ 00870 00871 /** 00872 * @} 00873 */ 00874 00875 /** 00876 * @} 00877 */ 00878 00879 #ifdef __cplusplus 00880 } 00881 #endif 00882 00883 #endif /* STM32L4xx_HAL_TSC_H */
1.7.6.1