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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_cortex.h 00004 * @author MCD Application Team 00005 * @brief Header file of CORTEX LL module. 00006 @verbatim 00007 ============================================================================== 00008 ##### How to use this driver ##### 00009 ============================================================================== 00010 [..] 00011 The LL CORTEX driver contains a set of generic APIs that can be 00012 used by user: 00013 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick 00014 functions 00015 (+) Low power mode configuration (SCB register of Cortex-MCU) 00016 (+) MPU API to configure and enable regions 00017 (+) API to access to MCU info (CPUID register) 00018 (+) API to enable fault handler (SHCSR accesses) 00019 00020 @endverbatim 00021 ****************************************************************************** 00022 * @attention 00023 * 00024 * Copyright (c) 2017 STMicroelectronics. 00025 * All rights reserved. 00026 * 00027 * This software is licensed under terms that can be found in the LICENSE file in 00028 * the root directory of this software component. 00029 * If no LICENSE file comes with this software, it is provided AS-IS. 00030 * 00031 ****************************************************************************** 00032 */ 00033 00034 /* Define to prevent recursive inclusion -------------------------------------*/ 00035 #ifndef STM32L4xx_LL_CORTEX_H 00036 #define STM32L4xx_LL_CORTEX_H 00037 00038 #ifdef __cplusplus 00039 extern "C" { 00040 #endif 00041 00042 /* Includes ------------------------------------------------------------------*/ 00043 #include "stm32l4xx.h" 00044 00045 /** @addtogroup STM32L4xx_LL_Driver 00046 * @{ 00047 */ 00048 00049 /** @defgroup CORTEX_LL CORTEX 00050 * @{ 00051 */ 00052 00053 /* Private types -------------------------------------------------------------*/ 00054 /* Private variables ---------------------------------------------------------*/ 00055 00056 /* Private constants ---------------------------------------------------------*/ 00057 00058 /* Private macros ------------------------------------------------------------*/ 00059 00060 /* Exported types ------------------------------------------------------------*/ 00061 /* Exported constants --------------------------------------------------------*/ 00062 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants 00063 * @{ 00064 */ 00065 00066 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source 00067 * @{ 00068 */ 00069 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ 00070 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ 00071 /** 00072 * @} 00073 */ 00074 00075 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type 00076 * @{ 00077 */ 00078 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ 00079 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ 00080 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ 00081 /** 00082 * @} 00083 */ 00084 00085 #if __MPU_PRESENT 00086 00087 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control 00088 * @{ 00089 */ 00090 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ 00091 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ 00092 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ 00093 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ 00094 /** 00095 * @} 00096 */ 00097 00098 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number 00099 * @{ 00100 */ 00101 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ 00102 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ 00103 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ 00104 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ 00105 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ 00106 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ 00107 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ 00108 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ 00109 /** 00110 * @} 00111 */ 00112 00113 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size 00114 * @{ 00115 */ 00116 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ 00117 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ 00118 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ 00119 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ 00120 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ 00121 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ 00122 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ 00123 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ 00124 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ 00125 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ 00126 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ 00127 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ 00128 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ 00129 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ 00130 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ 00131 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ 00132 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ 00133 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ 00134 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ 00135 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ 00136 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ 00137 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ 00138 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ 00139 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ 00140 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ 00141 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ 00142 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ 00143 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ 00144 /** 00145 * @} 00146 */ 00147 00148 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges 00149 * @{ 00150 */ 00151 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ 00152 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ 00153 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ 00154 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ 00155 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ 00156 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ 00157 /** 00158 * @} 00159 */ 00160 00161 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level 00162 * @{ 00163 */ 00164 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ 00165 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ 00166 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ 00167 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ 00168 /** 00169 * @} 00170 */ 00171 00172 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access 00173 * @{ 00174 */ 00175 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ 00176 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ 00177 /** 00178 * @} 00179 */ 00180 00181 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access 00182 * @{ 00183 */ 00184 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ 00185 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ 00186 /** 00187 * @} 00188 */ 00189 00190 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access 00191 * @{ 00192 */ 00193 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ 00194 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ 00195 /** 00196 * @} 00197 */ 00198 00199 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access 00200 * @{ 00201 */ 00202 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ 00203 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ 00204 /** 00205 * @} 00206 */ 00207 #endif /* __MPU_PRESENT */ 00208 /** 00209 * @} 00210 */ 00211 00212 /* Exported macro ------------------------------------------------------------*/ 00213 00214 /* Exported functions --------------------------------------------------------*/ 00215 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions 00216 * @{ 00217 */ 00218 00219 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK 00220 * @{ 00221 */ 00222 00223 /** 00224 * @brief This function checks if the Systick counter flag is active or not. 00225 * @note It can be used in timeout function on application side. 00226 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag 00227 * @retval State of bit (1 or 0). 00228 */ 00229 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) 00230 { 00231 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); 00232 } 00233 00234 /** 00235 * @brief Configures the SysTick clock source 00236 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource 00237 * @param Source This parameter can be one of the following values: 00238 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 00239 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK 00240 * @retval None 00241 */ 00242 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) 00243 { 00244 if (Source == LL_SYSTICK_CLKSOURCE_HCLK) 00245 { 00246 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 00247 } 00248 else 00249 { 00250 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 00251 } 00252 } 00253 00254 /** 00255 * @brief Get the SysTick clock source 00256 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource 00257 * @retval Returned value can be one of the following values: 00258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 00259 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK 00260 */ 00261 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) 00262 { 00263 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 00264 } 00265 00266 /** 00267 * @brief Enable SysTick exception request 00268 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT 00269 * @retval None 00270 */ 00271 __STATIC_INLINE void LL_SYSTICK_EnableIT(void) 00272 { 00273 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 00274 } 00275 00276 /** 00277 * @brief Disable SysTick exception request 00278 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT 00279 * @retval None 00280 */ 00281 __STATIC_INLINE void LL_SYSTICK_DisableIT(void) 00282 { 00283 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 00284 } 00285 00286 /** 00287 * @brief Checks if the SYSTICK interrupt is enabled or disabled. 00288 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT 00289 * @retval State of bit (1 or 0). 00290 */ 00291 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) 00292 { 00293 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); 00294 } 00295 00296 /** 00297 * @} 00298 */ 00299 00300 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE 00301 * @{ 00302 */ 00303 00304 /** 00305 * @brief Processor uses sleep as its low power mode 00306 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep 00307 * @retval None 00308 */ 00309 __STATIC_INLINE void LL_LPM_EnableSleep(void) 00310 { 00311 /* Clear SLEEPDEEP bit of Cortex System Control Register */ 00312 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00313 } 00314 00315 /** 00316 * @brief Processor uses deep sleep as its low power mode 00317 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep 00318 * @retval None 00319 */ 00320 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) 00321 { 00322 /* Set SLEEPDEEP bit of Cortex System Control Register */ 00323 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00324 } 00325 00326 /** 00327 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. 00328 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an 00329 * empty main application. 00330 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit 00331 * @retval None 00332 */ 00333 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) 00334 { 00335 /* Set SLEEPONEXIT bit of Cortex System Control Register */ 00336 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 00337 } 00338 00339 /** 00340 * @brief Do not sleep when returning to Thread mode. 00341 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit 00342 * @retval None 00343 */ 00344 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) 00345 { 00346 /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 00347 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 00348 } 00349 00350 /** 00351 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the 00352 * processor. 00353 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend 00354 * @retval None 00355 */ 00356 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) 00357 { 00358 /* Set SEVEONPEND bit of Cortex System Control Register */ 00359 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 00360 } 00361 00362 /** 00363 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are 00364 * excluded 00365 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend 00366 * @retval None 00367 */ 00368 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) 00369 { 00370 /* Clear SEVEONPEND bit of Cortex System Control Register */ 00371 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 00372 } 00373 00374 /** 00375 * @} 00376 */ 00377 00378 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER 00379 * @{ 00380 */ 00381 00382 /** 00383 * @brief Enable a fault in System handler control register (SHCSR) 00384 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault 00385 * @param Fault This parameter can be a combination of the following values: 00386 * @arg @ref LL_HANDLER_FAULT_USG 00387 * @arg @ref LL_HANDLER_FAULT_BUS 00388 * @arg @ref LL_HANDLER_FAULT_MEM 00389 * @retval None 00390 */ 00391 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) 00392 { 00393 /* Enable the system handler fault */ 00394 SET_BIT(SCB->SHCSR, Fault); 00395 } 00396 00397 /** 00398 * @brief Disable a fault in System handler control register (SHCSR) 00399 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault 00400 * @param Fault This parameter can be a combination of the following values: 00401 * @arg @ref LL_HANDLER_FAULT_USG 00402 * @arg @ref LL_HANDLER_FAULT_BUS 00403 * @arg @ref LL_HANDLER_FAULT_MEM 00404 * @retval None 00405 */ 00406 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) 00407 { 00408 /* Disable the system handler fault */ 00409 CLEAR_BIT(SCB->SHCSR, Fault); 00410 } 00411 00412 /** 00413 * @} 00414 */ 00415 00416 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO 00417 * @{ 00418 */ 00419 00420 /** 00421 * @brief Get Implementer code 00422 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer 00423 * @retval Value should be equal to 0x41 for ARM 00424 */ 00425 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) 00426 { 00427 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); 00428 } 00429 00430 /** 00431 * @brief Get Variant number (The r value in the rnpn product revision identifier) 00432 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant 00433 * @retval Value between 0 and 255 (0x0: revision 0) 00434 */ 00435 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) 00436 { 00437 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); 00438 } 00439 00440 /** 00441 * @brief Get Constant number 00442 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant 00443 * @retval Value should be equal to 0xF for Cortex-M4 devices 00444 */ 00445 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) 00446 { 00447 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); 00448 } 00449 00450 /** 00451 * @brief Get Part number 00452 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo 00453 * @retval Value should be equal to 0xC24 for Cortex-M4 00454 */ 00455 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) 00456 { 00457 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); 00458 } 00459 00460 /** 00461 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) 00462 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision 00463 * @retval Value between 0 and 255 (0x1: patch 1) 00464 */ 00465 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) 00466 { 00467 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); 00468 } 00469 00470 /** 00471 * @} 00472 */ 00473 00474 #if __MPU_PRESENT 00475 /** @defgroup CORTEX_LL_EF_MPU MPU 00476 * @{ 00477 */ 00478 00479 /** 00480 * @brief Enable MPU with input options 00481 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable 00482 * @param Options This parameter can be one of the following values: 00483 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 00484 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI 00485 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT 00486 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF 00487 * @retval None 00488 */ 00489 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) 00490 { 00491 /* Enable the MPU*/ 00492 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); 00493 /* Ensure MPU settings take effects */ 00494 __DSB(); 00495 /* Sequence instruction fetches using update settings */ 00496 __ISB(); 00497 } 00498 00499 /** 00500 * @brief Disable MPU 00501 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable 00502 * @retval None 00503 */ 00504 __STATIC_INLINE void LL_MPU_Disable(void) 00505 { 00506 /* Make sure outstanding transfers are done */ 00507 __DMB(); 00508 /* Disable MPU*/ 00509 WRITE_REG(MPU->CTRL, 0U); 00510 } 00511 00512 /** 00513 * @brief Check if MPU is enabled or not 00514 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled 00515 * @retval State of bit (1 or 0). 00516 */ 00517 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) 00518 { 00519 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); 00520 } 00521 00522 /** 00523 * @brief Enable a MPU region 00524 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion 00525 * @param Region This parameter can be one of the following values: 00526 * @arg @ref LL_MPU_REGION_NUMBER0 00527 * @arg @ref LL_MPU_REGION_NUMBER1 00528 * @arg @ref LL_MPU_REGION_NUMBER2 00529 * @arg @ref LL_MPU_REGION_NUMBER3 00530 * @arg @ref LL_MPU_REGION_NUMBER4 00531 * @arg @ref LL_MPU_REGION_NUMBER5 00532 * @arg @ref LL_MPU_REGION_NUMBER6 00533 * @arg @ref LL_MPU_REGION_NUMBER7 00534 * @retval None 00535 */ 00536 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) 00537 { 00538 /* Set Region number */ 00539 WRITE_REG(MPU->RNR, Region); 00540 /* Enable the MPU region */ 00541 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 00542 } 00543 00544 /** 00545 * @brief Configure and enable a region 00546 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n 00547 * MPU_RBAR REGION LL_MPU_ConfigRegion\n 00548 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n 00549 * MPU_RASR XN LL_MPU_ConfigRegion\n 00550 * MPU_RASR AP LL_MPU_ConfigRegion\n 00551 * MPU_RASR S LL_MPU_ConfigRegion\n 00552 * MPU_RASR C LL_MPU_ConfigRegion\n 00553 * MPU_RASR B LL_MPU_ConfigRegion\n 00554 * MPU_RASR SIZE LL_MPU_ConfigRegion 00555 * @param Region This parameter can be one of the following values: 00556 * @arg @ref LL_MPU_REGION_NUMBER0 00557 * @arg @ref LL_MPU_REGION_NUMBER1 00558 * @arg @ref LL_MPU_REGION_NUMBER2 00559 * @arg @ref LL_MPU_REGION_NUMBER3 00560 * @arg @ref LL_MPU_REGION_NUMBER4 00561 * @arg @ref LL_MPU_REGION_NUMBER5 00562 * @arg @ref LL_MPU_REGION_NUMBER6 00563 * @arg @ref LL_MPU_REGION_NUMBER7 00564 * @param Address Value of region base address 00565 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF 00566 * @param Attributes This parameter can be a combination of the following values: 00567 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B 00568 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB 00569 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB 00570 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB 00571 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB 00572 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB 00573 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS 00574 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO 00575 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 00576 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE 00577 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE 00578 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE 00579 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE 00580 * @retval None 00581 */ 00582 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) 00583 { 00584 /* Set Region number */ 00585 WRITE_REG(MPU->RNR, Region); 00586 /* Set base address */ 00587 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); 00588 /* Configure MPU */ 00589 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); 00590 } 00591 00592 /** 00593 * @brief Disable a region 00594 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n 00595 * MPU_RASR ENABLE LL_MPU_DisableRegion 00596 * @param Region This parameter can be one of the following values: 00597 * @arg @ref LL_MPU_REGION_NUMBER0 00598 * @arg @ref LL_MPU_REGION_NUMBER1 00599 * @arg @ref LL_MPU_REGION_NUMBER2 00600 * @arg @ref LL_MPU_REGION_NUMBER3 00601 * @arg @ref LL_MPU_REGION_NUMBER4 00602 * @arg @ref LL_MPU_REGION_NUMBER5 00603 * @arg @ref LL_MPU_REGION_NUMBER6 00604 * @arg @ref LL_MPU_REGION_NUMBER7 00605 * @retval None 00606 */ 00607 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) 00608 { 00609 /* Set Region number */ 00610 WRITE_REG(MPU->RNR, Region); 00611 /* Disable the MPU region */ 00612 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 00613 } 00614 00615 /** 00616 * @} 00617 */ 00618 00619 #endif /* __MPU_PRESENT */ 00620 /** 00621 * @} 00622 */ 00623 00624 /** 00625 * @} 00626 */ 00627 00628 /** 00629 * @} 00630 */ 00631 00632 #ifdef __cplusplus 00633 } 00634 #endif 00635 00636 #endif /* STM32L4xx_LL_CORTEX_H */ 00637
1.7.6.1