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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_pwr.h 00004 * @author MCD Application Team 00005 * @brief Header file of PWR LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_LL_PWR_H 00021 #define STM32L4xx_LL_PWR_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx.h" 00029 00030 /** @addtogroup STM32L4xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined(PWR) 00035 00036 /** @defgroup PWR_LL PWR 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 00043 /* Private constants ---------------------------------------------------------*/ 00044 00045 /* Private macros ------------------------------------------------------------*/ 00046 00047 /* Exported types ------------------------------------------------------------*/ 00048 /* Exported constants --------------------------------------------------------*/ 00049 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants 00050 * @{ 00051 */ 00052 00053 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines 00054 * @brief Flags defines which can be used with LL_PWR_WriteReg function 00055 * @{ 00056 */ 00057 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF 00058 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF 00059 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5 00060 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4 00061 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 00062 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 00063 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 00064 /** 00065 * @} 00066 */ 00067 00068 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines 00069 * @brief Flags defines which can be used with LL_PWR_ReadReg function 00070 * @{ 00071 */ 00072 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI 00073 #if defined(PWR_SR1_EXT_SMPS_RDY) 00074 #define LL_PWR_SR1_EXT_SMPS_RDY PWR_SR1_EXT_SMPS_RDY 00075 #endif /* PWR_SR1_EXT_SMPS_RDY */ 00076 #define LL_PWR_SR1_SBF PWR_SR1_SBF 00077 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 00078 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 00079 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 00080 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 00081 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 00082 #if defined(PWR_SR2_PVMO4) 00083 #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4 00084 #endif /* PWR_SR2_PVMO4 */ 00085 #if defined(PWR_SR2_PVMO3) 00086 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3 00087 #endif /* PWR_SR2_PVMO3 */ 00088 #if defined(PWR_SR2_PVMO2) 00089 #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2 00090 #endif /* PWR_SR2_PVMO2 */ 00091 #if defined(PWR_SR2_PVMO1) 00092 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1 00093 #endif /* PWR_SR2_PVMO1 */ 00094 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO 00095 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF 00096 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF 00097 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS 00098 /** 00099 * @} 00100 */ 00101 00102 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE 00103 * @{ 00104 */ 00105 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) 00106 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) 00107 /** 00108 * @} 00109 */ 00110 00111 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR 00112 * @{ 00113 */ 00114 #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0) 00115 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1) 00116 #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2) 00117 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY) 00118 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN) 00119 /** 00120 * @} 00121 */ 00122 00123 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring 00124 * @{ 00125 */ 00126 #if defined(PWR_CR2_PVME1) 00127 #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */ 00128 #endif 00129 #if defined(PWR_CR2_PVME2) 00130 #define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */ 00131 #endif 00132 #if defined(PWR_CR2_PVME3) 00133 #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */ 00134 #endif 00135 #if defined(PWR_CR2_PVME4) 00136 #define LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */ 00137 #endif 00138 /** 00139 * @} 00140 */ 00141 00142 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL 00143 * @{ 00144 */ 00145 #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */ 00146 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */ 00147 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */ 00148 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */ 00149 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */ 00150 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */ 00151 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */ 00152 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */ 00153 /** 00154 * @} 00155 */ 00156 00157 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP 00158 * @{ 00159 */ 00160 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1) 00161 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) 00162 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) 00163 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4) 00164 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5) 00165 /** 00166 * @} 00167 */ 00168 00169 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR 00170 * @{ 00171 */ 00172 #define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U) 00173 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS) 00174 /** 00175 * @} 00176 */ 00177 00178 /** @defgroup PWR_LL_EC_SRAM2_CONTENT_RETENTION SRAM2 CONTENT RETENTION 00179 * @{ 00180 */ 00181 #define LL_PWR_NO_SRAM2_RETENTION (0x00000000U) 00182 #if defined(PWR_CR3_RRS_1) 00183 #define LL_PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS_0 00184 #define LL_PWR_4KBYTES_SRAM2_RETENTION PWR_CR3_RRS_1 00185 #else 00186 #define LL_PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS 00187 #endif /* PWR_CR3_RRS_1 */ 00188 /** 00189 * @} 00190 */ 00191 00192 /** @defgroup PWR_LL_EC_GPIO GPIO 00193 * @{ 00194 */ 00195 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA))) 00196 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB))) 00197 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC))) 00198 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD))) 00199 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE))) 00200 #if defined(GPIOF) 00201 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF))) 00202 #endif 00203 #if defined(GPIOG) 00204 #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG))) 00205 #endif 00206 #if defined(GPIOH) 00207 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH))) 00208 #endif 00209 #if defined(GPIOI) 00210 #define LL_PWR_GPIO_I ((uint32_t)(&(PWR->PUCRI))) 00211 #endif 00212 /** 00213 * @} 00214 */ 00215 00216 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT 00217 * @{ 00218 */ 00219 #define LL_PWR_GPIO_BIT_0 (0x00000001U) 00220 #define LL_PWR_GPIO_BIT_1 (0x00000002U) 00221 #define LL_PWR_GPIO_BIT_2 (0x00000004U) 00222 #define LL_PWR_GPIO_BIT_3 (0x00000008U) 00223 #define LL_PWR_GPIO_BIT_4 (0x00000010U) 00224 #define LL_PWR_GPIO_BIT_5 (0x00000020U) 00225 #define LL_PWR_GPIO_BIT_6 (0x00000040U) 00226 #define LL_PWR_GPIO_BIT_7 (0x00000080U) 00227 #define LL_PWR_GPIO_BIT_8 (0x00000100U) 00228 #define LL_PWR_GPIO_BIT_9 (0x00000200U) 00229 #define LL_PWR_GPIO_BIT_10 (0x00000400U) 00230 #define LL_PWR_GPIO_BIT_11 (0x00000800U) 00231 #define LL_PWR_GPIO_BIT_12 (0x00001000U) 00232 #define LL_PWR_GPIO_BIT_13 (0x00002000U) 00233 #define LL_PWR_GPIO_BIT_14 (0x00004000U) 00234 #define LL_PWR_GPIO_BIT_15 (0x00008000U) 00235 /** 00236 * @} 00237 */ 00238 00239 /** 00240 * @} 00241 */ 00242 00243 /* Exported macro ------------------------------------------------------------*/ 00244 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros 00245 * @{ 00246 */ 00247 00248 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros 00249 * @{ 00250 */ 00251 00252 /** 00253 * @brief Write a value in PWR register 00254 * @param __REG__ Register to be written 00255 * @param __VALUE__ Value to be written in the register 00256 * @retval None 00257 */ 00258 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) 00259 00260 /** 00261 * @brief Read a value in PWR register 00262 * @param __REG__ Register to be read 00263 * @retval Register value 00264 */ 00265 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) 00266 /** 00267 * @} 00268 */ 00269 00270 /** 00271 * @} 00272 */ 00273 00274 00275 /* Exported functions --------------------------------------------------------*/ 00276 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions 00277 * @{ 00278 */ 00279 00280 /** @defgroup PWR_LL_EF_Configuration Configuration 00281 * @{ 00282 */ 00283 00284 /** 00285 * @brief Switch the regulator from main mode to low-power mode 00286 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode 00287 * @retval None 00288 */ 00289 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) 00290 { 00291 SET_BIT(PWR->CR1, PWR_CR1_LPR); 00292 } 00293 00294 /** 00295 * @brief Switch the regulator from low-power mode to main mode 00296 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode 00297 * @retval None 00298 */ 00299 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) 00300 { 00301 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); 00302 } 00303 00304 /** 00305 * @brief Switch from run main mode to run low-power mode. 00306 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode 00307 * @retval None 00308 */ 00309 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) 00310 { 00311 LL_PWR_EnableLowPowerRunMode(); 00312 } 00313 00314 /** 00315 * @brief Switch from run main mode to low-power mode. 00316 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode 00317 * @retval None 00318 */ 00319 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) 00320 { 00321 LL_PWR_DisableLowPowerRunMode(); 00322 } 00323 00324 /** 00325 * @brief Check if the regulator is in low-power mode 00326 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode 00327 * @retval State of bit (1 or 0). 00328 */ 00329 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) 00330 { 00331 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL); 00332 } 00333 00334 /** 00335 * @brief Set the main internal regulator output voltage 00336 * @note This configuration may be completed with LL_PWR_EnableRange1BoostMode() on STM32L4Rx/STM32L4Sx devices. 00337 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling 00338 * @param VoltageScaling This parameter can be one of the following values: 00339 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 00340 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 00341 * @retval None 00342 */ 00343 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) 00344 { 00345 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); 00346 } 00347 00348 /** 00349 * @brief Get the main internal regulator output voltage 00350 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling 00351 * @retval Returned value can be one of the following values: 00352 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 00353 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 00354 */ 00355 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) 00356 { 00357 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); 00358 } 00359 00360 #if defined(PWR_CR5_R1MODE) 00361 /** 00362 * @brief Enable main regulator voltage range 1 boost mode 00363 * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode 00364 * @retval None 00365 */ 00366 __STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void) 00367 { 00368 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 00369 } 00370 00371 /** 00372 * @brief Disable main regulator voltage range 1 boost mode 00373 * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode 00374 * @retval None 00375 */ 00376 __STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void) 00377 { 00378 SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 00379 } 00380 00381 /** 00382 * @brief Check if the main regulator voltage range 1 boost mode is enabled 00383 * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode 00384 * @retval Inverted state of bit (0 or 1). 00385 */ 00386 __STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void) 00387 { 00388 return ((READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == 0x0U) ? 1UL : 0UL); 00389 } 00390 #endif /* PWR_CR5_R1MODE */ 00391 00392 /** 00393 * @brief Enable access to the backup domain 00394 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess 00395 * @retval None 00396 */ 00397 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) 00398 { 00399 SET_BIT(PWR->CR1, PWR_CR1_DBP); 00400 } 00401 00402 /** 00403 * @brief Disable access to the backup domain 00404 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess 00405 * @retval None 00406 */ 00407 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) 00408 { 00409 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); 00410 } 00411 00412 /** 00413 * @brief Check if the backup domain is enabled 00414 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess 00415 * @retval State of bit (1 or 0). 00416 */ 00417 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) 00418 { 00419 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); 00420 } 00421 00422 /** 00423 * @brief Set Low-Power mode 00424 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode 00425 * @param LowPowerMode This parameter can be one of the following values: 00426 * @arg @ref LL_PWR_MODE_STOP0 00427 * @arg @ref LL_PWR_MODE_STOP1 00428 * @arg @ref LL_PWR_MODE_STOP2 00429 * @arg @ref LL_PWR_MODE_STANDBY 00430 * @arg @ref LL_PWR_MODE_SHUTDOWN 00431 * @retval None 00432 */ 00433 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) 00434 { 00435 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); 00436 } 00437 00438 /** 00439 * @brief Get Low-Power mode 00440 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode 00441 * @retval Returned value can be one of the following values: 00442 * @arg @ref LL_PWR_MODE_STOP0 00443 * @arg @ref LL_PWR_MODE_STOP1 00444 * @arg @ref LL_PWR_MODE_STOP2 00445 * @arg @ref LL_PWR_MODE_STANDBY 00446 * @arg @ref LL_PWR_MODE_SHUTDOWN 00447 */ 00448 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) 00449 { 00450 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); 00451 } 00452 00453 #if defined(PWR_CR1_RRSTP) 00454 /** 00455 * @brief Enable SRAM3 content retention in Stop mode 00456 * @rmtoll CR1 RRSTP LL_PWR_EnableSRAM3Retention 00457 * @retval None 00458 */ 00459 __STATIC_INLINE void LL_PWR_EnableSRAM3Retention(void) 00460 { 00461 SET_BIT(PWR->CR1, PWR_CR1_RRSTP); 00462 } 00463 00464 /** 00465 * @brief Disable SRAM3 content retention in Stop mode 00466 * @rmtoll CR1 RRSTP LL_PWR_DisableSRAM3Retention 00467 * @retval None 00468 */ 00469 __STATIC_INLINE void LL_PWR_DisableSRAM3Retention(void) 00470 { 00471 CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP); 00472 } 00473 00474 /** 00475 * @brief Check if SRAM3 content retention in Stop mode is enabled 00476 * @rmtoll CR1 RRSTP LL_PWR_IsEnabledSRAM3Retention 00477 * @retval State of bit (1 or 0). 00478 */ 00479 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM3Retention(void) 00480 { 00481 return ((READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)) ? 1UL : 0UL); 00482 } 00483 #endif /* PWR_CR1_RRSTP */ 00484 00485 #if defined(PWR_CR3_DSIPDEN) 00486 /** 00487 * @brief Enable pull-down activation on DSI pins 00488 * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPinsPDActivation 00489 * @retval None 00490 */ 00491 __STATIC_INLINE void LL_PWR_EnableDSIPinsPDActivation(void) 00492 { 00493 SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); 00494 } 00495 00496 /** 00497 * @brief Disable pull-down activation on DSI pins 00498 * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPinsPDActivation 00499 * @retval None 00500 */ 00501 __STATIC_INLINE void LL_PWR_DisableDSIPinsPDActivation(void) 00502 { 00503 CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); 00504 } 00505 00506 /** 00507 * @brief Check if pull-down activation on DSI pins is enabled 00508 * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPinsPDActivation 00509 * @retval State of bit (1 or 0). 00510 */ 00511 __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPinsPDActivation(void) 00512 { 00513 return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL); 00514 } 00515 #endif /* PWR_CR3_DSIPDEN */ 00516 00517 #if defined(PWR_CR2_USV) 00518 /** 00519 * @brief Enable VDDUSB supply 00520 * @rmtoll CR2 USV LL_PWR_EnableVddUSB 00521 * @retval None 00522 */ 00523 __STATIC_INLINE void LL_PWR_EnableVddUSB(void) 00524 { 00525 SET_BIT(PWR->CR2, PWR_CR2_USV); 00526 } 00527 00528 /** 00529 * @brief Disable VDDUSB supply 00530 * @rmtoll CR2 USV LL_PWR_DisableVddUSB 00531 * @retval None 00532 */ 00533 __STATIC_INLINE void LL_PWR_DisableVddUSB(void) 00534 { 00535 CLEAR_BIT(PWR->CR2, PWR_CR2_USV); 00536 } 00537 00538 /** 00539 * @brief Check if VDDUSB supply is enabled 00540 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB 00541 * @retval State of bit (1 or 0). 00542 */ 00543 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) 00544 { 00545 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL); 00546 } 00547 #endif 00548 00549 #if defined(PWR_CR2_IOSV) 00550 /** 00551 * @brief Enable VDDIO2 supply 00552 * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2 00553 * @retval None 00554 */ 00555 __STATIC_INLINE void LL_PWR_EnableVddIO2(void) 00556 { 00557 SET_BIT(PWR->CR2, PWR_CR2_IOSV); 00558 } 00559 00560 /** 00561 * @brief Disable VDDIO2 supply 00562 * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2 00563 * @retval None 00564 */ 00565 __STATIC_INLINE void LL_PWR_DisableVddIO2(void) 00566 { 00567 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); 00568 } 00569 00570 /** 00571 * @brief Check if VDDIO2 supply is enabled 00572 * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2 00573 * @retval State of bit (1 or 0). 00574 */ 00575 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) 00576 { 00577 return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL); 00578 } 00579 #endif 00580 00581 /** 00582 * @brief Enable the Power Voltage Monitoring on a peripheral 00583 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n 00584 * CR2 PVME2 LL_PWR_EnablePVM\n 00585 * CR2 PVME3 LL_PWR_EnablePVM\n 00586 * CR2 PVME4 LL_PWR_EnablePVM 00587 * @param PeriphVoltage This parameter can be one of the following values: 00588 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) 00589 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) 00590 * @arg @ref LL_PWR_PVM_VDDA_1_62V 00591 * @arg @ref LL_PWR_PVM_VDDA_2_2V 00592 * 00593 * (*) value not defined in all devices 00594 * @retval None 00595 */ 00596 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) 00597 { 00598 SET_BIT(PWR->CR2, PeriphVoltage); 00599 } 00600 00601 /** 00602 * @brief Disable the Power Voltage Monitoring on a peripheral 00603 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n 00604 * CR2 PVME2 LL_PWR_DisablePVM\n 00605 * CR2 PVME3 LL_PWR_DisablePVM\n 00606 * CR2 PVME4 LL_PWR_DisablePVM 00607 * @param PeriphVoltage This parameter can be one of the following values: 00608 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) 00609 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) 00610 * @arg @ref LL_PWR_PVM_VDDA_1_62V 00611 * @arg @ref LL_PWR_PVM_VDDA_2_2V 00612 * 00613 * (*) value not defined in all devices 00614 * @retval None 00615 */ 00616 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) 00617 { 00618 CLEAR_BIT(PWR->CR2, PeriphVoltage); 00619 } 00620 00621 /** 00622 * @brief Check if Power Voltage Monitoring is enabled on a peripheral 00623 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n 00624 * CR2 PVME2 LL_PWR_IsEnabledPVM\n 00625 * CR2 PVME3 LL_PWR_IsEnabledPVM\n 00626 * CR2 PVME4 LL_PWR_IsEnabledPVM 00627 * @param PeriphVoltage This parameter can be one of the following values: 00628 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) 00629 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) 00630 * @arg @ref LL_PWR_PVM_VDDA_1_62V 00631 * @arg @ref LL_PWR_PVM_VDDA_2_2V 00632 * 00633 * (*) value not defined in all devices 00634 * @retval State of bit (1 or 0). 00635 */ 00636 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) 00637 { 00638 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); 00639 } 00640 00641 /** 00642 * @brief Configure the voltage threshold detected by the Power Voltage Detector 00643 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel 00644 * @param PVDLevel This parameter can be one of the following values: 00645 * @arg @ref LL_PWR_PVDLEVEL_0 00646 * @arg @ref LL_PWR_PVDLEVEL_1 00647 * @arg @ref LL_PWR_PVDLEVEL_2 00648 * @arg @ref LL_PWR_PVDLEVEL_3 00649 * @arg @ref LL_PWR_PVDLEVEL_4 00650 * @arg @ref LL_PWR_PVDLEVEL_5 00651 * @arg @ref LL_PWR_PVDLEVEL_6 00652 * @arg @ref LL_PWR_PVDLEVEL_7 00653 * @retval None 00654 */ 00655 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) 00656 { 00657 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel); 00658 } 00659 00660 /** 00661 * @brief Get the voltage threshold detection 00662 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel 00663 * @retval Returned value can be one of the following values: 00664 * @arg @ref LL_PWR_PVDLEVEL_0 00665 * @arg @ref LL_PWR_PVDLEVEL_1 00666 * @arg @ref LL_PWR_PVDLEVEL_2 00667 * @arg @ref LL_PWR_PVDLEVEL_3 00668 * @arg @ref LL_PWR_PVDLEVEL_4 00669 * @arg @ref LL_PWR_PVDLEVEL_5 00670 * @arg @ref LL_PWR_PVDLEVEL_6 00671 * @arg @ref LL_PWR_PVDLEVEL_7 00672 */ 00673 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) 00674 { 00675 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS)); 00676 } 00677 00678 /** 00679 * @brief Enable Power Voltage Detector 00680 * @rmtoll CR2 PVDE LL_PWR_EnablePVD 00681 * @retval None 00682 */ 00683 __STATIC_INLINE void LL_PWR_EnablePVD(void) 00684 { 00685 SET_BIT(PWR->CR2, PWR_CR2_PVDE); 00686 } 00687 00688 /** 00689 * @brief Disable Power Voltage Detector 00690 * @rmtoll CR2 PVDE LL_PWR_DisablePVD 00691 * @retval None 00692 */ 00693 __STATIC_INLINE void LL_PWR_DisablePVD(void) 00694 { 00695 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); 00696 } 00697 00698 /** 00699 * @brief Check if Power Voltage Detector is enabled 00700 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD 00701 * @retval State of bit (1 or 0). 00702 */ 00703 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) 00704 { 00705 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); 00706 } 00707 00708 /** 00709 * @brief Enable Internal Wake-up line 00710 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU 00711 * @retval None 00712 */ 00713 __STATIC_INLINE void LL_PWR_EnableInternWU(void) 00714 { 00715 SET_BIT(PWR->CR3, PWR_CR3_EIWF); 00716 } 00717 00718 /** 00719 * @brief Disable Internal Wake-up line 00720 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU 00721 * @retval None 00722 */ 00723 __STATIC_INLINE void LL_PWR_DisableInternWU(void) 00724 { 00725 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); 00726 } 00727 00728 /** 00729 * @brief Check if Internal Wake-up line is enabled 00730 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU 00731 * @retval State of bit (1 or 0). 00732 */ 00733 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) 00734 { 00735 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)) ? 1UL : 0UL); 00736 } 00737 00738 /** 00739 * @brief Enable pull-up and pull-down configuration 00740 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg 00741 * @retval None 00742 */ 00743 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void) 00744 { 00745 SET_BIT(PWR->CR3, PWR_CR3_APC); 00746 } 00747 00748 /** 00749 * @brief Disable pull-up and pull-down configuration 00750 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg 00751 * @retval None 00752 */ 00753 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) 00754 { 00755 CLEAR_BIT(PWR->CR3, PWR_CR3_APC); 00756 } 00757 00758 /** 00759 * @brief Check if pull-up and pull-down configuration is enabled 00760 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg 00761 * @retval State of bit (1 or 0). 00762 */ 00763 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) 00764 { 00765 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL); 00766 } 00767 00768 #if defined(PWR_CR3_DSIPDEN) 00769 /** 00770 * @brief Enable pull-down activation on DSI pins 00771 * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPullDown 00772 * @retval None 00773 */ 00774 __STATIC_INLINE void LL_PWR_EnableDSIPullDown(void) 00775 { 00776 SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); 00777 } 00778 00779 /** 00780 * @brief Disable pull-down activation on DSI pins 00781 * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPullDown 00782 * @retval None 00783 */ 00784 __STATIC_INLINE void LL_PWR_DisableDSIPullDown(void) 00785 { 00786 CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); 00787 } 00788 00789 /** 00790 * @brief Check if pull-down activation on DSI pins is enabled 00791 * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPullDown 00792 * @retval State of bit (1 or 0). 00793 */ 00794 __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPullDown(void) 00795 { 00796 return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL); 00797 } 00798 #endif /* PWR_CR3_DSIPDEN */ 00799 00800 #if defined(PWR_CR3_ENULP) 00801 /** 00802 * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes 00803 * @rmtoll CR3 ENULP LL_PWR_EnableBORPVD_ULP 00804 * @retval None 00805 */ 00806 __STATIC_INLINE void LL_PWR_EnableBORPVD_ULP(void) 00807 { 00808 SET_BIT(PWR->CR3, PWR_CR3_ENULP); 00809 } 00810 00811 /** 00812 * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes 00813 * @rmtoll CR3 ENULP LL_PWR_DisableBORPVD_ULP 00814 * @retval None 00815 */ 00816 __STATIC_INLINE void LL_PWR_DisableBORPVD_ULP(void) 00817 { 00818 CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP); 00819 } 00820 00821 /** 00822 * @brief Check if Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes is enabled 00823 * @rmtoll CR3 ENULP LL_PWR_IsEnabledBORPVD_ULP 00824 * @retval State of bit (1 or 0). 00825 */ 00826 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBORPVD_ULP(void) 00827 { 00828 return ((READ_BIT(PWR->CR3, PWR_CR3_ENULP) == (PWR_CR3_ENULP)) ? 1UL : 0UL); 00829 } 00830 #endif /* PWR_CR3_ENULP */ 00831 00832 /** 00833 * @brief Enable SRAM2 full content retention in Standby mode 00834 * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention 00835 * @retval None 00836 */ 00837 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void) 00838 { 00839 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, LL_PWR_FULL_SRAM2_RETENTION); 00840 } 00841 00842 /** 00843 * @brief Disable SRAM2 content retention in Standby mode 00844 * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention 00845 * @retval None 00846 */ 00847 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) 00848 { 00849 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); 00850 } 00851 00852 /** 00853 * @brief Check if SRAM2 full content retention in Standby mode is enabled 00854 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention 00855 * @retval State of bit (1 or 0). 00856 */ 00857 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) 00858 { 00859 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (LL_PWR_FULL_SRAM2_RETENTION)) ? 1UL : 0UL); 00860 } 00861 00862 /** 00863 * @brief Set SRAM2 content retention in Standby mode 00864 * @rmtoll CR3 RRS LL_PWR_SetSRAM2ContentRetention 00865 * @param SRAM2Size This parameter can be one of the following values: 00866 * @arg @ref LL_PWR_NO_SRAM2_RETENTION 00867 * @arg @ref LL_PWR_FULL_SRAM2_RETENTION 00868 * @arg @ref LL_PWR_4KBYTES_SRAM2_RETENTION 00869 * @note LL_PWR_4KBYTES_SRAM2_RETENTION parameter is not available on all devices 00870 * @note Setting LL_PWR_NO_SRAM2_RETENTION is same as calling LL_PWR_DisableSRAM2Retention() 00871 * @note Setting LL_PWR_FULL_SRAM2_RETENTION is same as calling LL_PWR_EnableSRAM2Retention() 00872 * @retval None 00873 */ 00874 __STATIC_INLINE void LL_PWR_SetSRAM2ContentRetention(uint32_t SRAM2Size) 00875 { 00876 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2Size); 00877 } 00878 00879 /** 00880 * @brief Get SRAM2 content retention in Standby mode 00881 * @rmtoll CR3 RRS LL_PWR_GetSRAM2ContentRetention 00882 * @retval Returned value can be one of the following values: 00883 * @arg @ref LL_PWR_NO_SRAM2_RETENTION 00884 * @arg @ref LL_PWR_FULL_SRAM2_RETENTION 00885 * @arg @ref LL_PWR_4KBYTES_SRAM2_RETENTION 00886 * @note LL_PWR_4KBYTES_SRAM2_RETENTION parameter is not available on all devices 00887 */ 00888 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2ContentRetention(void) 00889 { 00890 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS)); 00891 } 00892 00893 /** 00894 * @brief Enable the WakeUp PINx functionality 00895 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n 00896 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n 00897 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n 00898 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n 00899 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n 00900 * @param WakeUpPin This parameter can be one of the following values: 00901 * @arg @ref LL_PWR_WAKEUP_PIN1 00902 * @arg @ref LL_PWR_WAKEUP_PIN2 00903 * @arg @ref LL_PWR_WAKEUP_PIN3 00904 * @arg @ref LL_PWR_WAKEUP_PIN4 00905 * @arg @ref LL_PWR_WAKEUP_PIN5 00906 * @retval None 00907 */ 00908 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) 00909 { 00910 SET_BIT(PWR->CR3, WakeUpPin); 00911 } 00912 00913 /** 00914 * @brief Disable the WakeUp PINx functionality 00915 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n 00916 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n 00917 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n 00918 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n 00919 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n 00920 * @param WakeUpPin This parameter can be one of the following values: 00921 * @arg @ref LL_PWR_WAKEUP_PIN1 00922 * @arg @ref LL_PWR_WAKEUP_PIN2 00923 * @arg @ref LL_PWR_WAKEUP_PIN3 00924 * @arg @ref LL_PWR_WAKEUP_PIN4 00925 * @arg @ref LL_PWR_WAKEUP_PIN5 00926 * @retval None 00927 */ 00928 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) 00929 { 00930 CLEAR_BIT(PWR->CR3, WakeUpPin); 00931 } 00932 00933 /** 00934 * @brief Check if the WakeUp PINx functionality is enabled 00935 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n 00936 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n 00937 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n 00938 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n 00939 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n 00940 * @param WakeUpPin This parameter can be one of the following values: 00941 * @arg @ref LL_PWR_WAKEUP_PIN1 00942 * @arg @ref LL_PWR_WAKEUP_PIN2 00943 * @arg @ref LL_PWR_WAKEUP_PIN3 00944 * @arg @ref LL_PWR_WAKEUP_PIN4 00945 * @arg @ref LL_PWR_WAKEUP_PIN5 00946 * @retval State of bit (1 or 0). 00947 */ 00948 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) 00949 { 00950 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); 00951 } 00952 00953 #if defined(PWR_CR4_EXT_SMPS_ON) 00954 /** 00955 * @brief Enable the CFLDO working @ 0.95V 00956 * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the 00957 * internal CFLDO can be reduced to 0.95V. 00958 * @rmtoll CR4 EXT_SMPS_ON LL_PWR_EnableExtSMPS_0V95 00959 * @retval None 00960 */ 00961 __STATIC_INLINE void LL_PWR_EnableExtSMPS_0V95(void) 00962 { 00963 SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON); 00964 } 00965 00966 /** 00967 * @brief Disable the CFLDO working @ 0.95V 00968 * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the 00969 * internal CFLDO can be reduced to 0.95V. 00970 * @rmtoll CR4 EXT_SMPS_ON LL_PWR_DisableExtSMPS_0V95 00971 * @retval None 00972 */ 00973 __STATIC_INLINE void LL_PWR_DisableExtSMPS_0V95(void) 00974 { 00975 CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON); 00976 } 00977 00978 /** 00979 * @brief Check if CFLDO is working @ 0.95V 00980 * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the 00981 * internal CFLDO can be reduced to 0.95V. 00982 * @rmtoll CR4 EXT_SMPS_ON LL_PWR_IsEnabledExtSMPS_0V95 00983 * @retval State of bit (1 or 0). 00984 */ 00985 __STATIC_INLINE uint32_t LL_PWR_IsEnabledExtSMPS_0V95(void) 00986 { 00987 return ((READ_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON) == (PWR_CR4_EXT_SMPS_ON)) ? 1UL : 0UL); 00988 } 00989 #endif /* PWR_CR4_EXT_SMPS_ON */ 00990 00991 /** 00992 * @brief Set the resistor impedance 00993 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor 00994 * @param Resistor This parameter can be one of the following values: 00995 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K 00996 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K 00997 * @retval None 00998 */ 00999 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) 01000 { 01001 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); 01002 } 01003 01004 /** 01005 * @brief Get the resistor impedance 01006 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor 01007 * @retval Returned value can be one of the following values: 01008 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K 01009 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K 01010 */ 01011 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) 01012 { 01013 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); 01014 } 01015 01016 /** 01017 * @brief Enable battery charging 01018 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging 01019 * @retval None 01020 */ 01021 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) 01022 { 01023 SET_BIT(PWR->CR4, PWR_CR4_VBE); 01024 } 01025 01026 /** 01027 * @brief Disable battery charging 01028 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging 01029 * @retval None 01030 */ 01031 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) 01032 { 01033 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); 01034 } 01035 01036 /** 01037 * @brief Check if battery charging is enabled 01038 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging 01039 * @retval State of bit (1 or 0). 01040 */ 01041 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) 01042 { 01043 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL); 01044 } 01045 01046 /** 01047 * @brief Set the Wake-Up pin polarity low for the event detection 01048 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n 01049 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n 01050 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n 01051 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n 01052 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow 01053 * @param WakeUpPin This parameter can be one of the following values: 01054 * @arg @ref LL_PWR_WAKEUP_PIN1 01055 * @arg @ref LL_PWR_WAKEUP_PIN2 01056 * @arg @ref LL_PWR_WAKEUP_PIN3 01057 * @arg @ref LL_PWR_WAKEUP_PIN4 01058 * @arg @ref LL_PWR_WAKEUP_PIN5 01059 * @retval None 01060 */ 01061 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) 01062 { 01063 SET_BIT(PWR->CR4, WakeUpPin); 01064 } 01065 01066 /** 01067 * @brief Set the Wake-Up pin polarity high for the event detection 01068 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n 01069 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n 01070 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n 01071 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n 01072 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh 01073 * @param WakeUpPin This parameter can be one of the following values: 01074 * @arg @ref LL_PWR_WAKEUP_PIN1 01075 * @arg @ref LL_PWR_WAKEUP_PIN2 01076 * @arg @ref LL_PWR_WAKEUP_PIN3 01077 * @arg @ref LL_PWR_WAKEUP_PIN4 01078 * @arg @ref LL_PWR_WAKEUP_PIN5 01079 * @retval None 01080 */ 01081 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) 01082 { 01083 CLEAR_BIT(PWR->CR4, WakeUpPin); 01084 } 01085 01086 /** 01087 * @brief Get the Wake-Up pin polarity for the event detection 01088 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n 01089 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n 01090 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n 01091 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n 01092 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow 01093 * @param WakeUpPin This parameter can be one of the following values: 01094 * @arg @ref LL_PWR_WAKEUP_PIN1 01095 * @arg @ref LL_PWR_WAKEUP_PIN2 01096 * @arg @ref LL_PWR_WAKEUP_PIN3 01097 * @arg @ref LL_PWR_WAKEUP_PIN4 01098 * @arg @ref LL_PWR_WAKEUP_PIN5 01099 * @retval State of bit (1 or 0). 01100 */ 01101 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) 01102 { 01103 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); 01104 } 01105 01106 /** 01107 * @brief Enable GPIO pull-up state in Standby and Shutdown modes 01108 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n 01109 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n 01110 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n 01111 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n 01112 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n 01113 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n 01114 * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n 01115 * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp\n 01116 * PUCRI PU0-11 LL_PWR_EnableGPIOPullUp 01117 * @param GPIO This parameter can be one of the following values: 01118 * @arg @ref LL_PWR_GPIO_A 01119 * @arg @ref LL_PWR_GPIO_B 01120 * @arg @ref LL_PWR_GPIO_C 01121 * @arg @ref LL_PWR_GPIO_D 01122 * @arg @ref LL_PWR_GPIO_E 01123 * @arg @ref LL_PWR_GPIO_F (*) 01124 * @arg @ref LL_PWR_GPIO_G (*) 01125 * @arg @ref LL_PWR_GPIO_H 01126 * @arg @ref LL_PWR_GPIO_I (*) 01127 * 01128 * (*) value not defined in all devices 01129 * @param GPIONumber This parameter can be one of the following values: 01130 * @arg @ref LL_PWR_GPIO_BIT_0 01131 * @arg @ref LL_PWR_GPIO_BIT_1 01132 * @arg @ref LL_PWR_GPIO_BIT_2 01133 * @arg @ref LL_PWR_GPIO_BIT_3 01134 * @arg @ref LL_PWR_GPIO_BIT_4 01135 * @arg @ref LL_PWR_GPIO_BIT_5 01136 * @arg @ref LL_PWR_GPIO_BIT_6 01137 * @arg @ref LL_PWR_GPIO_BIT_7 01138 * @arg @ref LL_PWR_GPIO_BIT_8 01139 * @arg @ref LL_PWR_GPIO_BIT_9 01140 * @arg @ref LL_PWR_GPIO_BIT_10 01141 * @arg @ref LL_PWR_GPIO_BIT_11 01142 * @arg @ref LL_PWR_GPIO_BIT_12 01143 * @arg @ref LL_PWR_GPIO_BIT_13 01144 * @arg @ref LL_PWR_GPIO_BIT_14 01145 * @arg @ref LL_PWR_GPIO_BIT_15 01146 * @retval None 01147 */ 01148 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 01149 { 01150 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber); 01151 } 01152 01153 /** 01154 * @brief Disable GPIO pull-up state in Standby and Shutdown modes 01155 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n 01156 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n 01157 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n 01158 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n 01159 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n 01160 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n 01161 * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n 01162 * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp\n 01163 * PUCRI PU0-11 LL_PWR_DisableGPIOPullUp 01164 * @param GPIO This parameter can be one of the following values: 01165 * @arg @ref LL_PWR_GPIO_A 01166 * @arg @ref LL_PWR_GPIO_B 01167 * @arg @ref LL_PWR_GPIO_C 01168 * @arg @ref LL_PWR_GPIO_D 01169 * @arg @ref LL_PWR_GPIO_E 01170 * @arg @ref LL_PWR_GPIO_F (*) 01171 * @arg @ref LL_PWR_GPIO_G (*) 01172 * @arg @ref LL_PWR_GPIO_H 01173 * @arg @ref LL_PWR_GPIO_I (*) 01174 * 01175 * (*) value not defined in all devices 01176 * @param GPIONumber This parameter can be one of the following values: 01177 * @arg @ref LL_PWR_GPIO_BIT_0 01178 * @arg @ref LL_PWR_GPIO_BIT_1 01179 * @arg @ref LL_PWR_GPIO_BIT_2 01180 * @arg @ref LL_PWR_GPIO_BIT_3 01181 * @arg @ref LL_PWR_GPIO_BIT_4 01182 * @arg @ref LL_PWR_GPIO_BIT_5 01183 * @arg @ref LL_PWR_GPIO_BIT_6 01184 * @arg @ref LL_PWR_GPIO_BIT_7 01185 * @arg @ref LL_PWR_GPIO_BIT_8 01186 * @arg @ref LL_PWR_GPIO_BIT_9 01187 * @arg @ref LL_PWR_GPIO_BIT_10 01188 * @arg @ref LL_PWR_GPIO_BIT_11 01189 * @arg @ref LL_PWR_GPIO_BIT_12 01190 * @arg @ref LL_PWR_GPIO_BIT_13 01191 * @arg @ref LL_PWR_GPIO_BIT_14 01192 * @arg @ref LL_PWR_GPIO_BIT_15 01193 * @retval None 01194 */ 01195 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 01196 { 01197 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber); 01198 } 01199 01200 /** 01201 * @brief Check if GPIO pull-up state is enabled 01202 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01203 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01204 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01205 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01206 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01207 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01208 * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01209 * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01210 * PUCRI PU0-11 LL_PWR_IsEnabledGPIOPullUp 01211 * @param GPIO This parameter can be one of the following values: 01212 * @arg @ref LL_PWR_GPIO_A 01213 * @arg @ref LL_PWR_GPIO_B 01214 * @arg @ref LL_PWR_GPIO_C 01215 * @arg @ref LL_PWR_GPIO_D 01216 * @arg @ref LL_PWR_GPIO_E 01217 * @arg @ref LL_PWR_GPIO_F (*) 01218 * @arg @ref LL_PWR_GPIO_G (*) 01219 * @arg @ref LL_PWR_GPIO_H 01220 * @arg @ref LL_PWR_GPIO_I (*) 01221 * 01222 * (*) value not defined in all devices 01223 * @param GPIONumber This parameter can be one of the following values: 01224 * @arg @ref LL_PWR_GPIO_BIT_0 01225 * @arg @ref LL_PWR_GPIO_BIT_1 01226 * @arg @ref LL_PWR_GPIO_BIT_2 01227 * @arg @ref LL_PWR_GPIO_BIT_3 01228 * @arg @ref LL_PWR_GPIO_BIT_4 01229 * @arg @ref LL_PWR_GPIO_BIT_5 01230 * @arg @ref LL_PWR_GPIO_BIT_6 01231 * @arg @ref LL_PWR_GPIO_BIT_7 01232 * @arg @ref LL_PWR_GPIO_BIT_8 01233 * @arg @ref LL_PWR_GPIO_BIT_9 01234 * @arg @ref LL_PWR_GPIO_BIT_10 01235 * @arg @ref LL_PWR_GPIO_BIT_11 01236 * @arg @ref LL_PWR_GPIO_BIT_12 01237 * @arg @ref LL_PWR_GPIO_BIT_13 01238 * @arg @ref LL_PWR_GPIO_BIT_14 01239 * @arg @ref LL_PWR_GPIO_BIT_15 01240 * @retval State of bit (1 or 0). 01241 */ 01242 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 01243 { 01244 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); 01245 } 01246 01247 /** 01248 * @brief Enable GPIO pull-down state in Standby and Shutdown modes 01249 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n 01250 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n 01251 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n 01252 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n 01253 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n 01254 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n 01255 * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n 01256 * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown\n 01257 * PDCRI PD0-11 LL_PWR_EnableGPIOPullDown 01258 * @param GPIO This parameter can be one of the following values: 01259 * @arg @ref LL_PWR_GPIO_A 01260 * @arg @ref LL_PWR_GPIO_B 01261 * @arg @ref LL_PWR_GPIO_C 01262 * @arg @ref LL_PWR_GPIO_D 01263 * @arg @ref LL_PWR_GPIO_E 01264 * @arg @ref LL_PWR_GPIO_F (*) 01265 * @arg @ref LL_PWR_GPIO_G (*) 01266 * @arg @ref LL_PWR_GPIO_H 01267 * @arg @ref LL_PWR_GPIO_I (*) 01268 * 01269 * (*) value not defined in all devices 01270 * @param GPIONumber This parameter can be one of the following values: 01271 * @arg @ref LL_PWR_GPIO_BIT_0 01272 * @arg @ref LL_PWR_GPIO_BIT_1 01273 * @arg @ref LL_PWR_GPIO_BIT_2 01274 * @arg @ref LL_PWR_GPIO_BIT_3 01275 * @arg @ref LL_PWR_GPIO_BIT_4 01276 * @arg @ref LL_PWR_GPIO_BIT_5 01277 * @arg @ref LL_PWR_GPIO_BIT_6 01278 * @arg @ref LL_PWR_GPIO_BIT_7 01279 * @arg @ref LL_PWR_GPIO_BIT_8 01280 * @arg @ref LL_PWR_GPIO_BIT_9 01281 * @arg @ref LL_PWR_GPIO_BIT_10 01282 * @arg @ref LL_PWR_GPIO_BIT_11 01283 * @arg @ref LL_PWR_GPIO_BIT_12 01284 * @arg @ref LL_PWR_GPIO_BIT_13 01285 * @arg @ref LL_PWR_GPIO_BIT_14 01286 * @arg @ref LL_PWR_GPIO_BIT_15 01287 * @retval None 01288 */ 01289 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 01290 { 01291 SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); 01292 } 01293 01294 /** 01295 * @brief Disable GPIO pull-down state in Standby and Shutdown modes 01296 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n 01297 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n 01298 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n 01299 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n 01300 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n 01301 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n 01302 * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n 01303 * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown\n 01304 * PDCRI PD0-11 LL_PWR_DisableGPIOPullDown 01305 * @param GPIO This parameter can be one of the following values: 01306 * @arg @ref LL_PWR_GPIO_A 01307 * @arg @ref LL_PWR_GPIO_B 01308 * @arg @ref LL_PWR_GPIO_C 01309 * @arg @ref LL_PWR_GPIO_D 01310 * @arg @ref LL_PWR_GPIO_E 01311 * @arg @ref LL_PWR_GPIO_F (*) 01312 * @arg @ref LL_PWR_GPIO_G (*) 01313 * @arg @ref LL_PWR_GPIO_H 01314 * @arg @ref LL_PWR_GPIO_I (*) 01315 * 01316 * (*) value not defined in all devices 01317 * @param GPIONumber This parameter can be one of the following values: 01318 * @arg @ref LL_PWR_GPIO_BIT_0 01319 * @arg @ref LL_PWR_GPIO_BIT_1 01320 * @arg @ref LL_PWR_GPIO_BIT_2 01321 * @arg @ref LL_PWR_GPIO_BIT_3 01322 * @arg @ref LL_PWR_GPIO_BIT_4 01323 * @arg @ref LL_PWR_GPIO_BIT_5 01324 * @arg @ref LL_PWR_GPIO_BIT_6 01325 * @arg @ref LL_PWR_GPIO_BIT_7 01326 * @arg @ref LL_PWR_GPIO_BIT_8 01327 * @arg @ref LL_PWR_GPIO_BIT_9 01328 * @arg @ref LL_PWR_GPIO_BIT_10 01329 * @arg @ref LL_PWR_GPIO_BIT_11 01330 * @arg @ref LL_PWR_GPIO_BIT_12 01331 * @arg @ref LL_PWR_GPIO_BIT_13 01332 * @arg @ref LL_PWR_GPIO_BIT_14 01333 * @arg @ref LL_PWR_GPIO_BIT_15 01334 * @retval None 01335 */ 01336 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 01337 { 01338 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); 01339 } 01340 01341 /** 01342 * @brief Check if GPIO pull-down state is enabled 01343 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01344 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01345 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01346 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01347 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01348 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01349 * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01350 * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01351 * PDCRI PD0-11 LL_PWR_IsEnabledGPIOPullDown 01352 * @param GPIO This parameter can be one of the following values: 01353 * @arg @ref LL_PWR_GPIO_A 01354 * @arg @ref LL_PWR_GPIO_B 01355 * @arg @ref LL_PWR_GPIO_C 01356 * @arg @ref LL_PWR_GPIO_D 01357 * @arg @ref LL_PWR_GPIO_E 01358 * @arg @ref LL_PWR_GPIO_F (*) 01359 * @arg @ref LL_PWR_GPIO_G (*) 01360 * @arg @ref LL_PWR_GPIO_H 01361 * @arg @ref LL_PWR_GPIO_I (*) 01362 * 01363 * (*) value not defined in all devices 01364 * @param GPIONumber This parameter can be one of the following values: 01365 * @arg @ref LL_PWR_GPIO_BIT_0 01366 * @arg @ref LL_PWR_GPIO_BIT_1 01367 * @arg @ref LL_PWR_GPIO_BIT_2 01368 * @arg @ref LL_PWR_GPIO_BIT_3 01369 * @arg @ref LL_PWR_GPIO_BIT_4 01370 * @arg @ref LL_PWR_GPIO_BIT_5 01371 * @arg @ref LL_PWR_GPIO_BIT_6 01372 * @arg @ref LL_PWR_GPIO_BIT_7 01373 * @arg @ref LL_PWR_GPIO_BIT_8 01374 * @arg @ref LL_PWR_GPIO_BIT_9 01375 * @arg @ref LL_PWR_GPIO_BIT_10 01376 * @arg @ref LL_PWR_GPIO_BIT_11 01377 * @arg @ref LL_PWR_GPIO_BIT_12 01378 * @arg @ref LL_PWR_GPIO_BIT_13 01379 * @arg @ref LL_PWR_GPIO_BIT_14 01380 * @arg @ref LL_PWR_GPIO_BIT_15 01381 * @retval State of bit (1 or 0). 01382 */ 01383 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 01384 { 01385 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); 01386 } 01387 01388 /** 01389 * @} 01390 */ 01391 01392 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management 01393 * @{ 01394 */ 01395 01396 /** 01397 * @brief Get Internal Wake-up line Flag 01398 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU 01399 * @retval State of bit (1 or 0). 01400 */ 01401 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) 01402 { 01403 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL); 01404 } 01405 01406 #if defined(PWR_SR1_EXT_SMPS_RDY) 01407 /** 01408 * @brief Get Ready Flag for switching to external SMPS 01409 * @rmtoll SR1 EXT_SMPS_RDY LL_PWR_IsActiveFlag_ExtSMPSReady 01410 * @retval State of bit (1 or 0). 01411 */ 01412 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ExtSMPSReady(void) 01413 { 01414 return ((READ_BIT(PWR->SR1, PWR_SR1_EXT_SMPS_RDY) == (PWR_SR1_EXT_SMPS_RDY)) ? 1UL : 0UL); 01415 } 01416 #endif /* PWR_SR1_EXT_SMPS_RDY */ 01417 01418 /** 01419 * @brief Get Stand-By Flag 01420 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB 01421 * @retval State of bit (1 or 0). 01422 */ 01423 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) 01424 { 01425 return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL); 01426 } 01427 01428 /** 01429 * @brief Get Wake-up Flag 5 01430 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5 01431 * @retval State of bit (1 or 0). 01432 */ 01433 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) 01434 { 01435 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); 01436 } 01437 01438 /** 01439 * @brief Get Wake-up Flag 4 01440 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4 01441 * @retval State of bit (1 or 0). 01442 */ 01443 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) 01444 { 01445 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL); 01446 } 01447 01448 /** 01449 * @brief Get Wake-up Flag 3 01450 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3 01451 * @retval State of bit (1 or 0). 01452 */ 01453 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) 01454 { 01455 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); 01456 } 01457 01458 /** 01459 * @brief Get Wake-up Flag 2 01460 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2 01461 * @retval State of bit (1 or 0). 01462 */ 01463 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) 01464 { 01465 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); 01466 } 01467 01468 /** 01469 * @brief Get Wake-up Flag 1 01470 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1 01471 * @retval State of bit (1 or 0). 01472 */ 01473 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) 01474 { 01475 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); 01476 } 01477 01478 /** 01479 * @brief Clear Stand-By Flag 01480 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB 01481 * @retval None 01482 */ 01483 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) 01484 { 01485 WRITE_REG(PWR->SCR, PWR_SCR_CSBF); 01486 } 01487 01488 /** 01489 * @brief Clear Wake-up Flags 01490 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU 01491 * @retval None 01492 */ 01493 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) 01494 { 01495 WRITE_REG(PWR->SCR, PWR_SCR_CWUF); 01496 } 01497 01498 /** 01499 * @brief Clear Wake-up Flag 5 01500 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5 01501 * @retval None 01502 */ 01503 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) 01504 { 01505 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); 01506 } 01507 01508 /** 01509 * @brief Clear Wake-up Flag 4 01510 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4 01511 * @retval None 01512 */ 01513 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) 01514 { 01515 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); 01516 } 01517 01518 /** 01519 * @brief Clear Wake-up Flag 3 01520 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3 01521 * @retval None 01522 */ 01523 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) 01524 { 01525 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); 01526 } 01527 01528 /** 01529 * @brief Clear Wake-up Flag 2 01530 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2 01531 * @retval None 01532 */ 01533 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) 01534 { 01535 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); 01536 } 01537 01538 /** 01539 * @brief Clear Wake-up Flag 1 01540 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1 01541 * @retval None 01542 */ 01543 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) 01544 { 01545 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); 01546 } 01547 01548 /** 01549 * @brief Indicate whether VDDA voltage is below or above PVM4 threshold 01550 * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4 01551 * @retval State of bit (1 or 0). 01552 */ 01553 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void) 01554 { 01555 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)) ? 1UL : 0UL); 01556 } 01557 01558 /** 01559 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold 01560 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3 01561 * @retval State of bit (1 or 0). 01562 */ 01563 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) 01564 { 01565 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL); 01566 } 01567 01568 #if defined(PWR_SR2_PVMO2) 01569 /** 01570 * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold 01571 * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2 01572 * @retval State of bit (1 or 0). 01573 */ 01574 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void) 01575 { 01576 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)) ? 1UL : 0UL); 01577 } 01578 #endif /* PWR_SR2_PVMO2 */ 01579 01580 #if defined(PWR_SR2_PVMO1) 01581 /** 01582 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold 01583 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1 01584 * @retval State of bit (1 or 0). 01585 */ 01586 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) 01587 { 01588 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL); 01589 } 01590 #endif /* PWR_SR2_PVMO1 */ 01591 01592 /** 01593 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold 01594 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO 01595 * @retval State of bit (1 or 0). 01596 */ 01597 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) 01598 { 01599 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); 01600 } 01601 01602 /** 01603 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level 01604 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS 01605 * @retval State of bit (1 or 0). 01606 */ 01607 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) 01608 { 01609 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL); 01610 } 01611 01612 /** 01613 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode 01614 * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. 01615 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF 01616 * @retval State of bit (1 or 0). 01617 */ 01618 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) 01619 { 01620 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL); 01621 } 01622 01623 /** 01624 * @brief Indicate whether or not the low-power regulator is ready 01625 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS 01626 * @retval State of bit (1 or 0). 01627 */ 01628 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void) 01629 { 01630 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL); 01631 } 01632 01633 /** 01634 * @} 01635 */ 01636 01637 #if defined(USE_FULL_LL_DRIVER) 01638 /** @defgroup PWR_LL_EF_Init De-initialization function 01639 * @{ 01640 */ 01641 ErrorStatus LL_PWR_DeInit(void); 01642 /** 01643 * @} 01644 */ 01645 #endif /* USE_FULL_LL_DRIVER */ 01646 01647 /** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name 01648 * @{ 01649 */ 01650 /* Old functions name kept for legacy purpose, to be replaced by the */ 01651 /* current functions name. */ 01652 #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS 01653 /** 01654 * @} 01655 */ 01656 01657 /** 01658 * @} 01659 */ 01660 01661 /** 01662 * @} 01663 */ 01664 01665 #endif /* defined(PWR) */ 01666 01667 /** 01668 * @} 01669 */ 01670 01671 #ifdef __cplusplus 01672 } 01673 #endif 01674 01675 #endif /* STM32L4xx_LL_PWR_H */
1.7.6.1