|
STM32L443xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_tim.h 00004 * @author MCD Application Team 00005 * @brief Header file of TIM LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef __STM32L4xx_LL_TIM_H 00021 #define __STM32L4xx_LL_TIM_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx.h" 00029 00030 /** @addtogroup STM32L4xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7) 00035 00036 /** @defgroup TIM_LL TIM 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 /** @defgroup TIM_LL_Private_Variables TIM Private Variables 00043 * @{ 00044 */ 00045 static const uint8_t OFFSET_TAB_CCMRx[] = 00046 { 00047 0x00U, /* 0: TIMx_CH1 */ 00048 0x00U, /* 1: TIMx_CH1N */ 00049 0x00U, /* 2: TIMx_CH2 */ 00050 0x00U, /* 3: TIMx_CH2N */ 00051 0x04U, /* 4: TIMx_CH3 */ 00052 0x04U, /* 5: TIMx_CH3N */ 00053 0x04U, /* 6: TIMx_CH4 */ 00054 0x3CU, /* 7: TIMx_CH5 */ 00055 0x3CU /* 8: TIMx_CH6 */ 00056 }; 00057 00058 static const uint8_t SHIFT_TAB_OCxx[] = 00059 { 00060 0U, /* 0: OC1M, OC1FE, OC1PE */ 00061 0U, /* 1: - NA */ 00062 8U, /* 2: OC2M, OC2FE, OC2PE */ 00063 0U, /* 3: - NA */ 00064 0U, /* 4: OC3M, OC3FE, OC3PE */ 00065 0U, /* 5: - NA */ 00066 8U, /* 6: OC4M, OC4FE, OC4PE */ 00067 0U, /* 7: OC5M, OC5FE, OC5PE */ 00068 8U /* 8: OC6M, OC6FE, OC6PE */ 00069 }; 00070 00071 static const uint8_t SHIFT_TAB_ICxx[] = 00072 { 00073 0U, /* 0: CC1S, IC1PSC, IC1F */ 00074 0U, /* 1: - NA */ 00075 8U, /* 2: CC2S, IC2PSC, IC2F */ 00076 0U, /* 3: - NA */ 00077 0U, /* 4: CC3S, IC3PSC, IC3F */ 00078 0U, /* 5: - NA */ 00079 8U, /* 6: CC4S, IC4PSC, IC4F */ 00080 0U, /* 7: - NA */ 00081 0U /* 8: - NA */ 00082 }; 00083 00084 static const uint8_t SHIFT_TAB_CCxP[] = 00085 { 00086 0U, /* 0: CC1P */ 00087 2U, /* 1: CC1NP */ 00088 4U, /* 2: CC2P */ 00089 6U, /* 3: CC2NP */ 00090 8U, /* 4: CC3P */ 00091 10U, /* 5: CC3NP */ 00092 12U, /* 6: CC4P */ 00093 16U, /* 7: CC5P */ 00094 20U /* 8: CC6P */ 00095 }; 00096 00097 static const uint8_t SHIFT_TAB_OISx[] = 00098 { 00099 0U, /* 0: OIS1 */ 00100 1U, /* 1: OIS1N */ 00101 2U, /* 2: OIS2 */ 00102 3U, /* 3: OIS2N */ 00103 4U, /* 4: OIS3 */ 00104 5U, /* 5: OIS3N */ 00105 6U, /* 6: OIS4 */ 00106 8U, /* 7: OIS5 */ 00107 10U /* 8: OIS6 */ 00108 }; 00109 /** 00110 * @} 00111 */ 00112 00113 /* Private constants ---------------------------------------------------------*/ 00114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants 00115 * @{ 00116 */ 00117 00118 /* Defines used for the bit position in the register and perform offsets */ 00119 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) 00120 00121 /* Generic bit definitions for TIMx_OR2 register */ 00122 #define TIMx_OR2_BKINP TIM1_OR2_BKINP /*!< BRK BKIN input polarity */ 00123 #define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /*!< TIMx ETR source selection */ 00124 00125 /* Remap mask definitions */ 00126 #define TIMx_OR1_RMP_SHIFT 16U 00127 #define TIMx_OR1_RMP_MASK 0x0000FFFFU 00128 #if defined(ADC3) 00129 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) 00130 #else 00131 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) 00132 #endif /* ADC3 */ 00133 #define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT) 00134 #define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) 00135 #if defined(ADC2) && defined(ADC3) 00136 #define TIM8_OR1_RMP_MASK ((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) 00137 #else 00138 #define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) 00139 #endif /* ADC2 & ADC3 */ 00140 #define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) 00141 #define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) 00142 #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) 00143 00144 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ 00145 #define DT_DELAY_1 ((uint8_t)0x7F) 00146 #define DT_DELAY_2 ((uint8_t)0x3F) 00147 #define DT_DELAY_3 ((uint8_t)0x1F) 00148 #define DT_DELAY_4 ((uint8_t)0x1F) 00149 00150 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ 00151 #define DT_RANGE_1 ((uint8_t)0x00) 00152 #define DT_RANGE_2 ((uint8_t)0x80) 00153 #define DT_RANGE_3 ((uint8_t)0xC0) 00154 #define DT_RANGE_4 ((uint8_t)0xE0) 00155 00156 /** Legacy definitions for compatibility purpose 00157 @cond 0 00158 */ 00159 #if defined(DFSDM1_Channel0) 00160 #define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E 00161 #define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E 00162 #endif /* DFSDM1_Channel0 */ 00163 /** 00164 @endcond 00165 */ 00166 00167 /** 00168 * @} 00169 */ 00170 00171 /* Private macros ------------------------------------------------------------*/ 00172 /** @defgroup TIM_LL_Private_Macros TIM Private Macros 00173 * @{ 00174 */ 00175 /** @brief Convert channel id into channel index. 00176 * @param __CHANNEL__ This parameter can be one of the following values: 00177 * @arg @ref LL_TIM_CHANNEL_CH1 00178 * @arg @ref LL_TIM_CHANNEL_CH1N 00179 * @arg @ref LL_TIM_CHANNEL_CH2 00180 * @arg @ref LL_TIM_CHANNEL_CH2N 00181 * @arg @ref LL_TIM_CHANNEL_CH3 00182 * @arg @ref LL_TIM_CHANNEL_CH3N 00183 * @arg @ref LL_TIM_CHANNEL_CH4 00184 * @arg @ref LL_TIM_CHANNEL_CH5 00185 * @arg @ref LL_TIM_CHANNEL_CH6 00186 * @retval none 00187 */ 00188 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ 00189 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ 00190 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ 00191 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ 00192 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ 00193 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ 00194 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ 00195 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ 00196 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) 00197 00198 /** @brief Calculate the deadtime sampling period(in ps). 00199 * @param __TIMCLK__ timer input clock frequency (in Hz). 00200 * @param __CKD__ This parameter can be one of the following values: 00201 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 00202 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 00203 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 00204 * @retval none 00205 */ 00206 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ 00207 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ 00208 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ 00209 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) 00210 /** 00211 * @} 00212 */ 00213 00214 00215 /* Exported types ------------------------------------------------------------*/ 00216 #if defined(USE_FULL_LL_DRIVER) 00217 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure 00218 * @{ 00219 */ 00220 00221 /** 00222 * @brief TIM Time Base configuration structure definition. 00223 */ 00224 typedef struct 00225 { 00226 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 00227 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 00228 00229 This feature can be modified afterwards using unitary function 00230 @ref LL_TIM_SetPrescaler().*/ 00231 00232 uint32_t CounterMode; /*!< Specifies the counter mode. 00233 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. 00234 00235 This feature can be modified afterwards using unitary function 00236 @ref LL_TIM_SetCounterMode().*/ 00237 00238 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active 00239 Auto-Reload Register at the next update event. 00240 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 00241 Some timer instances may support 32 bits counters. In that case this parameter must 00242 be a number between 0x0000 and 0xFFFFFFFF. 00243 00244 This feature can be modified afterwards using unitary function 00245 @ref LL_TIM_SetAutoReload().*/ 00246 00247 uint32_t ClockDivision; /*!< Specifies the clock division. 00248 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. 00249 00250 This feature can be modified afterwards using unitary function 00251 @ref LL_TIM_SetClockDivision().*/ 00252 00253 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 00254 reaches zero, an update event is generated and counting restarts 00255 from the RCR value (N). 00256 This means in PWM mode that (N+1) corresponds to: 00257 - the number of PWM periods in edge-aligned mode 00258 - the number of half PWM period in center-aligned mode 00259 GP timers: this parameter must be a number between Min_Data = 0x00 and 00260 Max_Data = 0xFF. 00261 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and 00262 Max_Data = 0xFFFF. 00263 00264 This feature can be modified afterwards using unitary function 00265 @ref LL_TIM_SetRepetitionCounter().*/ 00266 } LL_TIM_InitTypeDef; 00267 00268 /** 00269 * @brief TIM Output Compare configuration structure definition. 00270 */ 00271 typedef struct 00272 { 00273 uint32_t OCMode; /*!< Specifies the output mode. 00274 This parameter can be a value of @ref TIM_LL_EC_OCMODE. 00275 00276 This feature can be modified afterwards using unitary function 00277 @ref LL_TIM_OC_SetMode().*/ 00278 00279 uint32_t OCState; /*!< Specifies the TIM Output Compare state. 00280 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 00281 00282 This feature can be modified afterwards using unitary functions 00283 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 00284 00285 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. 00286 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 00287 00288 This feature can be modified afterwards using unitary functions 00289 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 00290 00291 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. 00292 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 00293 00294 This feature can be modified afterwards using unitary function 00295 LL_TIM_OC_SetCompareCHx (x=1..6).*/ 00296 00297 uint32_t OCPolarity; /*!< Specifies the output polarity. 00298 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 00299 00300 This feature can be modified afterwards using unitary function 00301 @ref LL_TIM_OC_SetPolarity().*/ 00302 00303 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00304 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 00305 00306 This feature can be modified afterwards using unitary function 00307 @ref LL_TIM_OC_SetPolarity().*/ 00308 00309 00310 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00311 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 00312 00313 This feature can be modified afterwards using unitary function 00314 @ref LL_TIM_OC_SetIdleState().*/ 00315 00316 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00317 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 00318 00319 This feature can be modified afterwards using unitary function 00320 @ref LL_TIM_OC_SetIdleState().*/ 00321 } LL_TIM_OC_InitTypeDef; 00322 00323 /** 00324 * @brief TIM Input Capture configuration structure definition. 00325 */ 00326 00327 typedef struct 00328 { 00329 00330 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00331 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00332 00333 This feature can be modified afterwards using unitary function 00334 @ref LL_TIM_IC_SetPolarity().*/ 00335 00336 uint32_t ICActiveInput; /*!< Specifies the input. 00337 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00338 00339 This feature can be modified afterwards using unitary function 00340 @ref LL_TIM_IC_SetActiveInput().*/ 00341 00342 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 00343 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00344 00345 This feature can be modified afterwards using unitary function 00346 @ref LL_TIM_IC_SetPrescaler().*/ 00347 00348 uint32_t ICFilter; /*!< Specifies the input capture filter. 00349 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00350 00351 This feature can be modified afterwards using unitary function 00352 @ref LL_TIM_IC_SetFilter().*/ 00353 } LL_TIM_IC_InitTypeDef; 00354 00355 00356 /** 00357 * @brief TIM Encoder interface configuration structure definition. 00358 */ 00359 typedef struct 00360 { 00361 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). 00362 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. 00363 00364 This feature can be modified afterwards using unitary function 00365 @ref LL_TIM_SetEncoderMode().*/ 00366 00367 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 00368 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00369 00370 This feature can be modified afterwards using unitary function 00371 @ref LL_TIM_IC_SetPolarity().*/ 00372 00373 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source 00374 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00375 00376 This feature can be modified afterwards using unitary function 00377 @ref LL_TIM_IC_SetActiveInput().*/ 00378 00379 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 00380 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00381 00382 This feature can be modified afterwards using unitary function 00383 @ref LL_TIM_IC_SetPrescaler().*/ 00384 00385 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 00386 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00387 00388 This feature can be modified afterwards using unitary function 00389 @ref LL_TIM_IC_SetFilter().*/ 00390 00391 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. 00392 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00393 00394 This feature can be modified afterwards using unitary function 00395 @ref LL_TIM_IC_SetPolarity().*/ 00396 00397 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source 00398 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00399 00400 This feature can be modified afterwards using unitary function 00401 @ref LL_TIM_IC_SetActiveInput().*/ 00402 00403 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. 00404 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00405 00406 This feature can be modified afterwards using unitary function 00407 @ref LL_TIM_IC_SetPrescaler().*/ 00408 00409 uint32_t IC2Filter; /*!< Specifies the TI2 input filter. 00410 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00411 00412 This feature can be modified afterwards using unitary function 00413 @ref LL_TIM_IC_SetFilter().*/ 00414 00415 } LL_TIM_ENCODER_InitTypeDef; 00416 00417 /** 00418 * @brief TIM Hall sensor interface configuration structure definition. 00419 */ 00420 typedef struct 00421 { 00422 00423 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 00424 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00425 00426 This feature can be modified afterwards using unitary function 00427 @ref LL_TIM_IC_SetPolarity().*/ 00428 00429 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 00430 Prescaler must be set to get a maximum counter period longer than the 00431 time interval between 2 consecutive changes on the Hall inputs. 00432 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00433 00434 This feature can be modified afterwards using unitary function 00435 @ref LL_TIM_IC_SetPrescaler().*/ 00436 00437 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 00438 This parameter can be a value of 00439 @ref TIM_LL_EC_IC_FILTER. 00440 00441 This feature can be modified afterwards using unitary function 00442 @ref LL_TIM_IC_SetFilter().*/ 00443 00444 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. 00445 A positive pulse (TRGO event) is generated with a programmable delay every time 00446 a change occurs on the Hall inputs. 00447 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. 00448 00449 This feature can be modified afterwards using unitary function 00450 @ref LL_TIM_OC_SetCompareCH2().*/ 00451 } LL_TIM_HALLSENSOR_InitTypeDef; 00452 00453 /** 00454 * @brief BDTR (Break and Dead Time) structure definition 00455 */ 00456 typedef struct 00457 { 00458 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. 00459 This parameter can be a value of @ref TIM_LL_EC_OSSR 00460 00461 This feature can be modified afterwards using unitary function 00462 @ref LL_TIM_SetOffStates() 00463 00464 @note This bit-field cannot be modified as long as LOCK level 2 has been 00465 programmed. */ 00466 00467 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. 00468 This parameter can be a value of @ref TIM_LL_EC_OSSI 00469 00470 This feature can be modified afterwards using unitary function 00471 @ref LL_TIM_SetOffStates() 00472 00473 @note This bit-field cannot be modified as long as LOCK level 2 has been 00474 programmed. */ 00475 00476 uint32_t LockLevel; /*!< Specifies the LOCK level parameters. 00477 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL 00478 00479 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR 00480 register has been written, their content is frozen until the next reset.*/ 00481 00482 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the 00483 switching-on of the outputs. 00484 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. 00485 00486 This feature can be modified afterwards using unitary function 00487 @ref LL_TIM_OC_SetDeadTime() 00488 00489 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been 00490 programmed. */ 00491 00492 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. 00493 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE 00494 00495 This feature can be modified afterwards using unitary functions 00496 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() 00497 00498 @note This bit-field can not be modified as long as LOCK level 1 has been 00499 programmed. */ 00500 00501 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 00502 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY 00503 00504 This feature can be modified afterwards using unitary function 00505 @ref LL_TIM_ConfigBRK() 00506 00507 @note This bit-field can not be modified as long as LOCK level 1 has been 00508 programmed. */ 00509 00510 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. 00511 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER 00512 00513 This feature can be modified afterwards using unitary function 00514 @ref LL_TIM_ConfigBRK() 00515 00516 @note This bit-field can not be modified as long as LOCK level 1 has been 00517 programmed. */ 00518 00519 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. 00520 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE 00521 00522 This feature can be modified afterwards using unitary functions 00523 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() 00524 00525 @note This bit-field can not be modified as long as LOCK level 1 has been 00526 programmed. */ 00527 00528 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. 00529 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY 00530 00531 This feature can be modified afterwards using unitary function 00532 @ref LL_TIM_ConfigBRK2() 00533 00534 @note This bit-field can not be modified as long as LOCK level 1 has been 00535 programmed. */ 00536 00537 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. 00538 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER 00539 00540 This feature can be modified afterwards using unitary function 00541 @ref LL_TIM_ConfigBRK2() 00542 00543 @note This bit-field can not be modified as long as LOCK level 1 has been 00544 programmed. */ 00545 00546 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 00547 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE 00548 00549 This feature can be modified afterwards using unitary functions 00550 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() 00551 00552 @note This bit-field can not be modified as long as LOCK level 1 has been 00553 programmed. */ 00554 } LL_TIM_BDTR_InitTypeDef; 00555 00556 /** 00557 * @} 00558 */ 00559 #endif /* USE_FULL_LL_DRIVER */ 00560 00561 /* Exported constants --------------------------------------------------------*/ 00562 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants 00563 * @{ 00564 */ 00565 00566 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines 00567 * @brief Flags defines which can be used with LL_TIM_ReadReg function. 00568 * @{ 00569 */ 00570 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ 00571 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ 00572 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ 00573 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ 00574 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ 00575 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ 00576 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ 00577 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ 00578 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ 00579 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ 00580 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ 00581 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ 00582 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ 00583 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ 00584 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ 00585 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ 00586 /** 00587 * @} 00588 */ 00589 00590 #if defined(USE_FULL_LL_DRIVER) 00591 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable 00592 * @{ 00593 */ 00594 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ 00595 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ 00596 /** 00597 * @} 00598 */ 00599 00600 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable 00601 * @{ 00602 */ 00603 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ 00604 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ 00605 /** 00606 * @} 00607 */ 00608 00609 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable 00610 * @{ 00611 */ 00612 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 00613 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ 00614 /** 00615 * @} 00616 */ 00617 #endif /* USE_FULL_LL_DRIVER */ 00618 00619 /** @defgroup TIM_LL_EC_IT IT Defines 00620 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. 00621 * @{ 00622 */ 00623 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ 00624 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ 00625 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ 00626 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ 00627 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ 00628 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ 00629 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ 00630 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ 00631 /** 00632 * @} 00633 */ 00634 00635 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source 00636 * @{ 00637 */ 00638 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ 00639 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ 00640 /** 00641 * @} 00642 */ 00643 00644 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode 00645 * @{ 00646 */ 00647 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 00648 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 00649 /** 00650 * @} 00651 */ 00652 00653 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode 00654 * @{ 00655 */ 00656 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ 00657 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ 00658 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ 00659 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ 00660 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ 00661 /** 00662 * @} 00663 */ 00664 00665 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division 00666 * @{ 00667 */ 00668 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ 00669 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ 00670 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ 00671 /** 00672 * @} 00673 */ 00674 00675 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction 00676 * @{ 00677 */ 00678 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ 00679 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ 00680 /** 00681 * @} 00682 */ 00683 00684 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source 00685 * @{ 00686 */ 00687 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ 00688 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ 00689 /** 00690 * @} 00691 */ 00692 00693 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request 00694 * @{ 00695 */ 00696 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ 00697 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 00698 /** 00699 * @} 00700 */ 00701 00702 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level 00703 * @{ 00704 */ 00705 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ 00706 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 00707 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 00708 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 00709 /** 00710 * @} 00711 */ 00712 00713 /** @defgroup TIM_LL_EC_CHANNEL Channel 00714 * @{ 00715 */ 00716 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ 00717 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ 00718 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ 00719 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ 00720 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ 00721 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ 00722 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ 00723 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ 00724 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ 00725 /** 00726 * @} 00727 */ 00728 00729 #if defined(USE_FULL_LL_DRIVER) 00730 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State 00731 * @{ 00732 */ 00733 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ 00734 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ 00735 /** 00736 * @} 00737 */ 00738 #endif /* USE_FULL_LL_DRIVER */ 00739 00740 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode 00741 * @{ 00742 */ 00743 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ 00744 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ 00745 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ 00746 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ 00747 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/ 00748 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ 00749 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ 00750 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ 00751 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/ 00752 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/ 00753 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/ 00754 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/ 00755 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/ 00756 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/ 00757 /** 00758 * @} 00759 */ 00760 00761 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity 00762 * @{ 00763 */ 00764 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ 00765 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ 00766 /** 00767 * @} 00768 */ 00769 00770 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State 00771 * @{ 00772 */ 00773 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ 00774 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ 00775 /** 00776 * @} 00777 */ 00778 00779 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5 00780 * @{ 00781 */ 00782 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 00783 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ 00784 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ 00785 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ 00786 /** 00787 * @} 00788 */ 00789 00790 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection 00791 * @{ 00792 */ 00793 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ 00794 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ 00795 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ 00796 /** 00797 * @} 00798 */ 00799 00800 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler 00801 * @{ 00802 */ 00803 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ 00804 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ 00805 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ 00806 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ 00807 /** 00808 * @} 00809 */ 00810 00811 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter 00812 * @{ 00813 */ 00814 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ 00815 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ 00816 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ 00817 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ 00818 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ 00819 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ 00820 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ 00821 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ 00822 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ 00823 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ 00824 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ 00825 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ 00826 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ 00827 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ 00828 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ 00829 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ 00830 /** 00831 * @} 00832 */ 00833 00834 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity 00835 * @{ 00836 */ 00837 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ 00838 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ 00839 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ 00840 /** 00841 * @} 00842 */ 00843 00844 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source 00845 * @{ 00846 */ 00847 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ 00848 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/ 00849 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ 00850 /** 00851 * @} 00852 */ 00853 00854 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode 00855 * @{ 00856 */ 00857 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ 00858 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ 00859 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ 00860 /** 00861 * @} 00862 */ 00863 00864 /** @defgroup TIM_LL_EC_TRGO Trigger Output 00865 * @{ 00866 */ 00867 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ 00868 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ 00869 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ 00870 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ 00871 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ 00872 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ 00873 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ 00874 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ 00875 /** 00876 * @} 00877 */ 00878 00879 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2 00880 * @{ 00881 */ 00882 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */ 00883 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */ 00884 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */ 00885 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */ 00886 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */ 00887 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */ 00888 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */ 00889 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */ 00890 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */ 00891 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */ 00892 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */ 00893 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */ 00894 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */ 00895 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */ 00896 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */ 00897 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */ 00898 /** 00899 * @} 00900 */ 00901 00902 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode 00903 * @{ 00904 */ 00905 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ 00906 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ 00907 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ 00908 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ 00909 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */ 00910 /** 00911 * @} 00912 */ 00913 00914 /** @defgroup TIM_LL_EC_TS Trigger Selection 00915 * @{ 00916 */ 00917 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ 00918 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ 00919 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ 00920 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ 00921 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ 00922 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ 00923 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ 00924 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ 00925 /** 00926 * @} 00927 */ 00928 00929 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity 00930 * @{ 00931 */ 00932 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ 00933 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ 00934 /** 00935 * @} 00936 */ 00937 00938 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler 00939 * @{ 00940 */ 00941 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ 00942 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ 00943 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ 00944 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ 00945 /** 00946 * @} 00947 */ 00948 00949 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter 00950 * @{ 00951 */ 00952 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ 00953 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ 00954 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ 00955 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ 00956 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ 00957 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ 00958 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ 00959 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ 00960 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ 00961 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ 00962 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ 00963 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ 00964 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ 00965 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ 00966 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ 00967 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ 00968 /** 00969 * @} 00970 */ 00971 00972 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source 00973 * @{ 00974 */ 00975 #define LL_TIM_ETRSOURCE_LEGACY 0x00000000U /*!< ETR legacy mode */ 00976 #define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /*!< COMP1 output connected to ETR input */ 00977 #define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /*!< COMP2 output connected to ETR input */ 00978 /** 00979 * @} 00980 */ 00981 00982 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity 00983 * @{ 00984 */ 00985 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 00986 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 00987 /** 00988 * @} 00989 */ 00990 00991 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter 00992 * @{ 00993 */ 00994 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ 00995 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */ 00996 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */ 00997 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */ 00998 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */ 00999 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */ 01000 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */ 01001 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */ 01002 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */ 01003 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */ 01004 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */ 01005 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */ 01006 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */ 01007 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */ 01008 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */ 01009 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */ 01010 /** 01011 * @} 01012 */ 01013 01014 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY 01015 * @{ 01016 */ 01017 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 01018 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 01019 /** 01020 * @} 01021 */ 01022 01023 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER 01024 * @{ 01025 */ 01026 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ 01027 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */ 01028 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */ 01029 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */ 01030 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */ 01031 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */ 01032 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */ 01033 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */ 01034 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */ 01035 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */ 01036 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */ 01037 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */ 01038 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */ 01039 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */ 01040 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */ 01041 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */ 01042 /** 01043 * @} 01044 */ 01045 01046 /** @defgroup TIM_LL_EC_OSSI OSSI 01047 * @{ 01048 */ 01049 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ 01050 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ 01051 /** 01052 * @} 01053 */ 01054 01055 /** @defgroup TIM_LL_EC_OSSR OSSR 01056 * @{ 01057 */ 01058 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ 01059 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ 01060 /** 01061 * @} 01062 */ 01063 01064 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT 01065 * @{ 01066 */ 01067 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */ 01068 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */ 01069 /** 01070 * @} 01071 */ 01072 01073 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE 01074 * @{ 01075 */ 01076 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */ 01077 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */ 01078 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */ 01079 #if defined(DFSDM1_Channel0) 01080 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */ 01081 #endif /* DFSDM1_Channel0 */ 01082 /** 01083 * @} 01084 */ 01085 01086 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY 01087 * @{ 01088 */ 01089 #define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /*!< BRK BKIN input is active low */ 01090 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */ 01091 /** 01092 * @} 01093 */ 01094 01095 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address 01096 * @{ 01097 */ 01098 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ 01099 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ 01100 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ 01101 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ 01102 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ 01103 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ 01104 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ 01105 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ 01106 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ 01107 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ 01108 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ 01109 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ 01110 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ 01111 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ 01112 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ 01113 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ 01114 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ 01115 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ 01116 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */ 01117 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ 01118 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ 01119 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ 01120 #define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_OR2 register is the DMA base address for DMA burst */ 01121 #define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */ 01122 /** 01123 * @} 01124 */ 01125 01126 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length 01127 * @{ 01128 */ 01129 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ 01130 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ 01131 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ 01132 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ 01133 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ 01134 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ 01135 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ 01136 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ 01137 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ 01138 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ 01139 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ 01140 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ 01141 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ 01142 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ 01143 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ 01144 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ 01145 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ 01146 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ 01147 /** 01148 * @} 01149 */ 01150 01151 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap 01152 * @{ 01153 */ 01154 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */ 01155 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */ 01156 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */ 01157 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */ 01158 /** 01159 * @} 01160 */ 01161 01162 #if defined(ADC3) 01163 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC3 Remap 01164 * @{ 01165 */ 01166 #define LL_TIM_TIM1_ETR_ADC3_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC3 analog watchdog x*/ 01167 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 1 */ 01168 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 2 */ 01169 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 3 */ 01170 /** 01171 * @} 01172 */ 01173 #endif /* ADC3 */ 01174 01175 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap 01176 * @{ 01177 */ 01178 #define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR1_RMP_MASK /*!< TIM1 input capture 1 is connected to GPIO */ 01179 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */ 01180 /** 01181 * @} 01182 */ 01183 01184 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap 01185 * @{ 01186 */ 01187 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 01188 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR1_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */ 01189 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */ 01190 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 01191 /* STM32L496xx || STM32L4A6xx || */ 01192 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01193 #if defined (STM32L412xx) || defined (STM32L422xx) ||defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 01194 #define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */ 01195 #define LL_TIM_TIM2_ITR1_RMP_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */ 01196 #endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ 01197 /* STM32L451xx || STM32L452xx || STM32L462xx */ 01198 #define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2_ETR is connected to GPIO */ 01199 #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to LSE */ 01200 /** 01201 * @} 01202 */ 01203 01204 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap 01205 * @{ 01206 */ 01207 #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */ 01208 #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */ 01209 #if defined (STM32L412xx) || defined (STM32L422xx) 01210 #else 01211 #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */ 01212 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */ 01213 #endif 01214 /** 01215 * @} 01216 */ 01217 01218 #if defined(TIM3) 01219 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap 01220 * @{ 01221 */ 01222 #define LL_TIM_TIM3_TI1_RMP_GPIO TIM3_OR1_RMP_MASK /*!< TIM3 input capture 1 is connected to GPIO */ 01223 #define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP1_OUT */ 01224 #define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP2_OUT */ 01225 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT */ 01226 /** 01227 * @} 01228 */ 01229 #endif /* TIM3 */ 01230 01231 #if defined(TIM8) 01232 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap 01233 * @{ 01234 */ 01235 #define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR1_RMP_MASK /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */ 01236 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */ 01237 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */ 01238 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */ 01239 /** 01240 * @} 01241 */ 01242 01243 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap 01244 * @{ 01245 */ 01246 #define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR1_RMP_MASK /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */ 01247 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */ 01248 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */ 01249 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */ 01250 /** 01251 * @} 01252 */ 01253 01254 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap 01255 * @{ 01256 */ 01257 #define LL_TIM_TIM8_TI1_RMP_GPIO TIM8_OR1_RMP_MASK /*!< TIM8 input capture 1 is connected to GPIO */ 01258 #define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8 input capture 1 is connected to COMP2 output */ 01259 /** 01260 * @} 01261 */ 01262 #endif /* TIM8 */ 01263 01264 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap 01265 * @{ 01266 */ 01267 #define LL_TIM_TIM15_TI1_RMP_GPIO TIM15_OR1_RMP_MASK /*!< TIM15 input capture 1 is connected to GPIO */ 01268 #define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK) /*!< TIM15 input capture 1 is connected to LSE */ 01269 /** 01270 * @} 01271 */ 01272 01273 /** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE 01274 * @{ 01275 */ 01276 #define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION TIM15_OR1_RMP_MASK /*!< No redirection*/ 01277 #define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ 01278 #define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y*/ 01279 #define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ 01280 /** 01281 * @} 01282 */ 01283 01284 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap 01285 * @{ 01286 */ 01287 #define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR1_RMP_MASK /*!< TIM16 input capture 1 is connected to GPIO */ 01288 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSI */ 01289 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSE */ 01290 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */ 01291 #if defined TIM16_OR1_TI1_RMP_2 01292 #define LL_TIM_TIM16_TI1_RMP_MSI (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MSI */ 01293 #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 */ 01294 #define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */ 01295 #endif 01296 /** 01297 * @} 01298 */ 01299 01300 #if defined(TIM17) 01301 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap 01302 * @{ 01303 */ 01304 #define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR1_RMP_MASK /*!< TIM17 input capture 1 is connected to GPIO */ 01305 #define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MSI */ 01306 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to HSE/32 */ 01307 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MCO */ 01308 /** 01309 * @} 01310 */ 01311 #endif /* TIM17 */ 01312 01313 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection 01314 * @{ 01315 */ 01316 #define LL_TIM_OCREF_CLR_INT_NC 0x00000000U /*!< OCREF_CLR_INT is not connected */ 01317 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */ 01318 /** 01319 * @} 01320 */ 01321 01322 /** Legacy definitions for compatibility purpose 01323 @cond 0 01324 */ 01325 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK 01326 /** 01327 @endcond 01328 */ 01329 /** 01330 * @} 01331 */ 01332 01333 /* Exported macro ------------------------------------------------------------*/ 01334 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros 01335 * @{ 01336 */ 01337 01338 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros 01339 * @{ 01340 */ 01341 /** 01342 * @brief Write a value in TIM register. 01343 * @param __INSTANCE__ TIM Instance 01344 * @param __REG__ Register to be written 01345 * @param __VALUE__ Value to be written in the register 01346 * @retval None 01347 */ 01348 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) 01349 01350 /** 01351 * @brief Read a value in TIM register. 01352 * @param __INSTANCE__ TIM Instance 01353 * @param __REG__ Register to be read 01354 * @retval Register value 01355 */ 01356 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) 01357 /** 01358 * @} 01359 */ 01360 01361 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros 01362 * @{ 01363 */ 01364 01365 /** 01366 * @brief HELPER macro retrieving the UIFCPY flag from the counter value. 01367 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); 01368 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied 01369 * to TIMx_CNT register bit 31) 01370 * @param __CNT__ Counter value 01371 * @retval UIF status bit 01372 */ 01373 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ 01374 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) 01375 01376 /** 01377 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. 01378 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); 01379 * @param __TIMCLK__ timer input clock frequency (in Hz) 01380 * @param __CKD__ This parameter can be one of the following values: 01381 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01382 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01383 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01384 * @param __DT__ deadtime duration (in ns) 01385 * @retval DTG[0:7] 01386 */ 01387 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ 01388 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ 01389 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ 01390 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ 01391 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ 01392 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ 01393 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ 01394 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ 01395 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ 01396 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ 01397 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ 01398 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 01399 0U) 01400 01401 /** 01402 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. 01403 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); 01404 * @param __TIMCLK__ timer input clock frequency (in Hz) 01405 * @param __CNTCLK__ counter clock frequency (in Hz) 01406 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) 01407 */ 01408 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ 01409 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) 01410 01411 /** 01412 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. 01413 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); 01414 * @param __TIMCLK__ timer input clock frequency (in Hz) 01415 * @param __PSC__ prescaler 01416 * @param __FREQ__ output signal frequency (in Hz) 01417 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 01418 */ 01419 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ 01420 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) 01421 01422 /** 01423 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare 01424 * active/inactive delay. 01425 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); 01426 * @param __TIMCLK__ timer input clock frequency (in Hz) 01427 * @param __PSC__ prescaler 01428 * @param __DELAY__ timer output compare active/inactive delay (in us) 01429 * @retval Compare value (between Min_Data=0 and Max_Data=65535) 01430 */ 01431 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ 01432 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ 01433 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) 01434 01435 /** 01436 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration 01437 * (when the timer operates in one pulse mode). 01438 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); 01439 * @param __TIMCLK__ timer input clock frequency (in Hz) 01440 * @param __PSC__ prescaler 01441 * @param __DELAY__ timer output compare active/inactive delay (in us) 01442 * @param __PULSE__ pulse duration (in us) 01443 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 01444 */ 01445 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ 01446 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ 01447 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) 01448 01449 /** 01450 * @brief HELPER macro retrieving the ratio of the input capture prescaler 01451 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); 01452 * @param __ICPSC__ This parameter can be one of the following values: 01453 * @arg @ref LL_TIM_ICPSC_DIV1 01454 * @arg @ref LL_TIM_ICPSC_DIV2 01455 * @arg @ref LL_TIM_ICPSC_DIV4 01456 * @arg @ref LL_TIM_ICPSC_DIV8 01457 * @retval Input capture prescaler ratio (1, 2, 4 or 8) 01458 */ 01459 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ 01460 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) 01461 01462 01463 /** 01464 * @} 01465 */ 01466 01467 01468 /** 01469 * @} 01470 */ 01471 01472 /* Exported functions --------------------------------------------------------*/ 01473 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions 01474 * @{ 01475 */ 01476 01477 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration 01478 * @{ 01479 */ 01480 /** 01481 * @brief Enable timer counter. 01482 * @rmtoll CR1 CEN LL_TIM_EnableCounter 01483 * @param TIMx Timer instance 01484 * @retval None 01485 */ 01486 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) 01487 { 01488 SET_BIT(TIMx->CR1, TIM_CR1_CEN); 01489 } 01490 01491 /** 01492 * @brief Disable timer counter. 01493 * @rmtoll CR1 CEN LL_TIM_DisableCounter 01494 * @param TIMx Timer instance 01495 * @retval None 01496 */ 01497 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) 01498 { 01499 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); 01500 } 01501 01502 /** 01503 * @brief Indicates whether the timer counter is enabled. 01504 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter 01505 * @param TIMx Timer instance 01506 * @retval State of bit (1 or 0). 01507 */ 01508 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) 01509 { 01510 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); 01511 } 01512 01513 /** 01514 * @brief Enable update event generation. 01515 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent 01516 * @param TIMx Timer instance 01517 * @retval None 01518 */ 01519 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) 01520 { 01521 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); 01522 } 01523 01524 /** 01525 * @brief Disable update event generation. 01526 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent 01527 * @param TIMx Timer instance 01528 * @retval None 01529 */ 01530 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) 01531 { 01532 SET_BIT(TIMx->CR1, TIM_CR1_UDIS); 01533 } 01534 01535 /** 01536 * @brief Indicates whether update event generation is enabled. 01537 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent 01538 * @param TIMx Timer instance 01539 * @retval Inverted state of bit (0 or 1). 01540 */ 01541 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) 01542 { 01543 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); 01544 } 01545 01546 /** 01547 * @brief Set update event source 01548 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events 01549 * generate an update interrupt or DMA request if enabled: 01550 * - Counter overflow/underflow 01551 * - Setting the UG bit 01552 * - Update generation through the slave mode controller 01553 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter 01554 * overflow/underflow generates an update interrupt or DMA request if enabled. 01555 * @rmtoll CR1 URS LL_TIM_SetUpdateSource 01556 * @param TIMx Timer instance 01557 * @param UpdateSource This parameter can be one of the following values: 01558 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 01559 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 01560 * @retval None 01561 */ 01562 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) 01563 { 01564 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); 01565 } 01566 01567 /** 01568 * @brief Get actual event update source 01569 * @rmtoll CR1 URS LL_TIM_GetUpdateSource 01570 * @param TIMx Timer instance 01571 * @retval Returned value can be one of the following values: 01572 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 01573 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 01574 */ 01575 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) 01576 { 01577 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); 01578 } 01579 01580 /** 01581 * @brief Set one pulse mode (one shot v.s. repetitive). 01582 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode 01583 * @param TIMx Timer instance 01584 * @param OnePulseMode This parameter can be one of the following values: 01585 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 01586 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 01587 * @retval None 01588 */ 01589 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) 01590 { 01591 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); 01592 } 01593 01594 /** 01595 * @brief Get actual one pulse mode. 01596 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode 01597 * @param TIMx Timer instance 01598 * @retval Returned value can be one of the following values: 01599 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 01600 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 01601 */ 01602 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) 01603 { 01604 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); 01605 } 01606 01607 /** 01608 * @brief Set the timer counter counting mode. 01609 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 01610 * check whether or not the counter mode selection feature is supported 01611 * by a timer instance. 01612 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 01613 * requires a timer reset to avoid unexpected direction 01614 * due to DIR bit readonly in center aligned mode. 01615 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n 01616 * CR1 CMS LL_TIM_SetCounterMode 01617 * @param TIMx Timer instance 01618 * @param CounterMode This parameter can be one of the following values: 01619 * @arg @ref LL_TIM_COUNTERMODE_UP 01620 * @arg @ref LL_TIM_COUNTERMODE_DOWN 01621 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 01622 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 01623 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 01624 * @retval None 01625 */ 01626 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) 01627 { 01628 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); 01629 } 01630 01631 /** 01632 * @brief Get actual counter mode. 01633 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 01634 * check whether or not the counter mode selection feature is supported 01635 * by a timer instance. 01636 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n 01637 * CR1 CMS LL_TIM_GetCounterMode 01638 * @param TIMx Timer instance 01639 * @retval Returned value can be one of the following values: 01640 * @arg @ref LL_TIM_COUNTERMODE_UP 01641 * @arg @ref LL_TIM_COUNTERMODE_DOWN 01642 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 01643 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 01644 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 01645 */ 01646 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) 01647 { 01648 uint32_t counter_mode; 01649 01650 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); 01651 01652 if (counter_mode == 0U) 01653 { 01654 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 01655 } 01656 01657 return counter_mode; 01658 } 01659 01660 /** 01661 * @brief Enable auto-reload (ARR) preload. 01662 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload 01663 * @param TIMx Timer instance 01664 * @retval None 01665 */ 01666 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) 01667 { 01668 SET_BIT(TIMx->CR1, TIM_CR1_ARPE); 01669 } 01670 01671 /** 01672 * @brief Disable auto-reload (ARR) preload. 01673 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload 01674 * @param TIMx Timer instance 01675 * @retval None 01676 */ 01677 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) 01678 { 01679 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); 01680 } 01681 01682 /** 01683 * @brief Indicates whether auto-reload (ARR) preload is enabled. 01684 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload 01685 * @param TIMx Timer instance 01686 * @retval State of bit (1 or 0). 01687 */ 01688 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) 01689 { 01690 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); 01691 } 01692 01693 /** 01694 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators 01695 * (when supported) and the digital filters. 01696 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 01697 * whether or not the clock division feature is supported by the timer 01698 * instance. 01699 * @rmtoll CR1 CKD LL_TIM_SetClockDivision 01700 * @param TIMx Timer instance 01701 * @param ClockDivision This parameter can be one of the following values: 01702 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01703 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01704 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01705 * @retval None 01706 */ 01707 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) 01708 { 01709 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); 01710 } 01711 01712 /** 01713 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time 01714 * generators (when supported) and the digital filters. 01715 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 01716 * whether or not the clock division feature is supported by the timer 01717 * instance. 01718 * @rmtoll CR1 CKD LL_TIM_GetClockDivision 01719 * @param TIMx Timer instance 01720 * @retval Returned value can be one of the following values: 01721 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01722 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01723 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01724 */ 01725 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) 01726 { 01727 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); 01728 } 01729 01730 /** 01731 * @brief Set the counter value. 01732 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01733 * whether or not a timer instance supports a 32 bits counter. 01734 * @rmtoll CNT CNT LL_TIM_SetCounter 01735 * @param TIMx Timer instance 01736 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 01737 * @retval None 01738 */ 01739 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) 01740 { 01741 WRITE_REG(TIMx->CNT, Counter); 01742 } 01743 01744 /** 01745 * @brief Get the counter value. 01746 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01747 * whether or not a timer instance supports a 32 bits counter. 01748 * @rmtoll CNT CNT LL_TIM_GetCounter 01749 * @param TIMx Timer instance 01750 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 01751 */ 01752 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) 01753 { 01754 return (uint32_t)(READ_REG(TIMx->CNT)); 01755 } 01756 01757 /** 01758 * @brief Get the current direction of the counter 01759 * @rmtoll CR1 DIR LL_TIM_GetDirection 01760 * @param TIMx Timer instance 01761 * @retval Returned value can be one of the following values: 01762 * @arg @ref LL_TIM_COUNTERDIRECTION_UP 01763 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN 01764 */ 01765 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) 01766 { 01767 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 01768 } 01769 01770 /** 01771 * @brief Set the prescaler value. 01772 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). 01773 * @note The prescaler can be changed on the fly as this control register is buffered. The new 01774 * prescaler ratio is taken into account at the next update event. 01775 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter 01776 * @rmtoll PSC PSC LL_TIM_SetPrescaler 01777 * @param TIMx Timer instance 01778 * @param Prescaler between Min_Data=0 and Max_Data=65535 01779 * @retval None 01780 */ 01781 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) 01782 { 01783 WRITE_REG(TIMx->PSC, Prescaler); 01784 } 01785 01786 /** 01787 * @brief Get the prescaler value. 01788 * @rmtoll PSC PSC LL_TIM_GetPrescaler 01789 * @param TIMx Timer instance 01790 * @retval Prescaler value between Min_Data=0 and Max_Data=65535 01791 */ 01792 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) 01793 { 01794 return (uint32_t)(READ_REG(TIMx->PSC)); 01795 } 01796 01797 /** 01798 * @brief Set the auto-reload value. 01799 * @note The counter is blocked while the auto-reload value is null. 01800 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01801 * whether or not a timer instance supports a 32 bits counter. 01802 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter 01803 * @rmtoll ARR ARR LL_TIM_SetAutoReload 01804 * @param TIMx Timer instance 01805 * @param AutoReload between Min_Data=0 and Max_Data=65535 01806 * @retval None 01807 */ 01808 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) 01809 { 01810 WRITE_REG(TIMx->ARR, AutoReload); 01811 } 01812 01813 /** 01814 * @brief Get the auto-reload value. 01815 * @rmtoll ARR ARR LL_TIM_GetAutoReload 01816 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01817 * whether or not a timer instance supports a 32 bits counter. 01818 * @param TIMx Timer instance 01819 * @retval Auto-reload value 01820 */ 01821 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) 01822 { 01823 return (uint32_t)(READ_REG(TIMx->ARR)); 01824 } 01825 01826 /** 01827 * @brief Set the repetition counter value. 01828 * @note For advanced timer instances RepetitionCounter can be up to 65535. 01829 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 01830 * whether or not a timer instance supports a repetition counter. 01831 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter 01832 * @param TIMx Timer instance 01833 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. 01834 * @retval None 01835 */ 01836 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) 01837 { 01838 WRITE_REG(TIMx->RCR, RepetitionCounter); 01839 } 01840 01841 /** 01842 * @brief Get the repetition counter value. 01843 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 01844 * whether or not a timer instance supports a repetition counter. 01845 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter 01846 * @param TIMx Timer instance 01847 * @retval Repetition counter value 01848 */ 01849 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) 01850 { 01851 return (uint32_t)(READ_REG(TIMx->RCR)); 01852 } 01853 01854 /** 01855 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 01856 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read 01857 * in an atomic way. 01858 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap 01859 * @param TIMx Timer instance 01860 * @retval None 01861 */ 01862 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) 01863 { 01864 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 01865 } 01866 01867 /** 01868 * @brief Disable update interrupt flag (UIF) remapping. 01869 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap 01870 * @param TIMx Timer instance 01871 * @retval None 01872 */ 01873 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) 01874 { 01875 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 01876 } 01877 01878 /** 01879 * @brief Indicate whether update interrupt flag (UIF) copy is set. 01880 * @param Counter Counter value 01881 * @retval State of bit (1 or 0). 01882 */ 01883 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) 01884 { 01885 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); 01886 } 01887 01888 /** 01889 * @} 01890 */ 01891 01892 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration 01893 * @{ 01894 */ 01895 /** 01896 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 01897 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, 01898 * they are updated only when a commutation event (COM) occurs. 01899 * @note Only on channels that have a complementary output. 01900 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01901 * whether or not a timer instance is able to generate a commutation event. 01902 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload 01903 * @param TIMx Timer instance 01904 * @retval None 01905 */ 01906 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) 01907 { 01908 SET_BIT(TIMx->CR2, TIM_CR2_CCPC); 01909 } 01910 01911 /** 01912 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 01913 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01914 * whether or not a timer instance is able to generate a commutation event. 01915 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload 01916 * @param TIMx Timer instance 01917 * @retval None 01918 */ 01919 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) 01920 { 01921 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); 01922 } 01923 01924 /** 01925 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). 01926 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01927 * whether or not a timer instance is able to generate a commutation event. 01928 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate 01929 * @param TIMx Timer instance 01930 * @param CCUpdateSource This parameter can be one of the following values: 01931 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY 01932 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI 01933 * @retval None 01934 */ 01935 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) 01936 { 01937 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); 01938 } 01939 01940 /** 01941 * @brief Set the trigger of the capture/compare DMA request. 01942 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger 01943 * @param TIMx Timer instance 01944 * @param DMAReqTrigger This parameter can be one of the following values: 01945 * @arg @ref LL_TIM_CCDMAREQUEST_CC 01946 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 01947 * @retval None 01948 */ 01949 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) 01950 { 01951 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); 01952 } 01953 01954 /** 01955 * @brief Get actual trigger of the capture/compare DMA request. 01956 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger 01957 * @param TIMx Timer instance 01958 * @retval Returned value can be one of the following values: 01959 * @arg @ref LL_TIM_CCDMAREQUEST_CC 01960 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 01961 */ 01962 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) 01963 { 01964 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); 01965 } 01966 01967 /** 01968 * @brief Set the lock level to freeze the 01969 * configuration of several capture/compare parameters. 01970 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 01971 * the lock mechanism is supported by a timer instance. 01972 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel 01973 * @param TIMx Timer instance 01974 * @param LockLevel This parameter can be one of the following values: 01975 * @arg @ref LL_TIM_LOCKLEVEL_OFF 01976 * @arg @ref LL_TIM_LOCKLEVEL_1 01977 * @arg @ref LL_TIM_LOCKLEVEL_2 01978 * @arg @ref LL_TIM_LOCKLEVEL_3 01979 * @retval None 01980 */ 01981 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) 01982 { 01983 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); 01984 } 01985 01986 /** 01987 * @brief Enable capture/compare channels. 01988 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n 01989 * CCER CC1NE LL_TIM_CC_EnableChannel\n 01990 * CCER CC2E LL_TIM_CC_EnableChannel\n 01991 * CCER CC2NE LL_TIM_CC_EnableChannel\n 01992 * CCER CC3E LL_TIM_CC_EnableChannel\n 01993 * CCER CC3NE LL_TIM_CC_EnableChannel\n 01994 * CCER CC4E LL_TIM_CC_EnableChannel\n 01995 * CCER CC5E LL_TIM_CC_EnableChannel\n 01996 * CCER CC6E LL_TIM_CC_EnableChannel 01997 * @param TIMx Timer instance 01998 * @param Channels This parameter can be a combination of the following values: 01999 * @arg @ref LL_TIM_CHANNEL_CH1 02000 * @arg @ref LL_TIM_CHANNEL_CH1N 02001 * @arg @ref LL_TIM_CHANNEL_CH2 02002 * @arg @ref LL_TIM_CHANNEL_CH2N 02003 * @arg @ref LL_TIM_CHANNEL_CH3 02004 * @arg @ref LL_TIM_CHANNEL_CH3N 02005 * @arg @ref LL_TIM_CHANNEL_CH4 02006 * @arg @ref LL_TIM_CHANNEL_CH5 02007 * @arg @ref LL_TIM_CHANNEL_CH6 02008 * @retval None 02009 */ 02010 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 02011 { 02012 SET_BIT(TIMx->CCER, Channels); 02013 } 02014 02015 /** 02016 * @brief Disable capture/compare channels. 02017 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n 02018 * CCER CC1NE LL_TIM_CC_DisableChannel\n 02019 * CCER CC2E LL_TIM_CC_DisableChannel\n 02020 * CCER CC2NE LL_TIM_CC_DisableChannel\n 02021 * CCER CC3E LL_TIM_CC_DisableChannel\n 02022 * CCER CC3NE LL_TIM_CC_DisableChannel\n 02023 * CCER CC4E LL_TIM_CC_DisableChannel\n 02024 * CCER CC5E LL_TIM_CC_DisableChannel\n 02025 * CCER CC6E LL_TIM_CC_DisableChannel 02026 * @param TIMx Timer instance 02027 * @param Channels This parameter can be a combination of the following values: 02028 * @arg @ref LL_TIM_CHANNEL_CH1 02029 * @arg @ref LL_TIM_CHANNEL_CH1N 02030 * @arg @ref LL_TIM_CHANNEL_CH2 02031 * @arg @ref LL_TIM_CHANNEL_CH2N 02032 * @arg @ref LL_TIM_CHANNEL_CH3 02033 * @arg @ref LL_TIM_CHANNEL_CH3N 02034 * @arg @ref LL_TIM_CHANNEL_CH4 02035 * @arg @ref LL_TIM_CHANNEL_CH5 02036 * @arg @ref LL_TIM_CHANNEL_CH6 02037 * @retval None 02038 */ 02039 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 02040 { 02041 CLEAR_BIT(TIMx->CCER, Channels); 02042 } 02043 02044 /** 02045 * @brief Indicate whether channel(s) is(are) enabled. 02046 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n 02047 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n 02048 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n 02049 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n 02050 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n 02051 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n 02052 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n 02053 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n 02054 * CCER CC6E LL_TIM_CC_IsEnabledChannel 02055 * @param TIMx Timer instance 02056 * @param Channels This parameter can be a combination of the following values: 02057 * @arg @ref LL_TIM_CHANNEL_CH1 02058 * @arg @ref LL_TIM_CHANNEL_CH1N 02059 * @arg @ref LL_TIM_CHANNEL_CH2 02060 * @arg @ref LL_TIM_CHANNEL_CH2N 02061 * @arg @ref LL_TIM_CHANNEL_CH3 02062 * @arg @ref LL_TIM_CHANNEL_CH3N 02063 * @arg @ref LL_TIM_CHANNEL_CH4 02064 * @arg @ref LL_TIM_CHANNEL_CH5 02065 * @arg @ref LL_TIM_CHANNEL_CH6 02066 * @retval State of bit (1 or 0). 02067 */ 02068 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) 02069 { 02070 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); 02071 } 02072 02073 /** 02074 * @} 02075 */ 02076 02077 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration 02078 * @{ 02079 */ 02080 /** 02081 * @brief Configure an output channel. 02082 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n 02083 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n 02084 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n 02085 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n 02086 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n 02087 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n 02088 * CCER CC1P LL_TIM_OC_ConfigOutput\n 02089 * CCER CC2P LL_TIM_OC_ConfigOutput\n 02090 * CCER CC3P LL_TIM_OC_ConfigOutput\n 02091 * CCER CC4P LL_TIM_OC_ConfigOutput\n 02092 * CCER CC5P LL_TIM_OC_ConfigOutput\n 02093 * CCER CC6P LL_TIM_OC_ConfigOutput\n 02094 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n 02095 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n 02096 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n 02097 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n 02098 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n 02099 * CR2 OIS6 LL_TIM_OC_ConfigOutput 02100 * @param TIMx Timer instance 02101 * @param Channel This parameter can be one of the following values: 02102 * @arg @ref LL_TIM_CHANNEL_CH1 02103 * @arg @ref LL_TIM_CHANNEL_CH2 02104 * @arg @ref LL_TIM_CHANNEL_CH3 02105 * @arg @ref LL_TIM_CHANNEL_CH4 02106 * @arg @ref LL_TIM_CHANNEL_CH5 02107 * @arg @ref LL_TIM_CHANNEL_CH6 02108 * @param Configuration This parameter must be a combination of all the following values: 02109 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW 02110 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH 02111 * @retval None 02112 */ 02113 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 02114 { 02115 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02116 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02117 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); 02118 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), 02119 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); 02120 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), 02121 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); 02122 } 02123 02124 /** 02125 * @brief Define the behavior of the output reference signal OCxREF from which 02126 * OCx and OCxN (when relevant) are derived. 02127 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n 02128 * CCMR1 OC2M LL_TIM_OC_SetMode\n 02129 * CCMR2 OC3M LL_TIM_OC_SetMode\n 02130 * CCMR2 OC4M LL_TIM_OC_SetMode\n 02131 * CCMR3 OC5M LL_TIM_OC_SetMode\n 02132 * CCMR3 OC6M LL_TIM_OC_SetMode 02133 * @param TIMx Timer instance 02134 * @param Channel This parameter can be one of the following values: 02135 * @arg @ref LL_TIM_CHANNEL_CH1 02136 * @arg @ref LL_TIM_CHANNEL_CH2 02137 * @arg @ref LL_TIM_CHANNEL_CH3 02138 * @arg @ref LL_TIM_CHANNEL_CH4 02139 * @arg @ref LL_TIM_CHANNEL_CH5 02140 * @arg @ref LL_TIM_CHANNEL_CH6 02141 * @param Mode This parameter can be one of the following values: 02142 * @arg @ref LL_TIM_OCMODE_FROZEN 02143 * @arg @ref LL_TIM_OCMODE_ACTIVE 02144 * @arg @ref LL_TIM_OCMODE_INACTIVE 02145 * @arg @ref LL_TIM_OCMODE_TOGGLE 02146 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 02147 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 02148 * @arg @ref LL_TIM_OCMODE_PWM1 02149 * @arg @ref LL_TIM_OCMODE_PWM2 02150 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 02151 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 02152 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 02153 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 02154 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 02155 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 02156 * @retval None 02157 */ 02158 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) 02159 { 02160 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02161 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02162 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); 02163 } 02164 02165 /** 02166 * @brief Get the output compare mode of an output channel. 02167 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n 02168 * CCMR1 OC2M LL_TIM_OC_GetMode\n 02169 * CCMR2 OC3M LL_TIM_OC_GetMode\n 02170 * CCMR2 OC4M LL_TIM_OC_GetMode\n 02171 * CCMR3 OC5M LL_TIM_OC_GetMode\n 02172 * CCMR3 OC6M LL_TIM_OC_GetMode 02173 * @param TIMx Timer instance 02174 * @param Channel This parameter can be one of the following values: 02175 * @arg @ref LL_TIM_CHANNEL_CH1 02176 * @arg @ref LL_TIM_CHANNEL_CH2 02177 * @arg @ref LL_TIM_CHANNEL_CH3 02178 * @arg @ref LL_TIM_CHANNEL_CH4 02179 * @arg @ref LL_TIM_CHANNEL_CH5 02180 * @arg @ref LL_TIM_CHANNEL_CH6 02181 * @retval Returned value can be one of the following values: 02182 * @arg @ref LL_TIM_OCMODE_FROZEN 02183 * @arg @ref LL_TIM_OCMODE_ACTIVE 02184 * @arg @ref LL_TIM_OCMODE_INACTIVE 02185 * @arg @ref LL_TIM_OCMODE_TOGGLE 02186 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 02187 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 02188 * @arg @ref LL_TIM_OCMODE_PWM1 02189 * @arg @ref LL_TIM_OCMODE_PWM2 02190 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 02191 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 02192 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 02193 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 02194 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 02195 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 02196 */ 02197 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) 02198 { 02199 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02200 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02201 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); 02202 } 02203 02204 /** 02205 * @brief Set the polarity of an output channel. 02206 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n 02207 * CCER CC1NP LL_TIM_OC_SetPolarity\n 02208 * CCER CC2P LL_TIM_OC_SetPolarity\n 02209 * CCER CC2NP LL_TIM_OC_SetPolarity\n 02210 * CCER CC3P LL_TIM_OC_SetPolarity\n 02211 * CCER CC3NP LL_TIM_OC_SetPolarity\n 02212 * CCER CC4P LL_TIM_OC_SetPolarity\n 02213 * CCER CC5P LL_TIM_OC_SetPolarity\n 02214 * CCER CC6P LL_TIM_OC_SetPolarity 02215 * @param TIMx Timer instance 02216 * @param Channel This parameter can be one of the following values: 02217 * @arg @ref LL_TIM_CHANNEL_CH1 02218 * @arg @ref LL_TIM_CHANNEL_CH1N 02219 * @arg @ref LL_TIM_CHANNEL_CH2 02220 * @arg @ref LL_TIM_CHANNEL_CH2N 02221 * @arg @ref LL_TIM_CHANNEL_CH3 02222 * @arg @ref LL_TIM_CHANNEL_CH3N 02223 * @arg @ref LL_TIM_CHANNEL_CH4 02224 * @arg @ref LL_TIM_CHANNEL_CH5 02225 * @arg @ref LL_TIM_CHANNEL_CH6 02226 * @param Polarity This parameter can be one of the following values: 02227 * @arg @ref LL_TIM_OCPOLARITY_HIGH 02228 * @arg @ref LL_TIM_OCPOLARITY_LOW 02229 * @retval None 02230 */ 02231 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) 02232 { 02233 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02234 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); 02235 } 02236 02237 /** 02238 * @brief Get the polarity of an output channel. 02239 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n 02240 * CCER CC1NP LL_TIM_OC_GetPolarity\n 02241 * CCER CC2P LL_TIM_OC_GetPolarity\n 02242 * CCER CC2NP LL_TIM_OC_GetPolarity\n 02243 * CCER CC3P LL_TIM_OC_GetPolarity\n 02244 * CCER CC3NP LL_TIM_OC_GetPolarity\n 02245 * CCER CC4P LL_TIM_OC_GetPolarity\n 02246 * CCER CC5P LL_TIM_OC_GetPolarity\n 02247 * CCER CC6P LL_TIM_OC_GetPolarity 02248 * @param TIMx Timer instance 02249 * @param Channel This parameter can be one of the following values: 02250 * @arg @ref LL_TIM_CHANNEL_CH1 02251 * @arg @ref LL_TIM_CHANNEL_CH1N 02252 * @arg @ref LL_TIM_CHANNEL_CH2 02253 * @arg @ref LL_TIM_CHANNEL_CH2N 02254 * @arg @ref LL_TIM_CHANNEL_CH3 02255 * @arg @ref LL_TIM_CHANNEL_CH3N 02256 * @arg @ref LL_TIM_CHANNEL_CH4 02257 * @arg @ref LL_TIM_CHANNEL_CH5 02258 * @arg @ref LL_TIM_CHANNEL_CH6 02259 * @retval Returned value can be one of the following values: 02260 * @arg @ref LL_TIM_OCPOLARITY_HIGH 02261 * @arg @ref LL_TIM_OCPOLARITY_LOW 02262 */ 02263 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) 02264 { 02265 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02266 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); 02267 } 02268 02269 /** 02270 * @brief Set the IDLE state of an output channel 02271 * @note This function is significant only for the timer instances 02272 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) 02273 * can be used to check whether or not a timer instance provides 02274 * a break input. 02275 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n 02276 * CR2 OIS2N LL_TIM_OC_SetIdleState\n 02277 * CR2 OIS2 LL_TIM_OC_SetIdleState\n 02278 * CR2 OIS2N LL_TIM_OC_SetIdleState\n 02279 * CR2 OIS3 LL_TIM_OC_SetIdleState\n 02280 * CR2 OIS3N LL_TIM_OC_SetIdleState\n 02281 * CR2 OIS4 LL_TIM_OC_SetIdleState\n 02282 * CR2 OIS5 LL_TIM_OC_SetIdleState\n 02283 * CR2 OIS6 LL_TIM_OC_SetIdleState 02284 * @param TIMx Timer instance 02285 * @param Channel This parameter can be one of the following values: 02286 * @arg @ref LL_TIM_CHANNEL_CH1 02287 * @arg @ref LL_TIM_CHANNEL_CH1N 02288 * @arg @ref LL_TIM_CHANNEL_CH2 02289 * @arg @ref LL_TIM_CHANNEL_CH2N 02290 * @arg @ref LL_TIM_CHANNEL_CH3 02291 * @arg @ref LL_TIM_CHANNEL_CH3N 02292 * @arg @ref LL_TIM_CHANNEL_CH4 02293 * @arg @ref LL_TIM_CHANNEL_CH5 02294 * @arg @ref LL_TIM_CHANNEL_CH6 02295 * @param IdleState This parameter can be one of the following values: 02296 * @arg @ref LL_TIM_OCIDLESTATE_LOW 02297 * @arg @ref LL_TIM_OCIDLESTATE_HIGH 02298 * @retval None 02299 */ 02300 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) 02301 { 02302 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02303 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); 02304 } 02305 02306 /** 02307 * @brief Get the IDLE state of an output channel 02308 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n 02309 * CR2 OIS2N LL_TIM_OC_GetIdleState\n 02310 * CR2 OIS2 LL_TIM_OC_GetIdleState\n 02311 * CR2 OIS2N LL_TIM_OC_GetIdleState\n 02312 * CR2 OIS3 LL_TIM_OC_GetIdleState\n 02313 * CR2 OIS3N LL_TIM_OC_GetIdleState\n 02314 * CR2 OIS4 LL_TIM_OC_GetIdleState\n 02315 * CR2 OIS5 LL_TIM_OC_GetIdleState\n 02316 * CR2 OIS6 LL_TIM_OC_GetIdleState 02317 * @param TIMx Timer instance 02318 * @param Channel This parameter can be one of the following values: 02319 * @arg @ref LL_TIM_CHANNEL_CH1 02320 * @arg @ref LL_TIM_CHANNEL_CH1N 02321 * @arg @ref LL_TIM_CHANNEL_CH2 02322 * @arg @ref LL_TIM_CHANNEL_CH2N 02323 * @arg @ref LL_TIM_CHANNEL_CH3 02324 * @arg @ref LL_TIM_CHANNEL_CH3N 02325 * @arg @ref LL_TIM_CHANNEL_CH4 02326 * @arg @ref LL_TIM_CHANNEL_CH5 02327 * @arg @ref LL_TIM_CHANNEL_CH6 02328 * @retval Returned value can be one of the following values: 02329 * @arg @ref LL_TIM_OCIDLESTATE_LOW 02330 * @arg @ref LL_TIM_OCIDLESTATE_HIGH 02331 */ 02332 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) 02333 { 02334 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02335 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); 02336 } 02337 02338 /** 02339 * @brief Enable fast mode for the output channel. 02340 * @note Acts only if the channel is configured in PWM1 or PWM2 mode. 02341 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n 02342 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n 02343 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n 02344 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n 02345 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n 02346 * CCMR3 OC6FE LL_TIM_OC_EnableFast 02347 * @param TIMx Timer instance 02348 * @param Channel This parameter can be one of the following values: 02349 * @arg @ref LL_TIM_CHANNEL_CH1 02350 * @arg @ref LL_TIM_CHANNEL_CH2 02351 * @arg @ref LL_TIM_CHANNEL_CH3 02352 * @arg @ref LL_TIM_CHANNEL_CH4 02353 * @arg @ref LL_TIM_CHANNEL_CH5 02354 * @arg @ref LL_TIM_CHANNEL_CH6 02355 * @retval None 02356 */ 02357 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) 02358 { 02359 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02360 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02361 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 02362 02363 } 02364 02365 /** 02366 * @brief Disable fast mode for the output channel. 02367 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n 02368 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n 02369 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n 02370 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n 02371 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n 02372 * CCMR3 OC6FE LL_TIM_OC_DisableFast 02373 * @param TIMx Timer instance 02374 * @param Channel This parameter can be one of the following values: 02375 * @arg @ref LL_TIM_CHANNEL_CH1 02376 * @arg @ref LL_TIM_CHANNEL_CH2 02377 * @arg @ref LL_TIM_CHANNEL_CH3 02378 * @arg @ref LL_TIM_CHANNEL_CH4 02379 * @arg @ref LL_TIM_CHANNEL_CH5 02380 * @arg @ref LL_TIM_CHANNEL_CH6 02381 * @retval None 02382 */ 02383 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) 02384 { 02385 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02386 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02387 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 02388 02389 } 02390 02391 /** 02392 * @brief Indicates whether fast mode is enabled for the output channel. 02393 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n 02394 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n 02395 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n 02396 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n 02397 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n 02398 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast 02399 * @param TIMx Timer instance 02400 * @param Channel This parameter can be one of the following values: 02401 * @arg @ref LL_TIM_CHANNEL_CH1 02402 * @arg @ref LL_TIM_CHANNEL_CH2 02403 * @arg @ref LL_TIM_CHANNEL_CH3 02404 * @arg @ref LL_TIM_CHANNEL_CH4 02405 * @arg @ref LL_TIM_CHANNEL_CH5 02406 * @arg @ref LL_TIM_CHANNEL_CH6 02407 * @retval State of bit (1 or 0). 02408 */ 02409 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) 02410 { 02411 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02412 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02413 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; 02414 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 02415 } 02416 02417 /** 02418 * @brief Enable compare register (TIMx_CCRx) preload for the output channel. 02419 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n 02420 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n 02421 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n 02422 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n 02423 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n 02424 * CCMR3 OC6PE LL_TIM_OC_EnablePreload 02425 * @param TIMx Timer instance 02426 * @param Channel This parameter can be one of the following values: 02427 * @arg @ref LL_TIM_CHANNEL_CH1 02428 * @arg @ref LL_TIM_CHANNEL_CH2 02429 * @arg @ref LL_TIM_CHANNEL_CH3 02430 * @arg @ref LL_TIM_CHANNEL_CH4 02431 * @arg @ref LL_TIM_CHANNEL_CH5 02432 * @arg @ref LL_TIM_CHANNEL_CH6 02433 * @retval None 02434 */ 02435 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 02436 { 02437 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02438 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02439 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 02440 } 02441 02442 /** 02443 * @brief Disable compare register (TIMx_CCRx) preload for the output channel. 02444 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n 02445 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n 02446 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n 02447 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n 02448 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n 02449 * CCMR3 OC6PE LL_TIM_OC_DisablePreload 02450 * @param TIMx Timer instance 02451 * @param Channel This parameter can be one of the following values: 02452 * @arg @ref LL_TIM_CHANNEL_CH1 02453 * @arg @ref LL_TIM_CHANNEL_CH2 02454 * @arg @ref LL_TIM_CHANNEL_CH3 02455 * @arg @ref LL_TIM_CHANNEL_CH4 02456 * @arg @ref LL_TIM_CHANNEL_CH5 02457 * @arg @ref LL_TIM_CHANNEL_CH6 02458 * @retval None 02459 */ 02460 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 02461 { 02462 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02463 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02464 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 02465 } 02466 02467 /** 02468 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. 02469 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n 02470 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n 02471 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n 02472 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n 02473 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n 02474 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload 02475 * @param TIMx Timer instance 02476 * @param Channel This parameter can be one of the following values: 02477 * @arg @ref LL_TIM_CHANNEL_CH1 02478 * @arg @ref LL_TIM_CHANNEL_CH2 02479 * @arg @ref LL_TIM_CHANNEL_CH3 02480 * @arg @ref LL_TIM_CHANNEL_CH4 02481 * @arg @ref LL_TIM_CHANNEL_CH5 02482 * @arg @ref LL_TIM_CHANNEL_CH6 02483 * @retval State of bit (1 or 0). 02484 */ 02485 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) 02486 { 02487 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02488 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02489 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; 02490 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 02491 } 02492 02493 /** 02494 * @brief Enable clearing the output channel on an external event. 02495 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 02496 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 02497 * or not a timer instance can clear the OCxREF signal on an external event. 02498 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n 02499 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n 02500 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n 02501 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n 02502 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n 02503 * CCMR3 OC6CE LL_TIM_OC_EnableClear 02504 * @param TIMx Timer instance 02505 * @param Channel This parameter can be one of the following values: 02506 * @arg @ref LL_TIM_CHANNEL_CH1 02507 * @arg @ref LL_TIM_CHANNEL_CH2 02508 * @arg @ref LL_TIM_CHANNEL_CH3 02509 * @arg @ref LL_TIM_CHANNEL_CH4 02510 * @arg @ref LL_TIM_CHANNEL_CH5 02511 * @arg @ref LL_TIM_CHANNEL_CH6 02512 * @retval None 02513 */ 02514 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) 02515 { 02516 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02517 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02518 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 02519 } 02520 02521 /** 02522 * @brief Disable clearing the output channel on an external event. 02523 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 02524 * or not a timer instance can clear the OCxREF signal on an external event. 02525 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n 02526 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n 02527 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n 02528 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n 02529 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n 02530 * CCMR3 OC6CE LL_TIM_OC_DisableClear 02531 * @param TIMx Timer instance 02532 * @param Channel This parameter can be one of the following values: 02533 * @arg @ref LL_TIM_CHANNEL_CH1 02534 * @arg @ref LL_TIM_CHANNEL_CH2 02535 * @arg @ref LL_TIM_CHANNEL_CH3 02536 * @arg @ref LL_TIM_CHANNEL_CH4 02537 * @arg @ref LL_TIM_CHANNEL_CH5 02538 * @arg @ref LL_TIM_CHANNEL_CH6 02539 * @retval None 02540 */ 02541 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) 02542 { 02543 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02544 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02545 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 02546 } 02547 02548 /** 02549 * @brief Indicates clearing the output channel on an external event is enabled for the output channel. 02550 * @note This function enables clearing the output channel on an external event. 02551 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 02552 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 02553 * or not a timer instance can clear the OCxREF signal on an external event. 02554 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n 02555 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n 02556 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n 02557 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n 02558 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n 02559 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear 02560 * @param TIMx Timer instance 02561 * @param Channel This parameter can be one of the following values: 02562 * @arg @ref LL_TIM_CHANNEL_CH1 02563 * @arg @ref LL_TIM_CHANNEL_CH2 02564 * @arg @ref LL_TIM_CHANNEL_CH3 02565 * @arg @ref LL_TIM_CHANNEL_CH4 02566 * @arg @ref LL_TIM_CHANNEL_CH5 02567 * @arg @ref LL_TIM_CHANNEL_CH6 02568 * @retval State of bit (1 or 0). 02569 */ 02570 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) 02571 { 02572 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02573 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02574 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; 02575 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 02576 } 02577 02578 /** 02579 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of 02580 * the Ocx and OCxN signals). 02581 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02582 * dead-time insertion feature is supported by a timer instance. 02583 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter 02584 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime 02585 * @param TIMx Timer instance 02586 * @param DeadTime between Min_Data=0 and Max_Data=255 02587 * @retval None 02588 */ 02589 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) 02590 { 02591 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); 02592 } 02593 02594 /** 02595 * @brief Set compare value for output channel 1 (TIMx_CCR1). 02596 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02597 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02598 * whether or not a timer instance supports a 32 bits counter. 02599 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 02600 * output channel 1 is supported by a timer instance. 02601 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 02602 * @param TIMx Timer instance 02603 * @param CompareValue between Min_Data=0 and Max_Data=65535 02604 * @retval None 02605 */ 02606 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) 02607 { 02608 WRITE_REG(TIMx->CCR1, CompareValue); 02609 } 02610 02611 /** 02612 * @brief Set compare value for output channel 2 (TIMx_CCR2). 02613 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02614 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02615 * whether or not a timer instance supports a 32 bits counter. 02616 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 02617 * output channel 2 is supported by a timer instance. 02618 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 02619 * @param TIMx Timer instance 02620 * @param CompareValue between Min_Data=0 and Max_Data=65535 02621 * @retval None 02622 */ 02623 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) 02624 { 02625 WRITE_REG(TIMx->CCR2, CompareValue); 02626 } 02627 02628 /** 02629 * @brief Set compare value for output channel 3 (TIMx_CCR3). 02630 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02631 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02632 * whether or not a timer instance supports a 32 bits counter. 02633 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 02634 * output channel is supported by a timer instance. 02635 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 02636 * @param TIMx Timer instance 02637 * @param CompareValue between Min_Data=0 and Max_Data=65535 02638 * @retval None 02639 */ 02640 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) 02641 { 02642 WRITE_REG(TIMx->CCR3, CompareValue); 02643 } 02644 02645 /** 02646 * @brief Set compare value for output channel 4 (TIMx_CCR4). 02647 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02648 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02649 * whether or not a timer instance supports a 32 bits counter. 02650 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 02651 * output channel 4 is supported by a timer instance. 02652 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 02653 * @param TIMx Timer instance 02654 * @param CompareValue between Min_Data=0 and Max_Data=65535 02655 * @retval None 02656 */ 02657 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) 02658 { 02659 WRITE_REG(TIMx->CCR4, CompareValue); 02660 } 02661 02662 /** 02663 * @brief Set compare value for output channel 5 (TIMx_CCR5). 02664 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 02665 * output channel 5 is supported by a timer instance. 02666 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 02667 * @param TIMx Timer instance 02668 * @param CompareValue between Min_Data=0 and Max_Data=65535 02669 * @retval None 02670 */ 02671 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) 02672 { 02673 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); 02674 } 02675 02676 /** 02677 * @brief Set compare value for output channel 6 (TIMx_CCR6). 02678 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 02679 * output channel 6 is supported by a timer instance. 02680 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 02681 * @param TIMx Timer instance 02682 * @param CompareValue between Min_Data=0 and Max_Data=65535 02683 * @retval None 02684 */ 02685 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) 02686 { 02687 WRITE_REG(TIMx->CCR6, CompareValue); 02688 } 02689 02690 /** 02691 * @brief Get compare value (TIMx_CCR1) set for output channel 1. 02692 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02693 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02694 * whether or not a timer instance supports a 32 bits counter. 02695 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 02696 * output channel 1 is supported by a timer instance. 02697 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 02698 * @param TIMx Timer instance 02699 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02700 */ 02701 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) 02702 { 02703 return (uint32_t)(READ_REG(TIMx->CCR1)); 02704 } 02705 02706 /** 02707 * @brief Get compare value (TIMx_CCR2) set for output channel 2. 02708 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02709 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02710 * whether or not a timer instance supports a 32 bits counter. 02711 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 02712 * output channel 2 is supported by a timer instance. 02713 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 02714 * @param TIMx Timer instance 02715 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02716 */ 02717 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) 02718 { 02719 return (uint32_t)(READ_REG(TIMx->CCR2)); 02720 } 02721 02722 /** 02723 * @brief Get compare value (TIMx_CCR3) set for output channel 3. 02724 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02725 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02726 * whether or not a timer instance supports a 32 bits counter. 02727 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 02728 * output channel 3 is supported by a timer instance. 02729 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 02730 * @param TIMx Timer instance 02731 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02732 */ 02733 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) 02734 { 02735 return (uint32_t)(READ_REG(TIMx->CCR3)); 02736 } 02737 02738 /** 02739 * @brief Get compare value (TIMx_CCR4) set for output channel 4. 02740 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02741 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02742 * whether or not a timer instance supports a 32 bits counter. 02743 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 02744 * output channel 4 is supported by a timer instance. 02745 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 02746 * @param TIMx Timer instance 02747 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02748 */ 02749 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) 02750 { 02751 return (uint32_t)(READ_REG(TIMx->CCR4)); 02752 } 02753 02754 /** 02755 * @brief Get compare value (TIMx_CCR5) set for output channel 5. 02756 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 02757 * output channel 5 is supported by a timer instance. 02758 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 02759 * @param TIMx Timer instance 02760 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02761 */ 02762 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) 02763 { 02764 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); 02765 } 02766 02767 /** 02768 * @brief Get compare value (TIMx_CCR6) set for output channel 6. 02769 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 02770 * output channel 6 is supported by a timer instance. 02771 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 02772 * @param TIMx Timer instance 02773 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02774 */ 02775 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) 02776 { 02777 return (uint32_t)(READ_REG(TIMx->CCR6)); 02778 } 02779 02780 /** 02781 * @brief Select on which reference signal the OC5REF is combined to. 02782 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check 02783 * whether or not a timer instance supports the combined 3-phase PWM mode. 02784 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n 02785 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n 02786 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels 02787 * @param TIMx Timer instance 02788 * @param GroupCH5 This parameter can be a combination of the following values: 02789 * @arg @ref LL_TIM_GROUPCH5_NONE 02790 * @arg @ref LL_TIM_GROUPCH5_OC1REFC 02791 * @arg @ref LL_TIM_GROUPCH5_OC2REFC 02792 * @arg @ref LL_TIM_GROUPCH5_OC3REFC 02793 * @retval None 02794 */ 02795 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) 02796 { 02797 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); 02798 } 02799 02800 /** 02801 * @} 02802 */ 02803 02804 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration 02805 * @{ 02806 */ 02807 /** 02808 * @brief Configure input channel. 02809 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n 02810 * CCMR1 IC1PSC LL_TIM_IC_Config\n 02811 * CCMR1 IC1F LL_TIM_IC_Config\n 02812 * CCMR1 CC2S LL_TIM_IC_Config\n 02813 * CCMR1 IC2PSC LL_TIM_IC_Config\n 02814 * CCMR1 IC2F LL_TIM_IC_Config\n 02815 * CCMR2 CC3S LL_TIM_IC_Config\n 02816 * CCMR2 IC3PSC LL_TIM_IC_Config\n 02817 * CCMR2 IC3F LL_TIM_IC_Config\n 02818 * CCMR2 CC4S LL_TIM_IC_Config\n 02819 * CCMR2 IC4PSC LL_TIM_IC_Config\n 02820 * CCMR2 IC4F LL_TIM_IC_Config\n 02821 * CCER CC1P LL_TIM_IC_Config\n 02822 * CCER CC1NP LL_TIM_IC_Config\n 02823 * CCER CC2P LL_TIM_IC_Config\n 02824 * CCER CC2NP LL_TIM_IC_Config\n 02825 * CCER CC3P LL_TIM_IC_Config\n 02826 * CCER CC3NP LL_TIM_IC_Config\n 02827 * CCER CC4P LL_TIM_IC_Config\n 02828 * CCER CC4NP LL_TIM_IC_Config 02829 * @param TIMx Timer instance 02830 * @param Channel This parameter can be one of the following values: 02831 * @arg @ref LL_TIM_CHANNEL_CH1 02832 * @arg @ref LL_TIM_CHANNEL_CH2 02833 * @arg @ref LL_TIM_CHANNEL_CH3 02834 * @arg @ref LL_TIM_CHANNEL_CH4 02835 * @param Configuration This parameter must be a combination of all the following values: 02836 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC 02837 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 02838 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 02839 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE 02840 * @retval None 02841 */ 02842 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 02843 { 02844 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02845 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02846 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), 02847 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ 02848 << SHIFT_TAB_ICxx[iChannel]); 02849 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 02850 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); 02851 } 02852 02853 /** 02854 * @brief Set the active input. 02855 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n 02856 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n 02857 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n 02858 * CCMR2 CC4S LL_TIM_IC_SetActiveInput 02859 * @param TIMx Timer instance 02860 * @param Channel This parameter can be one of the following values: 02861 * @arg @ref LL_TIM_CHANNEL_CH1 02862 * @arg @ref LL_TIM_CHANNEL_CH2 02863 * @arg @ref LL_TIM_CHANNEL_CH3 02864 * @arg @ref LL_TIM_CHANNEL_CH4 02865 * @param ICActiveInput This parameter can be one of the following values: 02866 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 02867 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 02868 * @arg @ref LL_TIM_ACTIVEINPUT_TRC 02869 * @retval None 02870 */ 02871 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) 02872 { 02873 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02874 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02875 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02876 } 02877 02878 /** 02879 * @brief Get the current active input. 02880 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n 02881 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n 02882 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n 02883 * CCMR2 CC4S LL_TIM_IC_GetActiveInput 02884 * @param TIMx Timer instance 02885 * @param Channel This parameter can be one of the following values: 02886 * @arg @ref LL_TIM_CHANNEL_CH1 02887 * @arg @ref LL_TIM_CHANNEL_CH2 02888 * @arg @ref LL_TIM_CHANNEL_CH3 02889 * @arg @ref LL_TIM_CHANNEL_CH4 02890 * @retval Returned value can be one of the following values: 02891 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 02892 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 02893 * @arg @ref LL_TIM_ACTIVEINPUT_TRC 02894 */ 02895 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) 02896 { 02897 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02898 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02899 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 02900 } 02901 02902 /** 02903 * @brief Set the prescaler of input channel. 02904 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n 02905 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n 02906 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n 02907 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler 02908 * @param TIMx Timer instance 02909 * @param Channel This parameter can be one of the following values: 02910 * @arg @ref LL_TIM_CHANNEL_CH1 02911 * @arg @ref LL_TIM_CHANNEL_CH2 02912 * @arg @ref LL_TIM_CHANNEL_CH3 02913 * @arg @ref LL_TIM_CHANNEL_CH4 02914 * @param ICPrescaler This parameter can be one of the following values: 02915 * @arg @ref LL_TIM_ICPSC_DIV1 02916 * @arg @ref LL_TIM_ICPSC_DIV2 02917 * @arg @ref LL_TIM_ICPSC_DIV4 02918 * @arg @ref LL_TIM_ICPSC_DIV8 02919 * @retval None 02920 */ 02921 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) 02922 { 02923 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02924 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02925 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02926 } 02927 02928 /** 02929 * @brief Get the current prescaler value acting on an input channel. 02930 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n 02931 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n 02932 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n 02933 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler 02934 * @param TIMx Timer instance 02935 * @param Channel This parameter can be one of the following values: 02936 * @arg @ref LL_TIM_CHANNEL_CH1 02937 * @arg @ref LL_TIM_CHANNEL_CH2 02938 * @arg @ref LL_TIM_CHANNEL_CH3 02939 * @arg @ref LL_TIM_CHANNEL_CH4 02940 * @retval Returned value can be one of the following values: 02941 * @arg @ref LL_TIM_ICPSC_DIV1 02942 * @arg @ref LL_TIM_ICPSC_DIV2 02943 * @arg @ref LL_TIM_ICPSC_DIV4 02944 * @arg @ref LL_TIM_ICPSC_DIV8 02945 */ 02946 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) 02947 { 02948 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02949 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02950 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 02951 } 02952 02953 /** 02954 * @brief Set the input filter duration. 02955 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n 02956 * CCMR1 IC2F LL_TIM_IC_SetFilter\n 02957 * CCMR2 IC3F LL_TIM_IC_SetFilter\n 02958 * CCMR2 IC4F LL_TIM_IC_SetFilter 02959 * @param TIMx Timer instance 02960 * @param Channel This parameter can be one of the following values: 02961 * @arg @ref LL_TIM_CHANNEL_CH1 02962 * @arg @ref LL_TIM_CHANNEL_CH2 02963 * @arg @ref LL_TIM_CHANNEL_CH3 02964 * @arg @ref LL_TIM_CHANNEL_CH4 02965 * @param ICFilter This parameter can be one of the following values: 02966 * @arg @ref LL_TIM_IC_FILTER_FDIV1 02967 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 02968 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 02969 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 02970 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 02971 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 02972 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 02973 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 02974 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 02975 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 02976 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 02977 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 02978 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 02979 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 02980 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 02981 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 02982 * @retval None 02983 */ 02984 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) 02985 { 02986 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02987 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02988 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02989 } 02990 02991 /** 02992 * @brief Get the input filter duration. 02993 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n 02994 * CCMR1 IC2F LL_TIM_IC_GetFilter\n 02995 * CCMR2 IC3F LL_TIM_IC_GetFilter\n 02996 * CCMR2 IC4F LL_TIM_IC_GetFilter 02997 * @param TIMx Timer instance 02998 * @param Channel This parameter can be one of the following values: 02999 * @arg @ref LL_TIM_CHANNEL_CH1 03000 * @arg @ref LL_TIM_CHANNEL_CH2 03001 * @arg @ref LL_TIM_CHANNEL_CH3 03002 * @arg @ref LL_TIM_CHANNEL_CH4 03003 * @retval Returned value can be one of the following values: 03004 * @arg @ref LL_TIM_IC_FILTER_FDIV1 03005 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 03006 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 03007 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 03008 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 03009 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 03010 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 03011 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 03012 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 03013 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 03014 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 03015 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 03016 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 03017 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 03018 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 03019 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 03020 */ 03021 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) 03022 { 03023 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 03024 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 03025 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 03026 } 03027 03028 /** 03029 * @brief Set the input channel polarity. 03030 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n 03031 * CCER CC1NP LL_TIM_IC_SetPolarity\n 03032 * CCER CC2P LL_TIM_IC_SetPolarity\n 03033 * CCER CC2NP LL_TIM_IC_SetPolarity\n 03034 * CCER CC3P LL_TIM_IC_SetPolarity\n 03035 * CCER CC3NP LL_TIM_IC_SetPolarity\n 03036 * CCER CC4P LL_TIM_IC_SetPolarity\n 03037 * CCER CC4NP LL_TIM_IC_SetPolarity 03038 * @param TIMx Timer instance 03039 * @param Channel This parameter can be one of the following values: 03040 * @arg @ref LL_TIM_CHANNEL_CH1 03041 * @arg @ref LL_TIM_CHANNEL_CH2 03042 * @arg @ref LL_TIM_CHANNEL_CH3 03043 * @arg @ref LL_TIM_CHANNEL_CH4 03044 * @param ICPolarity This parameter can be one of the following values: 03045 * @arg @ref LL_TIM_IC_POLARITY_RISING 03046 * @arg @ref LL_TIM_IC_POLARITY_FALLING 03047 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 03048 * @retval None 03049 */ 03050 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) 03051 { 03052 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 03053 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 03054 ICPolarity << SHIFT_TAB_CCxP[iChannel]); 03055 } 03056 03057 /** 03058 * @brief Get the current input channel polarity. 03059 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n 03060 * CCER CC1NP LL_TIM_IC_GetPolarity\n 03061 * CCER CC2P LL_TIM_IC_GetPolarity\n 03062 * CCER CC2NP LL_TIM_IC_GetPolarity\n 03063 * CCER CC3P LL_TIM_IC_GetPolarity\n 03064 * CCER CC3NP LL_TIM_IC_GetPolarity\n 03065 * CCER CC4P LL_TIM_IC_GetPolarity\n 03066 * CCER CC4NP LL_TIM_IC_GetPolarity 03067 * @param TIMx Timer instance 03068 * @param Channel This parameter can be one of the following values: 03069 * @arg @ref LL_TIM_CHANNEL_CH1 03070 * @arg @ref LL_TIM_CHANNEL_CH2 03071 * @arg @ref LL_TIM_CHANNEL_CH3 03072 * @arg @ref LL_TIM_CHANNEL_CH4 03073 * @retval Returned value can be one of the following values: 03074 * @arg @ref LL_TIM_IC_POLARITY_RISING 03075 * @arg @ref LL_TIM_IC_POLARITY_FALLING 03076 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 03077 */ 03078 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) 03079 { 03080 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 03081 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> 03082 SHIFT_TAB_CCxP[iChannel]); 03083 } 03084 03085 /** 03086 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). 03087 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 03088 * a timer instance provides an XOR input. 03089 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination 03090 * @param TIMx Timer instance 03091 * @retval None 03092 */ 03093 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) 03094 { 03095 SET_BIT(TIMx->CR2, TIM_CR2_TI1S); 03096 } 03097 03098 /** 03099 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. 03100 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 03101 * a timer instance provides an XOR input. 03102 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination 03103 * @param TIMx Timer instance 03104 * @retval None 03105 */ 03106 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) 03107 { 03108 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); 03109 } 03110 03111 /** 03112 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. 03113 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 03114 * a timer instance provides an XOR input. 03115 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination 03116 * @param TIMx Timer instance 03117 * @retval State of bit (1 or 0). 03118 */ 03119 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) 03120 { 03121 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); 03122 } 03123 03124 /** 03125 * @brief Get captured value for input channel 1. 03126 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 03127 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 03128 * whether or not a timer instance supports a 32 bits counter. 03129 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 03130 * input channel 1 is supported by a timer instance. 03131 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 03132 * @param TIMx Timer instance 03133 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 03134 */ 03135 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) 03136 { 03137 return (uint32_t)(READ_REG(TIMx->CCR1)); 03138 } 03139 03140 /** 03141 * @brief Get captured value for input channel 2. 03142 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 03143 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 03144 * whether or not a timer instance supports a 32 bits counter. 03145 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 03146 * input channel 2 is supported by a timer instance. 03147 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 03148 * @param TIMx Timer instance 03149 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 03150 */ 03151 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) 03152 { 03153 return (uint32_t)(READ_REG(TIMx->CCR2)); 03154 } 03155 03156 /** 03157 * @brief Get captured value for input channel 3. 03158 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 03159 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 03160 * whether or not a timer instance supports a 32 bits counter. 03161 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 03162 * input channel 3 is supported by a timer instance. 03163 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 03164 * @param TIMx Timer instance 03165 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 03166 */ 03167 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) 03168 { 03169 return (uint32_t)(READ_REG(TIMx->CCR3)); 03170 } 03171 03172 /** 03173 * @brief Get captured value for input channel 4. 03174 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 03175 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 03176 * whether or not a timer instance supports a 32 bits counter. 03177 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 03178 * input channel 4 is supported by a timer instance. 03179 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 03180 * @param TIMx Timer instance 03181 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 03182 */ 03183 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) 03184 { 03185 return (uint32_t)(READ_REG(TIMx->CCR4)); 03186 } 03187 03188 /** 03189 * @} 03190 */ 03191 03192 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection 03193 * @{ 03194 */ 03195 /** 03196 * @brief Enable external clock mode 2. 03197 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. 03198 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03199 * whether or not a timer instance supports external clock mode2. 03200 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock 03201 * @param TIMx Timer instance 03202 * @retval None 03203 */ 03204 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) 03205 { 03206 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); 03207 } 03208 03209 /** 03210 * @brief Disable external clock mode 2. 03211 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03212 * whether or not a timer instance supports external clock mode2. 03213 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock 03214 * @param TIMx Timer instance 03215 * @retval None 03216 */ 03217 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) 03218 { 03219 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); 03220 } 03221 03222 /** 03223 * @brief Indicate whether external clock mode 2 is enabled. 03224 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03225 * whether or not a timer instance supports external clock mode2. 03226 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock 03227 * @param TIMx Timer instance 03228 * @retval State of bit (1 or 0). 03229 */ 03230 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) 03231 { 03232 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); 03233 } 03234 03235 /** 03236 * @brief Set the clock source of the counter clock. 03237 * @note when selected clock source is external clock mode 1, the timer input 03238 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() 03239 * function. This timer input must be configured by calling 03240 * the @ref LL_TIM_IC_Config() function. 03241 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check 03242 * whether or not a timer instance supports external clock mode1. 03243 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03244 * whether or not a timer instance supports external clock mode2. 03245 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n 03246 * SMCR ECE LL_TIM_SetClockSource 03247 * @param TIMx Timer instance 03248 * @param ClockSource This parameter can be one of the following values: 03249 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL 03250 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 03251 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 03252 * @retval None 03253 */ 03254 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) 03255 { 03256 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 03257 } 03258 03259 /** 03260 * @brief Set the encoder interface mode. 03261 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check 03262 * whether or not a timer instance supports the encoder mode. 03263 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode 03264 * @param TIMx Timer instance 03265 * @param EncoderMode This parameter can be one of the following values: 03266 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 03267 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 03268 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 03269 * @retval None 03270 */ 03271 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) 03272 { 03273 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); 03274 } 03275 03276 /** 03277 * @} 03278 */ 03279 03280 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration 03281 * @{ 03282 */ 03283 /** 03284 * @brief Set the trigger output (TRGO) used for timer synchronization . 03285 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check 03286 * whether or not a timer instance can operate as a master timer. 03287 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput 03288 * @param TIMx Timer instance 03289 * @param TimerSynchronization This parameter can be one of the following values: 03290 * @arg @ref LL_TIM_TRGO_RESET 03291 * @arg @ref LL_TIM_TRGO_ENABLE 03292 * @arg @ref LL_TIM_TRGO_UPDATE 03293 * @arg @ref LL_TIM_TRGO_CC1IF 03294 * @arg @ref LL_TIM_TRGO_OC1REF 03295 * @arg @ref LL_TIM_TRGO_OC2REF 03296 * @arg @ref LL_TIM_TRGO_OC3REF 03297 * @arg @ref LL_TIM_TRGO_OC4REF 03298 * @retval None 03299 */ 03300 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) 03301 { 03302 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 03303 } 03304 03305 /** 03306 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . 03307 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check 03308 * whether or not a timer instance can be used for ADC synchronization. 03309 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 03310 * @param TIMx Timer Instance 03311 * @param ADCSynchronization This parameter can be one of the following values: 03312 * @arg @ref LL_TIM_TRGO2_RESET 03313 * @arg @ref LL_TIM_TRGO2_ENABLE 03314 * @arg @ref LL_TIM_TRGO2_UPDATE 03315 * @arg @ref LL_TIM_TRGO2_CC1F 03316 * @arg @ref LL_TIM_TRGO2_OC1 03317 * @arg @ref LL_TIM_TRGO2_OC2 03318 * @arg @ref LL_TIM_TRGO2_OC3 03319 * @arg @ref LL_TIM_TRGO2_OC4 03320 * @arg @ref LL_TIM_TRGO2_OC5 03321 * @arg @ref LL_TIM_TRGO2_OC6 03322 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING 03323 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING 03324 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING 03325 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING 03326 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING 03327 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING 03328 * @retval None 03329 */ 03330 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) 03331 { 03332 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); 03333 } 03334 03335 /** 03336 * @brief Set the synchronization mode of a slave timer. 03337 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03338 * a timer instance can operate as a slave timer. 03339 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode 03340 * @param TIMx Timer instance 03341 * @param SlaveMode This parameter can be one of the following values: 03342 * @arg @ref LL_TIM_SLAVEMODE_DISABLED 03343 * @arg @ref LL_TIM_SLAVEMODE_RESET 03344 * @arg @ref LL_TIM_SLAVEMODE_GATED 03345 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER 03346 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER 03347 * @retval None 03348 */ 03349 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) 03350 { 03351 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); 03352 } 03353 03354 /** 03355 * @brief Set the selects the trigger input to be used to synchronize the counter. 03356 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03357 * a timer instance can operate as a slave timer. 03358 * @rmtoll SMCR TS LL_TIM_SetTriggerInput 03359 * @param TIMx Timer instance 03360 * @param TriggerInput This parameter can be one of the following values: 03361 * @arg @ref LL_TIM_TS_ITR0 03362 * @arg @ref LL_TIM_TS_ITR1 03363 * @arg @ref LL_TIM_TS_ITR2 03364 * @arg @ref LL_TIM_TS_ITR3 03365 * @arg @ref LL_TIM_TS_TI1F_ED 03366 * @arg @ref LL_TIM_TS_TI1FP1 03367 * @arg @ref LL_TIM_TS_TI2FP2 03368 * @arg @ref LL_TIM_TS_ETRF 03369 * @retval None 03370 */ 03371 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) 03372 { 03373 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); 03374 } 03375 03376 /** 03377 * @brief Enable the Master/Slave mode. 03378 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03379 * a timer instance can operate as a slave timer. 03380 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode 03381 * @param TIMx Timer instance 03382 * @retval None 03383 */ 03384 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) 03385 { 03386 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); 03387 } 03388 03389 /** 03390 * @brief Disable the Master/Slave mode. 03391 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03392 * a timer instance can operate as a slave timer. 03393 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode 03394 * @param TIMx Timer instance 03395 * @retval None 03396 */ 03397 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) 03398 { 03399 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 03400 } 03401 03402 /** 03403 * @brief Indicates whether the Master/Slave mode is enabled. 03404 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03405 * a timer instance can operate as a slave timer. 03406 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode 03407 * @param TIMx Timer instance 03408 * @retval State of bit (1 or 0). 03409 */ 03410 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) 03411 { 03412 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); 03413 } 03414 03415 /** 03416 * @brief Configure the external trigger (ETR) input. 03417 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not 03418 * a timer instance provides an external trigger input. 03419 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n 03420 * SMCR ETPS LL_TIM_ConfigETR\n 03421 * SMCR ETF LL_TIM_ConfigETR 03422 * @param TIMx Timer instance 03423 * @param ETRPolarity This parameter can be one of the following values: 03424 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED 03425 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED 03426 * @param ETRPrescaler This parameter can be one of the following values: 03427 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 03428 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 03429 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 03430 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 03431 * @param ETRFilter This parameter can be one of the following values: 03432 * @arg @ref LL_TIM_ETR_FILTER_FDIV1 03433 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 03434 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 03435 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 03436 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 03437 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 03438 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 03439 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 03440 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 03441 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 03442 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 03443 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 03444 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 03445 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 03446 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 03447 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 03448 * @retval None 03449 */ 03450 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, 03451 uint32_t ETRFilter) 03452 { 03453 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); 03454 } 03455 03456 /** 03457 * @brief Select the external trigger (ETR) input source. 03458 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or 03459 * not a timer instance supports ETR source selection. 03460 * @rmtoll OR2 ETRSEL LL_TIM_SetETRSource 03461 * @param TIMx Timer instance 03462 * @param ETRSource This parameter can be one of the following values: 03463 * @arg @ref LL_TIM_ETRSOURCE_LEGACY 03464 * @arg @ref LL_TIM_ETRSOURCE_COMP1 03465 * @arg @ref LL_TIM_ETRSOURCE_COMP2 03466 * @retval None 03467 */ 03468 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) 03469 { 03470 MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource); 03471 } 03472 03473 /** 03474 * @} 03475 */ 03476 03477 /** @defgroup TIM_LL_EF_Break_Function Break function configuration 03478 * @{ 03479 */ 03480 /** 03481 * @brief Enable the break function. 03482 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03483 * a timer instance provides a break input. 03484 * @rmtoll BDTR BKE LL_TIM_EnableBRK 03485 * @param TIMx Timer instance 03486 * @retval None 03487 */ 03488 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) 03489 { 03490 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); 03491 } 03492 03493 /** 03494 * @brief Disable the break function. 03495 * @rmtoll BDTR BKE LL_TIM_DisableBRK 03496 * @param TIMx Timer instance 03497 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03498 * a timer instance provides a break input. 03499 * @retval None 03500 */ 03501 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) 03502 { 03503 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); 03504 } 03505 03506 /** 03507 * @brief Configure the break input. 03508 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03509 * a timer instance provides a break input. 03510 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n 03511 * BDTR BKF LL_TIM_ConfigBRK 03512 * @param TIMx Timer instance 03513 * @param BreakPolarity This parameter can be one of the following values: 03514 * @arg @ref LL_TIM_BREAK_POLARITY_LOW 03515 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH 03516 * @param BreakFilter This parameter can be one of the following values: 03517 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 03518 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 03519 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 03520 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 03521 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 03522 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 03523 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 03524 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 03525 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 03526 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 03527 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 03528 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 03529 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 03530 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 03531 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 03532 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 03533 * @retval None 03534 */ 03535 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, 03536 uint32_t BreakFilter) 03537 { 03538 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); 03539 } 03540 03541 /** 03542 * @brief Enable the break 2 function. 03543 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03544 * a timer instance provides a second break input. 03545 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 03546 * @param TIMx Timer instance 03547 * @retval None 03548 */ 03549 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) 03550 { 03551 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 03552 } 03553 03554 /** 03555 * @brief Disable the break 2 function. 03556 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03557 * a timer instance provides a second break input. 03558 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 03559 * @param TIMx Timer instance 03560 * @retval None 03561 */ 03562 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) 03563 { 03564 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 03565 } 03566 03567 /** 03568 * @brief Configure the break 2 input. 03569 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03570 * a timer instance provides a second break input. 03571 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n 03572 * BDTR BK2F LL_TIM_ConfigBRK2 03573 * @param TIMx Timer instance 03574 * @param Break2Polarity This parameter can be one of the following values: 03575 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW 03576 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH 03577 * @param Break2Filter This parameter can be one of the following values: 03578 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 03579 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 03580 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 03581 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 03582 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 03583 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 03584 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 03585 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 03586 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 03587 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 03588 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 03589 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 03590 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 03591 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 03592 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 03593 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 03594 * @retval None 03595 */ 03596 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) 03597 { 03598 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); 03599 } 03600 03601 /** 03602 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. 03603 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03604 * a timer instance provides a break input. 03605 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n 03606 * BDTR OSSR LL_TIM_SetOffStates 03607 * @param TIMx Timer instance 03608 * @param OffStateIdle This parameter can be one of the following values: 03609 * @arg @ref LL_TIM_OSSI_DISABLE 03610 * @arg @ref LL_TIM_OSSI_ENABLE 03611 * @param OffStateRun This parameter can be one of the following values: 03612 * @arg @ref LL_TIM_OSSR_DISABLE 03613 * @arg @ref LL_TIM_OSSR_ENABLE 03614 * @retval None 03615 */ 03616 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) 03617 { 03618 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); 03619 } 03620 03621 /** 03622 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). 03623 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03624 * a timer instance provides a break input. 03625 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput 03626 * @param TIMx Timer instance 03627 * @retval None 03628 */ 03629 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) 03630 { 03631 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); 03632 } 03633 03634 /** 03635 * @brief Disable automatic output (MOE can be set only by software). 03636 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03637 * a timer instance provides a break input. 03638 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput 03639 * @param TIMx Timer instance 03640 * @retval None 03641 */ 03642 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) 03643 { 03644 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); 03645 } 03646 03647 /** 03648 * @brief Indicate whether automatic output is enabled. 03649 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03650 * a timer instance provides a break input. 03651 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput 03652 * @param TIMx Timer instance 03653 * @retval State of bit (1 or 0). 03654 */ 03655 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) 03656 { 03657 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); 03658 } 03659 03660 /** 03661 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). 03662 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 03663 * software and is reset in case of break or break2 event 03664 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03665 * a timer instance provides a break input. 03666 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs 03667 * @param TIMx Timer instance 03668 * @retval None 03669 */ 03670 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) 03671 { 03672 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); 03673 } 03674 03675 /** 03676 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). 03677 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 03678 * software and is reset in case of break or break2 event. 03679 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03680 * a timer instance provides a break input. 03681 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs 03682 * @param TIMx Timer instance 03683 * @retval None 03684 */ 03685 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) 03686 { 03687 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); 03688 } 03689 03690 /** 03691 * @brief Indicates whether outputs are enabled. 03692 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03693 * a timer instance provides a break input. 03694 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs 03695 * @param TIMx Timer instance 03696 * @retval State of bit (1 or 0). 03697 */ 03698 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) 03699 { 03700 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); 03701 } 03702 03703 /** 03704 * @brief Enable the signals connected to the designated timer break input. 03705 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 03706 * or not a timer instance allows for break input selection. 03707 * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n 03708 * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n 03709 * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n 03710 * OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n 03711 * OR3 BK2INE LL_TIM_EnableBreakInputSource\n 03712 * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n 03713 * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n 03714 * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource 03715 * @param TIMx Timer instance 03716 * @param BreakInput This parameter can be one of the following values: 03717 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 03718 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 03719 * @param Source This parameter can be one of the following values: 03720 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 03721 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 03722 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 03723 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 03724 * @retval None 03725 */ 03726 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) 03727 { 03728 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); 03729 SET_BIT(*pReg, Source); 03730 } 03731 03732 /** 03733 * @brief Disable the signals connected to the designated timer break input. 03734 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 03735 * or not a timer instance allows for break input selection. 03736 * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n 03737 * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n 03738 * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n 03739 * OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n 03740 * OR3 BK2INE LL_TIM_DisableBreakInputSource\n 03741 * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n 03742 * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n 03743 * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource 03744 * @param TIMx Timer instance 03745 * @param BreakInput This parameter can be one of the following values: 03746 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 03747 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 03748 * @param Source This parameter can be one of the following values: 03749 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 03750 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 03751 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 03752 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 03753 * @retval None 03754 */ 03755 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) 03756 { 03757 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); 03758 CLEAR_BIT(*pReg, Source); 03759 } 03760 03761 /** 03762 * @brief Set the polarity of the break signal for the timer break input. 03763 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 03764 * or not a timer instance allows for break input selection. 03765 * @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n 03766 * OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n 03767 * OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n 03768 * OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n 03769 * OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n 03770 * OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity 03771 * @param TIMx Timer instance 03772 * @param BreakInput This parameter can be one of the following values: 03773 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 03774 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 03775 * @param Source This parameter can be one of the following values: 03776 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 03777 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 03778 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 03779 * @param Polarity This parameter can be one of the following values: 03780 * @arg @ref LL_TIM_BKIN_POLARITY_LOW 03781 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH 03782 * @retval None 03783 */ 03784 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, 03785 uint32_t Polarity) 03786 { 03787 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); 03788 MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); 03789 } 03790 /** 03791 * @} 03792 */ 03793 03794 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration 03795 * @{ 03796 */ 03797 /** 03798 * @brief Configures the timer DMA burst feature. 03799 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or 03800 * not a timer instance supports the DMA burst mode. 03801 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n 03802 * DCR DBA LL_TIM_ConfigDMABurst 03803 * @param TIMx Timer instance 03804 * @param DMABurstBaseAddress This parameter can be one of the following values: 03805 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 03806 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 03807 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR 03808 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER 03809 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR 03810 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR 03811 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 03812 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 03813 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER 03814 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT 03815 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC 03816 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR 03817 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR 03818 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 03819 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 03820 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 03821 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 03822 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR 03823 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1 03824 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 03825 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 03826 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 03827 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2 03828 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3 03829 * @param DMABurstLength This parameter can be one of the following values: 03830 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER 03831 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS 03832 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS 03833 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS 03834 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS 03835 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS 03836 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS 03837 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS 03838 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS 03839 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS 03840 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS 03841 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS 03842 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS 03843 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS 03844 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS 03845 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS 03846 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS 03847 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS 03848 * @retval None 03849 */ 03850 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) 03851 { 03852 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); 03853 } 03854 03855 /** 03856 * @} 03857 */ 03858 03859 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping 03860 * @{ 03861 */ 03862 /** 03863 * @brief Remap TIM inputs (input channel, internal/external triggers). 03864 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not 03865 * a some timer inputs can be remapped. 03866 @if STM32L486xx 03867 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n 03868 * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n 03869 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n 03870 * TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n 03871 * TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n 03872 * TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n 03873 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n 03874 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n 03875 * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n 03876 * TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n 03877 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n 03878 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n 03879 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n 03880 * TIM17_OR1 TI1_RMP LL_TIM_SetRemap 03881 @endif 03882 @if STM32L443xx 03883 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n 03884 * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n 03885 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n 03886 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n 03887 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n 03888 * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n 03889 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n 03890 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n 03891 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n 03892 @endif 03893 * @param TIMx Timer instance 03894 * @param Remap Remap param depends on the TIMx. Description available only 03895 * in CHM version of the User Manual (not in .pdf). 03896 * Otherwise see Reference Manual description of OR registers. 03897 * 03898 * Below description summarizes "Timer Instance" and "Remap" param combinations: 03899 * 03900 @if STM32L486xx 03901 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where 03902 * 03903 * . . ADC1_RMP can be one of the following values 03904 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC 03905 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 03906 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 03907 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 03908 * 03909 * . . ADC3_RMP can be one of the following values 03910 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC 03911 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 03912 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 03913 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 03914 * 03915 * . . TI1_RMP can be one of the following values 03916 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO 03917 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 03918 * 03919 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where 03920 * 03921 * ITR1_RMP can be one of the following values 03922 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO 03923 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF 03924 * 03925 * . . ETR1_RMP can be one of the following values 03926 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO 03927 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE 03928 * 03929 * . . TI4_RMP can be one of the following values 03930 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO 03931 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 03932 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 03933 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 03934 * 03935 * TIM3: one of the following values 03936 * 03937 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO 03938 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1 03939 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2 03940 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 03941 * 03942 * TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where 03943 * 03944 * . . ADC1_RMP can be one of the following values 03945 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC 03946 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 03947 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 03948 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 03949 * 03950 * . . ADC3_RMP can be one of the following values 03951 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC 03952 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 03953 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 03954 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 03955 * 03956 * . . TI1_RMP can be one of the following values 03957 * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO 03958 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2 03959 * 03960 * TIM15: any combination of TI1_RMP, ENCODER_MODE where 03961 * 03962 * . . TI1_RMP can be one of the following values 03963 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO 03964 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE 03965 * 03966 * . . ENCODER_MODE can be one of the following values 03967 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION 03968 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2 03969 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3 03970 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4 03971 * 03972 * TIM16: one of the following values 03973 * 03974 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO 03975 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI 03976 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE 03977 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC 03978 * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI 03979 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32 03980 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO 03981 * 03982 * TIM17: one of the following values 03983 * 03984 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO 03985 * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI 03986 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32 03987 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO 03988 @endif 03989 @if STM32L443xx 03990 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where 03991 * 03992 * . . ADC1_RMP can be one of the following values 03993 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC 03994 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 03995 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 03996 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 03997 * 03998 * . . TI1_RMP can be one of the following values 03999 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO 04000 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 04001 * 04002 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where 04003 * 04004 * ITR1_RMP can be one of the following values 04005 * @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE 04006 * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF 04007 * 04008 * . . ETR1_RMP can be one of the following values 04009 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO 04010 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE 04011 * 04012 * . . TI4_RMP can be one of the following values 04013 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO 04014 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 04015 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 04016 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 04017 * 04018 * TIM15: any combination of TI1_RMP, ENCODER_MODE where 04019 * 04020 * . . TI1_RMP can be one of the following values 04021 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO 04022 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE 04023 * 04024 * . . ENCODER_MODE can be one of the following values 04025 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION 04026 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2 04027 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3 04028 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4 04029 * 04030 * TIM16: one of the following values 04031 * 04032 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO 04033 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI 04034 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE 04035 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC 04036 * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI 04037 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32 04038 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO 04039 @endif 04040 * @retval None 04041 */ 04042 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) 04043 { 04044 MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK)); 04045 } 04046 04047 /** 04048 * @} 04049 */ 04050 04051 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management 04052 * @{ 04053 */ 04054 /** 04055 * @brief Set the OCREF clear input source 04056 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT 04057 * @note This function can only be used in Output compare and PWM modes. 04058 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource 04059 * @param TIMx Timer instance 04060 * @param OCRefClearInputSource This parameter can be one of the following values: 04061 * @arg @ref LL_TIM_OCREF_CLR_INT_NC 04062 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR 04063 * @retval None 04064 */ 04065 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) 04066 { 04067 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); 04068 } 04069 /** 04070 * @} 04071 */ 04072 04073 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management 04074 * @{ 04075 */ 04076 /** 04077 * @brief Clear the update interrupt flag (UIF). 04078 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE 04079 * @param TIMx Timer instance 04080 * @retval None 04081 */ 04082 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) 04083 { 04084 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 04085 } 04086 04087 /** 04088 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). 04089 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE 04090 * @param TIMx Timer instance 04091 * @retval State of bit (1 or 0). 04092 */ 04093 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) 04094 { 04095 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); 04096 } 04097 04098 /** 04099 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). 04100 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 04101 * @param TIMx Timer instance 04102 * @retval None 04103 */ 04104 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) 04105 { 04106 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); 04107 } 04108 04109 /** 04110 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). 04111 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 04112 * @param TIMx Timer instance 04113 * @retval State of bit (1 or 0). 04114 */ 04115 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) 04116 { 04117 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); 04118 } 04119 04120 /** 04121 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). 04122 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 04123 * @param TIMx Timer instance 04124 * @retval None 04125 */ 04126 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) 04127 { 04128 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); 04129 } 04130 04131 /** 04132 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). 04133 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 04134 * @param TIMx Timer instance 04135 * @retval State of bit (1 or 0). 04136 */ 04137 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) 04138 { 04139 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); 04140 } 04141 04142 /** 04143 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). 04144 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 04145 * @param TIMx Timer instance 04146 * @retval None 04147 */ 04148 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) 04149 { 04150 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); 04151 } 04152 04153 /** 04154 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). 04155 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 04156 * @param TIMx Timer instance 04157 * @retval State of bit (1 or 0). 04158 */ 04159 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) 04160 { 04161 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); 04162 } 04163 04164 /** 04165 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). 04166 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 04167 * @param TIMx Timer instance 04168 * @retval None 04169 */ 04170 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) 04171 { 04172 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); 04173 } 04174 04175 /** 04176 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). 04177 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 04178 * @param TIMx Timer instance 04179 * @retval State of bit (1 or 0). 04180 */ 04181 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) 04182 { 04183 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); 04184 } 04185 04186 /** 04187 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). 04188 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 04189 * @param TIMx Timer instance 04190 * @retval None 04191 */ 04192 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) 04193 { 04194 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); 04195 } 04196 04197 /** 04198 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). 04199 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 04200 * @param TIMx Timer instance 04201 * @retval State of bit (1 or 0). 04202 */ 04203 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) 04204 { 04205 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); 04206 } 04207 04208 /** 04209 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). 04210 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 04211 * @param TIMx Timer instance 04212 * @retval None 04213 */ 04214 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) 04215 { 04216 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); 04217 } 04218 04219 /** 04220 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). 04221 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 04222 * @param TIMx Timer instance 04223 * @retval State of bit (1 or 0). 04224 */ 04225 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) 04226 { 04227 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); 04228 } 04229 04230 /** 04231 * @brief Clear the commutation interrupt flag (COMIF). 04232 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM 04233 * @param TIMx Timer instance 04234 * @retval None 04235 */ 04236 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) 04237 { 04238 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); 04239 } 04240 04241 /** 04242 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). 04243 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM 04244 * @param TIMx Timer instance 04245 * @retval State of bit (1 or 0). 04246 */ 04247 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) 04248 { 04249 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); 04250 } 04251 04252 /** 04253 * @brief Clear the trigger interrupt flag (TIF). 04254 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG 04255 * @param TIMx Timer instance 04256 * @retval None 04257 */ 04258 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) 04259 { 04260 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); 04261 } 04262 04263 /** 04264 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). 04265 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG 04266 * @param TIMx Timer instance 04267 * @retval State of bit (1 or 0). 04268 */ 04269 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) 04270 { 04271 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); 04272 } 04273 04274 /** 04275 * @brief Clear the break interrupt flag (BIF). 04276 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK 04277 * @param TIMx Timer instance 04278 * @retval None 04279 */ 04280 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) 04281 { 04282 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); 04283 } 04284 04285 /** 04286 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). 04287 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK 04288 * @param TIMx Timer instance 04289 * @retval State of bit (1 or 0). 04290 */ 04291 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) 04292 { 04293 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); 04294 } 04295 04296 /** 04297 * @brief Clear the break 2 interrupt flag (B2IF). 04298 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 04299 * @param TIMx Timer instance 04300 * @retval None 04301 */ 04302 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) 04303 { 04304 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); 04305 } 04306 04307 /** 04308 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). 04309 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 04310 * @param TIMx Timer instance 04311 * @retval State of bit (1 or 0). 04312 */ 04313 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) 04314 { 04315 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); 04316 } 04317 04318 /** 04319 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). 04320 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR 04321 * @param TIMx Timer instance 04322 * @retval None 04323 */ 04324 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) 04325 { 04326 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); 04327 } 04328 04329 /** 04330 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set 04331 * (Capture/Compare 1 interrupt is pending). 04332 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR 04333 * @param TIMx Timer instance 04334 * @retval State of bit (1 or 0). 04335 */ 04336 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) 04337 { 04338 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); 04339 } 04340 04341 /** 04342 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). 04343 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR 04344 * @param TIMx Timer instance 04345 * @retval None 04346 */ 04347 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) 04348 { 04349 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); 04350 } 04351 04352 /** 04353 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set 04354 * (Capture/Compare 2 over-capture interrupt is pending). 04355 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR 04356 * @param TIMx Timer instance 04357 * @retval State of bit (1 or 0). 04358 */ 04359 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) 04360 { 04361 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); 04362 } 04363 04364 /** 04365 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). 04366 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR 04367 * @param TIMx Timer instance 04368 * @retval None 04369 */ 04370 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) 04371 { 04372 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); 04373 } 04374 04375 /** 04376 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set 04377 * (Capture/Compare 3 over-capture interrupt is pending). 04378 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR 04379 * @param TIMx Timer instance 04380 * @retval State of bit (1 or 0). 04381 */ 04382 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) 04383 { 04384 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); 04385 } 04386 04387 /** 04388 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). 04389 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR 04390 * @param TIMx Timer instance 04391 * @retval None 04392 */ 04393 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) 04394 { 04395 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); 04396 } 04397 04398 /** 04399 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set 04400 * (Capture/Compare 4 over-capture interrupt is pending). 04401 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR 04402 * @param TIMx Timer instance 04403 * @retval State of bit (1 or 0). 04404 */ 04405 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) 04406 { 04407 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); 04408 } 04409 04410 /** 04411 * @brief Clear the system break interrupt flag (SBIF). 04412 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK 04413 * @param TIMx Timer instance 04414 * @retval None 04415 */ 04416 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) 04417 { 04418 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); 04419 } 04420 04421 /** 04422 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). 04423 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK 04424 * @param TIMx Timer instance 04425 * @retval State of bit (1 or 0). 04426 */ 04427 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) 04428 { 04429 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); 04430 } 04431 04432 /** 04433 * @} 04434 */ 04435 04436 /** @defgroup TIM_LL_EF_IT_Management IT-Management 04437 * @{ 04438 */ 04439 /** 04440 * @brief Enable update interrupt (UIE). 04441 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE 04442 * @param TIMx Timer instance 04443 * @retval None 04444 */ 04445 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) 04446 { 04447 SET_BIT(TIMx->DIER, TIM_DIER_UIE); 04448 } 04449 04450 /** 04451 * @brief Disable update interrupt (UIE). 04452 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE 04453 * @param TIMx Timer instance 04454 * @retval None 04455 */ 04456 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) 04457 { 04458 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); 04459 } 04460 04461 /** 04462 * @brief Indicates whether the update interrupt (UIE) is enabled. 04463 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE 04464 * @param TIMx Timer instance 04465 * @retval State of bit (1 or 0). 04466 */ 04467 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) 04468 { 04469 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); 04470 } 04471 04472 /** 04473 * @brief Enable capture/compare 1 interrupt (CC1IE). 04474 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 04475 * @param TIMx Timer instance 04476 * @retval None 04477 */ 04478 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) 04479 { 04480 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); 04481 } 04482 04483 /** 04484 * @brief Disable capture/compare 1 interrupt (CC1IE). 04485 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 04486 * @param TIMx Timer instance 04487 * @retval None 04488 */ 04489 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) 04490 { 04491 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); 04492 } 04493 04494 /** 04495 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. 04496 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 04497 * @param TIMx Timer instance 04498 * @retval State of bit (1 or 0). 04499 */ 04500 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) 04501 { 04502 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); 04503 } 04504 04505 /** 04506 * @brief Enable capture/compare 2 interrupt (CC2IE). 04507 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 04508 * @param TIMx Timer instance 04509 * @retval None 04510 */ 04511 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) 04512 { 04513 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); 04514 } 04515 04516 /** 04517 * @brief Disable capture/compare 2 interrupt (CC2IE). 04518 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 04519 * @param TIMx Timer instance 04520 * @retval None 04521 */ 04522 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) 04523 { 04524 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); 04525 } 04526 04527 /** 04528 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. 04529 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 04530 * @param TIMx Timer instance 04531 * @retval State of bit (1 or 0). 04532 */ 04533 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) 04534 { 04535 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); 04536 } 04537 04538 /** 04539 * @brief Enable capture/compare 3 interrupt (CC3IE). 04540 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 04541 * @param TIMx Timer instance 04542 * @retval None 04543 */ 04544 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) 04545 { 04546 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); 04547 } 04548 04549 /** 04550 * @brief Disable capture/compare 3 interrupt (CC3IE). 04551 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 04552 * @param TIMx Timer instance 04553 * @retval None 04554 */ 04555 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) 04556 { 04557 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); 04558 } 04559 04560 /** 04561 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. 04562 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 04563 * @param TIMx Timer instance 04564 * @retval State of bit (1 or 0). 04565 */ 04566 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) 04567 { 04568 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); 04569 } 04570 04571 /** 04572 * @brief Enable capture/compare 4 interrupt (CC4IE). 04573 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 04574 * @param TIMx Timer instance 04575 * @retval None 04576 */ 04577 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) 04578 { 04579 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); 04580 } 04581 04582 /** 04583 * @brief Disable capture/compare 4 interrupt (CC4IE). 04584 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 04585 * @param TIMx Timer instance 04586 * @retval None 04587 */ 04588 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) 04589 { 04590 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); 04591 } 04592 04593 /** 04594 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. 04595 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 04596 * @param TIMx Timer instance 04597 * @retval State of bit (1 or 0). 04598 */ 04599 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) 04600 { 04601 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); 04602 } 04603 04604 /** 04605 * @brief Enable commutation interrupt (COMIE). 04606 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM 04607 * @param TIMx Timer instance 04608 * @retval None 04609 */ 04610 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) 04611 { 04612 SET_BIT(TIMx->DIER, TIM_DIER_COMIE); 04613 } 04614 04615 /** 04616 * @brief Disable commutation interrupt (COMIE). 04617 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM 04618 * @param TIMx Timer instance 04619 * @retval None 04620 */ 04621 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) 04622 { 04623 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); 04624 } 04625 04626 /** 04627 * @brief Indicates whether the commutation interrupt (COMIE) is enabled. 04628 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM 04629 * @param TIMx Timer instance 04630 * @retval State of bit (1 or 0). 04631 */ 04632 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) 04633 { 04634 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); 04635 } 04636 04637 /** 04638 * @brief Enable trigger interrupt (TIE). 04639 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG 04640 * @param TIMx Timer instance 04641 * @retval None 04642 */ 04643 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) 04644 { 04645 SET_BIT(TIMx->DIER, TIM_DIER_TIE); 04646 } 04647 04648 /** 04649 * @brief Disable trigger interrupt (TIE). 04650 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG 04651 * @param TIMx Timer instance 04652 * @retval None 04653 */ 04654 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) 04655 { 04656 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); 04657 } 04658 04659 /** 04660 * @brief Indicates whether the trigger interrupt (TIE) is enabled. 04661 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG 04662 * @param TIMx Timer instance 04663 * @retval State of bit (1 or 0). 04664 */ 04665 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) 04666 { 04667 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); 04668 } 04669 04670 /** 04671 * @brief Enable break interrupt (BIE). 04672 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK 04673 * @param TIMx Timer instance 04674 * @retval None 04675 */ 04676 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) 04677 { 04678 SET_BIT(TIMx->DIER, TIM_DIER_BIE); 04679 } 04680 04681 /** 04682 * @brief Disable break interrupt (BIE). 04683 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK 04684 * @param TIMx Timer instance 04685 * @retval None 04686 */ 04687 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) 04688 { 04689 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); 04690 } 04691 04692 /** 04693 * @brief Indicates whether the break interrupt (BIE) is enabled. 04694 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK 04695 * @param TIMx Timer instance 04696 * @retval State of bit (1 or 0). 04697 */ 04698 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) 04699 { 04700 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); 04701 } 04702 04703 /** 04704 * @} 04705 */ 04706 04707 /** @defgroup TIM_LL_EF_DMA_Management DMA Management 04708 * @{ 04709 */ 04710 /** 04711 * @brief Enable update DMA request (UDE). 04712 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE 04713 * @param TIMx Timer instance 04714 * @retval None 04715 */ 04716 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) 04717 { 04718 SET_BIT(TIMx->DIER, TIM_DIER_UDE); 04719 } 04720 04721 /** 04722 * @brief Disable update DMA request (UDE). 04723 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE 04724 * @param TIMx Timer instance 04725 * @retval None 04726 */ 04727 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) 04728 { 04729 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); 04730 } 04731 04732 /** 04733 * @brief Indicates whether the update DMA request (UDE) is enabled. 04734 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE 04735 * @param TIMx Timer instance 04736 * @retval State of bit (1 or 0). 04737 */ 04738 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) 04739 { 04740 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); 04741 } 04742 04743 /** 04744 * @brief Enable capture/compare 1 DMA request (CC1DE). 04745 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 04746 * @param TIMx Timer instance 04747 * @retval None 04748 */ 04749 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) 04750 { 04751 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); 04752 } 04753 04754 /** 04755 * @brief Disable capture/compare 1 DMA request (CC1DE). 04756 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 04757 * @param TIMx Timer instance 04758 * @retval None 04759 */ 04760 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) 04761 { 04762 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); 04763 } 04764 04765 /** 04766 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. 04767 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 04768 * @param TIMx Timer instance 04769 * @retval State of bit (1 or 0). 04770 */ 04771 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) 04772 { 04773 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); 04774 } 04775 04776 /** 04777 * @brief Enable capture/compare 2 DMA request (CC2DE). 04778 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 04779 * @param TIMx Timer instance 04780 * @retval None 04781 */ 04782 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) 04783 { 04784 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); 04785 } 04786 04787 /** 04788 * @brief Disable capture/compare 2 DMA request (CC2DE). 04789 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 04790 * @param TIMx Timer instance 04791 * @retval None 04792 */ 04793 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) 04794 { 04795 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); 04796 } 04797 04798 /** 04799 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. 04800 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 04801 * @param TIMx Timer instance 04802 * @retval State of bit (1 or 0). 04803 */ 04804 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) 04805 { 04806 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); 04807 } 04808 04809 /** 04810 * @brief Enable capture/compare 3 DMA request (CC3DE). 04811 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 04812 * @param TIMx Timer instance 04813 * @retval None 04814 */ 04815 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) 04816 { 04817 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); 04818 } 04819 04820 /** 04821 * @brief Disable capture/compare 3 DMA request (CC3DE). 04822 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 04823 * @param TIMx Timer instance 04824 * @retval None 04825 */ 04826 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) 04827 { 04828 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); 04829 } 04830 04831 /** 04832 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. 04833 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 04834 * @param TIMx Timer instance 04835 * @retval State of bit (1 or 0). 04836 */ 04837 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) 04838 { 04839 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); 04840 } 04841 04842 /** 04843 * @brief Enable capture/compare 4 DMA request (CC4DE). 04844 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 04845 * @param TIMx Timer instance 04846 * @retval None 04847 */ 04848 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) 04849 { 04850 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); 04851 } 04852 04853 /** 04854 * @brief Disable capture/compare 4 DMA request (CC4DE). 04855 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 04856 * @param TIMx Timer instance 04857 * @retval None 04858 */ 04859 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) 04860 { 04861 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); 04862 } 04863 04864 /** 04865 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. 04866 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 04867 * @param TIMx Timer instance 04868 * @retval State of bit (1 or 0). 04869 */ 04870 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) 04871 { 04872 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); 04873 } 04874 04875 /** 04876 * @brief Enable commutation DMA request (COMDE). 04877 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM 04878 * @param TIMx Timer instance 04879 * @retval None 04880 */ 04881 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) 04882 { 04883 SET_BIT(TIMx->DIER, TIM_DIER_COMDE); 04884 } 04885 04886 /** 04887 * @brief Disable commutation DMA request (COMDE). 04888 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM 04889 * @param TIMx Timer instance 04890 * @retval None 04891 */ 04892 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) 04893 { 04894 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); 04895 } 04896 04897 /** 04898 * @brief Indicates whether the commutation DMA request (COMDE) is enabled. 04899 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM 04900 * @param TIMx Timer instance 04901 * @retval State of bit (1 or 0). 04902 */ 04903 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) 04904 { 04905 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); 04906 } 04907 04908 /** 04909 * @brief Enable trigger interrupt (TDE). 04910 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG 04911 * @param TIMx Timer instance 04912 * @retval None 04913 */ 04914 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) 04915 { 04916 SET_BIT(TIMx->DIER, TIM_DIER_TDE); 04917 } 04918 04919 /** 04920 * @brief Disable trigger interrupt (TDE). 04921 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG 04922 * @param TIMx Timer instance 04923 * @retval None 04924 */ 04925 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) 04926 { 04927 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); 04928 } 04929 04930 /** 04931 * @brief Indicates whether the trigger interrupt (TDE) is enabled. 04932 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG 04933 * @param TIMx Timer instance 04934 * @retval State of bit (1 or 0). 04935 */ 04936 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) 04937 { 04938 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); 04939 } 04940 04941 /** 04942 * @} 04943 */ 04944 04945 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management 04946 * @{ 04947 */ 04948 /** 04949 * @brief Generate an update event. 04950 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE 04951 * @param TIMx Timer instance 04952 * @retval None 04953 */ 04954 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) 04955 { 04956 SET_BIT(TIMx->EGR, TIM_EGR_UG); 04957 } 04958 04959 /** 04960 * @brief Generate Capture/Compare 1 event. 04961 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 04962 * @param TIMx Timer instance 04963 * @retval None 04964 */ 04965 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) 04966 { 04967 SET_BIT(TIMx->EGR, TIM_EGR_CC1G); 04968 } 04969 04970 /** 04971 * @brief Generate Capture/Compare 2 event. 04972 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 04973 * @param TIMx Timer instance 04974 * @retval None 04975 */ 04976 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) 04977 { 04978 SET_BIT(TIMx->EGR, TIM_EGR_CC2G); 04979 } 04980 04981 /** 04982 * @brief Generate Capture/Compare 3 event. 04983 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 04984 * @param TIMx Timer instance 04985 * @retval None 04986 */ 04987 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) 04988 { 04989 SET_BIT(TIMx->EGR, TIM_EGR_CC3G); 04990 } 04991 04992 /** 04993 * @brief Generate Capture/Compare 4 event. 04994 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 04995 * @param TIMx Timer instance 04996 * @retval None 04997 */ 04998 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) 04999 { 05000 SET_BIT(TIMx->EGR, TIM_EGR_CC4G); 05001 } 05002 05003 /** 05004 * @brief Generate commutation event. 05005 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM 05006 * @param TIMx Timer instance 05007 * @retval None 05008 */ 05009 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) 05010 { 05011 SET_BIT(TIMx->EGR, TIM_EGR_COMG); 05012 } 05013 05014 /** 05015 * @brief Generate trigger event. 05016 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG 05017 * @param TIMx Timer instance 05018 * @retval None 05019 */ 05020 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) 05021 { 05022 SET_BIT(TIMx->EGR, TIM_EGR_TG); 05023 } 05024 05025 /** 05026 * @brief Generate break event. 05027 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK 05028 * @param TIMx Timer instance 05029 * @retval None 05030 */ 05031 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) 05032 { 05033 SET_BIT(TIMx->EGR, TIM_EGR_BG); 05034 } 05035 05036 /** 05037 * @brief Generate break 2 event. 05038 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 05039 * @param TIMx Timer instance 05040 * @retval None 05041 */ 05042 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) 05043 { 05044 SET_BIT(TIMx->EGR, TIM_EGR_B2G); 05045 } 05046 05047 /** 05048 * @} 05049 */ 05050 05051 #if defined(USE_FULL_LL_DRIVER) 05052 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions 05053 * @{ 05054 */ 05055 05056 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); 05057 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); 05058 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); 05059 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); 05060 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); 05061 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 05062 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); 05063 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); 05064 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); 05065 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); 05066 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); 05067 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); 05068 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); 05069 /** 05070 * @} 05071 */ 05072 #endif /* USE_FULL_LL_DRIVER */ 05073 05074 /** 05075 * @} 05076 */ 05077 05078 /** 05079 * @} 05080 */ 05081 05082 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */ 05083 05084 /** 05085 * @} 05086 */ 05087 05088 #ifdef __cplusplus 05089 } 05090 #endif 05091 05092 #endif /* __STM32L4xx_LL_TIM_H */
1.7.6.1