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STM32F103xB HAL User Manual
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Freeze/Unfreeze Peripherals in Debug mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode). More...
Defines | |
| #define | __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) |
| TIM2 Peripherals Debug mode. | |
| #define | __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) |
| #define | __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) |
| TIM3 Peripherals Debug mode. | |
| #define | __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) |
| #define | __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) |
| TIM4 Peripherals Debug mode. | |
| #define | __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) |
| #define | __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) |
| WWDG Peripherals Debug mode. | |
| #define | __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) |
| #define | __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) |
| IWDG Peripherals Debug mode. | |
| #define | __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) |
| #define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) |
| I2C1 Peripherals Debug mode. | |
| #define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) |
| #define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
| I2C2 Peripherals Debug mode. | |
| #define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
| #define | __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) |
| CAN1 Peripherals Debug mode. | |
| #define | __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) |
| #define | __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) |
| TIM1 Peripherals Debug mode. | |
| #define | __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) |
Freeze/Unfreeze Peripherals in Debug mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
Refer to errata sheet of these devices for more details.
| #define __HAL_DBGMCU_FREEZE_CAN1 | ( | ) | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) |
CAN1 Peripherals Debug mode.
Definition at line 183 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT | ( | ) | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) |
I2C1 Peripherals Debug mode.
Definition at line 168 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT | ( | ) | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
I2C2 Peripherals Debug mode.
Definition at line 175 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_FREEZE_IWDG | ( | ) | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) |
IWDG Peripherals Debug mode.
Definition at line 162 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_FREEZE_TIM1 | ( | ) | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) |
TIM1 Peripherals Debug mode.
Definition at line 200 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_FREEZE_TIM2 | ( | ) | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) |
TIM2 Peripherals Debug mode.
Definition at line 88 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_FREEZE_TIM3 | ( | ) | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) |
TIM3 Peripherals Debug mode.
Definition at line 94 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_FREEZE_TIM4 | ( | ) | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) |
TIM4 Peripherals Debug mode.
Definition at line 101 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_FREEZE_WWDG | ( | ) | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) |
WWDG Peripherals Debug mode.
Definition at line 156 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_UNFREEZE_CAN1 | ( | ) | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) |
Definition at line 184 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT | ( | ) | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) |
Definition at line 169 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT | ( | ) | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
Definition at line 176 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_UNFREEZE_IWDG | ( | ) | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) |
Definition at line 163 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_UNFREEZE_TIM1 | ( | ) | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) |
Definition at line 201 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_UNFREEZE_TIM2 | ( | ) | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) |
Definition at line 89 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_UNFREEZE_TIM3 | ( | ) | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) |
Definition at line 95 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_UNFREEZE_TIM4 | ( | ) | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) |
Definition at line 102 of file stm32f1xx_hal.h.
| #define __HAL_DBGMCU_UNFREEZE_WWDG | ( | ) | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) |
Definition at line 157 of file stm32f1xx_hal.h.
1.7.6.1