PLL SOURCE

Defines
#define	LL_RCC_PLLSOURCE_HSI_DIV_2   0x00000000U
#define	LL_RCC_PLLSOURCE_HSE   RCC_CFGR_PLLSRC
#define	LL_RCC_PLLSOURCE_HSE_DIV_1   (RCC_CFGR_PLLSRC | 0x00000000U)
#define	LL_RCC_PLLSOURCE_HSE_DIV_2   (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)

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Define Documentation

#define LL_RCC_PLLSOURCE_HSE   RCC_CFGR_PLLSRC

HSE/PREDIV1 clock selected as PLL entry clock source

Definition at line 404 of file stm32f1xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and RCC_PLL_GetFreqDomain_SYS().

#define LL_RCC_PLLSOURCE_HSE_DIV_1   (RCC_CFGR_PLLSRC | 0x00000000U)

HSE/1 clock selected as PLL entry clock source

Definition at line 445 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_2   (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)

HSE/2 clock selected as PLL entry clock source

Definition at line 446 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSI_DIV_2   0x00000000U

HSI clock divided by 2 selected as PLL entry clock source

Definition at line 403 of file stm32f1xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), RCC_PLL_GetFreqDomain_SYS(), and UTILS_EnablePLLAndSwitchSystem().