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STM32F103xB HAL User Manual
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Defines | |
| #define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U |
| #define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 |
| #define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 |
| #define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 |
| #define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) |
| #define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 |
| #define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) |
| #define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) |
| #define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) |
| #define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 |
| #define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) |
| #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) |
Transfer is done to 10 registers starting from the DMA burst base address
Definition at line 903 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) |
Transfer is done to 11 registers starting from the DMA burst base address
Definition at line 904 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) |
Transfer is done to 12 registers starting from the DMA burst base address
Definition at line 905 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) |
Transfer is done to 13 registers starting from the DMA burst base address
Definition at line 906 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) |
Transfer is done to 14 registers starting from the DMA burst base address
Definition at line 907 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) |
Transfer is done to 15 registers starting from the DMA burst base address
Definition at line 908 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) |
Transfer is done to 16 registers starting from the DMA burst base address
Definition at line 909 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 |
Transfer is done to 17 registers starting from the DMA burst base address
Definition at line 910 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) |
Transfer is done to 18 registers starting from the DMA burst base address
Definition at line 911 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U |
Transfer is done to 1 register starting from the DMA burst base address
Definition at line 894 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 |
Transfer is done to 2 registers starting from the DMA burst base address
Definition at line 895 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 |
Transfer is done to 3 registers starting from the DMA burst base address
Definition at line 896 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) |
Transfer is done to 4 registers starting from the DMA burst base address
Definition at line 897 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 |
Transfer is done to 5 registers starting from the DMA burst base address
Definition at line 898 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) |
Transfer is done to 6 registers starting from the DMA burst base address
Definition at line 899 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) |
Transfer is done to 7 registers starting from the DMA burst base address
Definition at line 900 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) |
Transfer is done to 1 registers starting from the DMA burst base address
Definition at line 901 of file stm32f1xx_ll_tim.h.
| #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 |
Transfer is done to 9 registers starting from the DMA burst base address
Definition at line 902 of file stm32f1xx_ll_tim.h.
1.7.6.1