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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_tim.h 00004 * @author MCD Application Team 00005 * @brief Header file of TIM HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32F1xx_HAL_TIM_H 00022 #define STM32F1xx_HAL_TIM_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f1xx_hal_def.h" 00030 00031 /** @addtogroup STM32F1xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup TIM 00036 * @{ 00037 */ 00038 00039 /* Exported types ------------------------------------------------------------*/ 00040 /** @defgroup TIM_Exported_Types TIM Exported Types 00041 * @{ 00042 */ 00043 00044 /** 00045 * @brief TIM Time base Configuration Structure definition 00046 */ 00047 typedef struct 00048 { 00049 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 00050 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 00051 00052 uint32_t CounterMode; /*!< Specifies the counter mode. 00053 This parameter can be a value of @ref TIM_Counter_Mode */ 00054 00055 uint32_t Period; /*!< Specifies the period value to be loaded into the active 00056 Auto-Reload Register at the next update event. 00057 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 00058 00059 uint32_t ClockDivision; /*!< Specifies the clock division. 00060 This parameter can be a value of @ref TIM_ClockDivision */ 00061 00062 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 00063 reaches zero, an update event is generated and counting restarts 00064 from the RCR value (N). 00065 This means in PWM mode that (N+1) corresponds to: 00066 - the number of PWM periods in edge-aligned mode 00067 - the number of half PWM period in center-aligned mode 00068 GP timers: this parameter must be a number between Min_Data = 0x00 and 00069 Max_Data = 0xFF. 00070 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and 00071 Max_Data = 0xFFFF. */ 00072 00073 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 00074 This parameter can be a value of @ref TIM_AutoReloadPreload */ 00075 } TIM_Base_InitTypeDef; 00076 00077 /** 00078 * @brief TIM Output Compare Configuration Structure definition 00079 */ 00080 typedef struct 00081 { 00082 uint32_t OCMode; /*!< Specifies the TIM mode. 00083 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 00084 00085 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 00086 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 00087 00088 uint32_t OCPolarity; /*!< Specifies the output polarity. 00089 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 00090 00091 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00092 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 00093 @note This parameter is valid only for timer instances supporting break feature. */ 00094 00095 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 00096 This parameter can be a value of @ref TIM_Output_Fast_State 00097 @note This parameter is valid only in PWM1 and PWM2 mode. */ 00098 00099 00100 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00101 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 00102 @note This parameter is valid only for timer instances supporting break feature. */ 00103 00104 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00105 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 00106 @note This parameter is valid only for timer instances supporting break feature. */ 00107 } TIM_OC_InitTypeDef; 00108 00109 /** 00110 * @brief TIM One Pulse Mode Configuration Structure definition 00111 */ 00112 typedef struct 00113 { 00114 uint32_t OCMode; /*!< Specifies the TIM mode. 00115 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 00116 00117 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 00118 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 00119 00120 uint32_t OCPolarity; /*!< Specifies the output polarity. 00121 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 00122 00123 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00124 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 00125 @note This parameter is valid only for timer instances supporting break feature. */ 00126 00127 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00128 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 00129 @note This parameter is valid only for timer instances supporting break feature. */ 00130 00131 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00132 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 00133 @note This parameter is valid only for timer instances supporting break feature. */ 00134 00135 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00136 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00137 00138 uint32_t ICSelection; /*!< Specifies the input. 00139 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00140 00141 uint32_t ICFilter; /*!< Specifies the input capture filter. 00142 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00143 } TIM_OnePulse_InitTypeDef; 00144 00145 /** 00146 * @brief TIM Input Capture Configuration Structure definition 00147 */ 00148 typedef struct 00149 { 00150 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00151 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00152 00153 uint32_t ICSelection; /*!< Specifies the input. 00154 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00155 00156 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 00157 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00158 00159 uint32_t ICFilter; /*!< Specifies the input capture filter. 00160 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00161 } TIM_IC_InitTypeDef; 00162 00163 /** 00164 * @brief TIM Encoder Configuration Structure definition 00165 */ 00166 typedef struct 00167 { 00168 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 00169 This parameter can be a value of @ref TIM_Encoder_Mode */ 00170 00171 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 00172 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 00173 00174 uint32_t IC1Selection; /*!< Specifies the input. 00175 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00176 00177 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 00178 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00179 00180 uint32_t IC1Filter; /*!< Specifies the input capture filter. 00181 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00182 00183 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 00184 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 00185 00186 uint32_t IC2Selection; /*!< Specifies the input. 00187 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00188 00189 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 00190 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00191 00192 uint32_t IC2Filter; /*!< Specifies the input capture filter. 00193 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00194 } TIM_Encoder_InitTypeDef; 00195 00196 /** 00197 * @brief Clock Configuration Handle Structure definition 00198 */ 00199 typedef struct 00200 { 00201 uint32_t ClockSource; /*!< TIM clock sources 00202 This parameter can be a value of @ref TIM_Clock_Source */ 00203 uint32_t ClockPolarity; /*!< TIM clock polarity 00204 This parameter can be a value of @ref TIM_Clock_Polarity */ 00205 uint32_t ClockPrescaler; /*!< TIM clock prescaler 00206 This parameter can be a value of @ref TIM_Clock_Prescaler */ 00207 uint32_t ClockFilter; /*!< TIM clock filter 00208 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00209 } TIM_ClockConfigTypeDef; 00210 00211 /** 00212 * @brief TIM Clear Input Configuration Handle Structure definition 00213 */ 00214 typedef struct 00215 { 00216 uint32_t ClearInputState; /*!< TIM clear Input state 00217 This parameter can be ENABLE or DISABLE */ 00218 uint32_t ClearInputSource; /*!< TIM clear Input sources 00219 This parameter can be a value of @ref TIM_ClearInput_Source */ 00220 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 00221 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 00222 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 00223 This parameter must be 0: When OCRef clear feature is used with ETR source, 00224 ETR prescaler must be off */ 00225 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 00226 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00227 } TIM_ClearInputConfigTypeDef; 00228 00229 /** 00230 * @brief TIM Master configuration Structure definition 00231 */ 00232 typedef struct 00233 { 00234 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 00235 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 00236 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 00237 This parameter can be a value of @ref TIM_Master_Slave_Mode 00238 @note When the Master/slave mode is enabled, the effect of 00239 an event on the trigger input (TRGI) is delayed to allow a 00240 perfect synchronization between the current timer and its 00241 slaves (through TRGO). It is not mandatory in case of timer 00242 synchronization mode. */ 00243 } TIM_MasterConfigTypeDef; 00244 00245 /** 00246 * @brief TIM Slave configuration Structure definition 00247 */ 00248 typedef struct 00249 { 00250 uint32_t SlaveMode; /*!< Slave mode selection 00251 This parameter can be a value of @ref TIM_Slave_Mode */ 00252 uint32_t InputTrigger; /*!< Input Trigger source 00253 This parameter can be a value of @ref TIM_Trigger_Selection */ 00254 uint32_t TriggerPolarity; /*!< Input Trigger polarity 00255 This parameter can be a value of @ref TIM_Trigger_Polarity */ 00256 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 00257 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 00258 uint32_t TriggerFilter; /*!< Input trigger filter 00259 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00260 00261 } TIM_SlaveConfigTypeDef; 00262 00263 /** 00264 * @brief TIM Break input(s) and Dead time configuration Structure definition 00265 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 00266 * filter and polarity. 00267 */ 00268 typedef struct 00269 { 00270 uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 00271 00272 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 00273 00274 uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ 00275 00276 uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 00277 00278 uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 00279 00280 uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ 00281 00282 uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00283 00284 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 00285 00286 } TIM_BreakDeadTimeConfigTypeDef; 00287 00288 /** 00289 * @brief HAL State structures definition 00290 */ 00291 typedef enum 00292 { 00293 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 00294 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00295 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 00296 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 00297 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 00298 } HAL_TIM_StateTypeDef; 00299 00300 /** 00301 * @brief TIM Channel States definition 00302 */ 00303 typedef enum 00304 { 00305 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 00306 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 00307 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 00308 } HAL_TIM_ChannelStateTypeDef; 00309 00310 /** 00311 * @brief DMA Burst States definition 00312 */ 00313 typedef enum 00314 { 00315 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 00316 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 00317 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 00318 } HAL_TIM_DMABurstStateTypeDef; 00319 00320 /** 00321 * @brief HAL Active channel structures definition 00322 */ 00323 typedef enum 00324 { 00325 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 00326 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 00327 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 00328 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 00329 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 00330 } HAL_TIM_ActiveChannel; 00331 00332 /** 00333 * @brief TIM Time Base Handle Structure definition 00334 */ 00335 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00336 typedef struct __TIM_HandleTypeDef 00337 #else 00338 typedef struct 00339 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00340 { 00341 TIM_TypeDef *Instance; /*!< Register base address */ 00342 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 00343 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 00344 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 00345 This array is accessed by a @ref DMA_Handle_index */ 00346 HAL_LockTypeDef Lock; /*!< Locking object */ 00347 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 00348 __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ 00349 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ 00350 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 00351 00352 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00353 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 00354 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 00355 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 00356 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 00357 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 00358 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 00359 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 00360 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 00361 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 00362 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 00363 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 00364 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 00365 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 00366 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 00367 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 00368 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 00369 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 00370 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 00371 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 00372 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 00373 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 00374 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 00375 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 00376 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 00377 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 00378 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 00379 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 00380 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00381 } TIM_HandleTypeDef; 00382 00383 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00384 /** 00385 * @brief HAL TIM Callback ID enumeration definition 00386 */ 00387 typedef enum 00388 { 00389 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 00390 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 00391 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 00392 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 00393 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 00394 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 00395 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 00396 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 00397 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 00398 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 00399 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 00400 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 00401 , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 00402 , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 00403 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 00404 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 00405 , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 00406 , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 00407 00408 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 00409 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 00410 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 00411 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 00412 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 00413 , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 00414 , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 00415 , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 00416 , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 00417 } HAL_TIM_CallbackIDTypeDef; 00418 00419 /** 00420 * @brief HAL TIM Callback pointer definition 00421 */ 00422 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 00423 00424 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00425 00426 /** 00427 * @} 00428 */ 00429 /* End of exported types -----------------------------------------------------*/ 00430 00431 /* Exported constants --------------------------------------------------------*/ 00432 /** @defgroup TIM_Exported_Constants TIM Exported Constants 00433 * @{ 00434 */ 00435 00436 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 00437 * @{ 00438 */ 00439 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 00440 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 00441 /** 00442 * @} 00443 */ 00444 00445 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 00446 * @{ 00447 */ 00448 #define TIM_DMABASE_CR1 0x00000000U 00449 #define TIM_DMABASE_CR2 0x00000001U 00450 #define TIM_DMABASE_SMCR 0x00000002U 00451 #define TIM_DMABASE_DIER 0x00000003U 00452 #define TIM_DMABASE_SR 0x00000004U 00453 #define TIM_DMABASE_EGR 0x00000005U 00454 #define TIM_DMABASE_CCMR1 0x00000006U 00455 #define TIM_DMABASE_CCMR2 0x00000007U 00456 #define TIM_DMABASE_CCER 0x00000008U 00457 #define TIM_DMABASE_CNT 0x00000009U 00458 #define TIM_DMABASE_PSC 0x0000000AU 00459 #define TIM_DMABASE_ARR 0x0000000BU 00460 #define TIM_DMABASE_RCR 0x0000000CU 00461 #define TIM_DMABASE_CCR1 0x0000000DU 00462 #define TIM_DMABASE_CCR2 0x0000000EU 00463 #define TIM_DMABASE_CCR3 0x0000000FU 00464 #define TIM_DMABASE_CCR4 0x00000010U 00465 #define TIM_DMABASE_BDTR 0x00000011U 00466 #define TIM_DMABASE_DCR 0x00000012U 00467 #define TIM_DMABASE_DMAR 0x00000013U 00468 /** 00469 * @} 00470 */ 00471 00472 /** @defgroup TIM_Event_Source TIM Event Source 00473 * @{ 00474 */ 00475 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 00476 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 00477 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 00478 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 00479 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 00480 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 00481 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 00482 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 00483 /** 00484 * @} 00485 */ 00486 00487 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 00488 * @{ 00489 */ 00490 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 00491 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 00492 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 00493 /** 00494 * @} 00495 */ 00496 00497 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 00498 * @{ 00499 */ 00500 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 00501 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 00502 /** 00503 * @} 00504 */ 00505 00506 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 00507 * @{ 00508 */ 00509 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 00510 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 00511 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 00512 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 00513 /** 00514 * @} 00515 */ 00516 00517 /** @defgroup TIM_Counter_Mode TIM Counter Mode 00518 * @{ 00519 */ 00520 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 00521 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 00522 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 00523 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 00524 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 00525 /** 00526 * @} 00527 */ 00528 00529 /** @defgroup TIM_ClockDivision TIM Clock Division 00530 * @{ 00531 */ 00532 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 00533 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 00534 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 00535 /** 00536 * @} 00537 */ 00538 00539 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 00540 * @{ 00541 */ 00542 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 00543 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 00544 /** 00545 * @} 00546 */ 00547 00548 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 00549 * @{ 00550 */ 00551 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 00552 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 00553 00554 /** 00555 * @} 00556 */ 00557 00558 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 00559 * @{ 00560 */ 00561 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 00562 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 00563 /** 00564 * @} 00565 */ 00566 00567 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 00568 * @{ 00569 */ 00570 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 00571 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 00572 /** 00573 * @} 00574 */ 00575 00576 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 00577 * @{ 00578 */ 00579 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 00580 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 00581 /** 00582 * @} 00583 */ 00584 00585 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 00586 * @{ 00587 */ 00588 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 00589 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 00590 /** 00591 * @} 00592 */ 00593 00594 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 00595 * @{ 00596 */ 00597 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 00598 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 00599 /** 00600 * @} 00601 */ 00602 00603 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 00604 * @{ 00605 */ 00606 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 00607 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 00608 /** 00609 * @} 00610 */ 00611 00612 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 00613 * @{ 00614 */ 00615 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 00616 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 00617 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 00618 /** 00619 * @} 00620 */ 00621 00622 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 00623 * @{ 00624 */ 00625 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 00626 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 00627 /** 00628 * @} 00629 */ 00630 00631 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 00632 * @{ 00633 */ 00634 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ 00635 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ 00636 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 00637 /** 00638 * @} 00639 */ 00640 00641 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 00642 * @{ 00643 */ 00644 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 00645 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 00646 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 00647 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 00648 /** 00649 * @} 00650 */ 00651 00652 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 00653 * @{ 00654 */ 00655 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 00656 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 00657 /** 00658 * @} 00659 */ 00660 00661 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 00662 * @{ 00663 */ 00664 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 00665 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 00666 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 00667 /** 00668 * @} 00669 */ 00670 00671 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 00672 * @{ 00673 */ 00674 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 00675 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 00676 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 00677 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 00678 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 00679 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 00680 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 00681 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 00682 /** 00683 * @} 00684 */ 00685 00686 /** @defgroup TIM_Commutation_Source TIM Commutation Source 00687 * @{ 00688 */ 00689 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 00690 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 00691 /** 00692 * @} 00693 */ 00694 00695 /** @defgroup TIM_DMA_sources TIM DMA Sources 00696 * @{ 00697 */ 00698 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 00699 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 00700 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 00701 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 00702 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 00703 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 00704 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 00705 /** 00706 * @} 00707 */ 00708 00709 /** @defgroup TIM_Flag_definition TIM Flag Definition 00710 * @{ 00711 */ 00712 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 00713 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 00714 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 00715 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 00716 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 00717 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 00718 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 00719 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 00720 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 00721 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 00722 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 00723 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 00724 /** 00725 * @} 00726 */ 00727 00728 /** @defgroup TIM_Channel TIM Channel 00729 * @{ 00730 */ 00731 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 00732 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 00733 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 00734 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 00735 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 00736 /** 00737 * @} 00738 */ 00739 00740 /** @defgroup TIM_Clock_Source TIM Clock Source 00741 * @{ 00742 */ 00743 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 00744 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 00745 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 00746 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 00747 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 00748 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 00749 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 00750 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 00751 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 00752 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 00753 /** 00754 * @} 00755 */ 00756 00757 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 00758 * @{ 00759 */ 00760 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 00761 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 00762 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 00763 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 00764 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 00765 /** 00766 * @} 00767 */ 00768 00769 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 00770 * @{ 00771 */ 00772 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00773 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 00774 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 00775 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 00776 /** 00777 * @} 00778 */ 00779 00780 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 00781 * @{ 00782 */ 00783 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 00784 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 00785 /** 00786 * @} 00787 */ 00788 00789 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 00790 * @{ 00791 */ 00792 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00793 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 00794 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 00795 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 00796 /** 00797 * @} 00798 */ 00799 00800 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 00801 * @{ 00802 */ 00803 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 00804 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 00805 /** 00806 * @} 00807 */ 00808 00809 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 00810 * @{ 00811 */ 00812 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 00813 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 00814 /** 00815 * @} 00816 */ 00817 /** @defgroup TIM_Lock_level TIM Lock level 00818 * @{ 00819 */ 00820 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 00821 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 00822 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 00823 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 00824 /** 00825 * @} 00826 */ 00827 00828 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 00829 * @{ 00830 */ 00831 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 00832 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 00833 /** 00834 * @} 00835 */ 00836 00837 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 00838 * @{ 00839 */ 00840 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 00841 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 00842 /** 00843 * @} 00844 */ 00845 00846 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 00847 * @{ 00848 */ 00849 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 00850 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ 00851 /** 00852 * @} 00853 */ 00854 00855 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 00856 * @{ 00857 */ 00858 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 00859 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 00860 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 00861 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 00862 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 00863 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 00864 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 00865 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 00866 /** 00867 * @} 00868 */ 00869 00870 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 00871 * @{ 00872 */ 00873 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 00874 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 00875 /** 00876 * @} 00877 */ 00878 00879 /** @defgroup TIM_Slave_Mode TIM Slave mode 00880 * @{ 00881 */ 00882 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 00883 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 00884 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 00885 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 00886 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 00887 /** 00888 * @} 00889 */ 00890 00891 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 00892 * @{ 00893 */ 00894 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 00895 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 00896 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 00897 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 00898 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 00899 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 00900 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 00901 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 00902 /** 00903 * @} 00904 */ 00905 00906 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 00907 * @{ 00908 */ 00909 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 00910 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 00911 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 00912 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 00913 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 00914 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 00915 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 00916 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 00917 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 00918 /** 00919 * @} 00920 */ 00921 00922 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 00923 * @{ 00924 */ 00925 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 00926 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 00927 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 00928 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 00929 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 00930 /** 00931 * @} 00932 */ 00933 00934 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 00935 * @{ 00936 */ 00937 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00938 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 00939 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 00940 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 00941 /** 00942 * @} 00943 */ 00944 00945 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 00946 * @{ 00947 */ 00948 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 00949 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 00950 /** 00951 * @} 00952 */ 00953 00954 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 00955 * @{ 00956 */ 00957 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ 00958 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00959 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00960 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00961 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00962 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00963 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00964 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00965 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00966 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00967 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00968 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00969 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00970 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00971 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00972 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00973 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00974 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 00975 /** 00976 * @} 00977 */ 00978 00979 /** @defgroup DMA_Handle_index TIM DMA Handle Index 00980 * @{ 00981 */ 00982 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 00983 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 00984 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 00985 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 00986 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 00987 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 00988 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 00989 /** 00990 * @} 00991 */ 00992 00993 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 00994 * @{ 00995 */ 00996 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 00997 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 00998 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 00999 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 01000 /** 01001 * @} 01002 */ 01003 01004 /** 01005 * @} 01006 */ 01007 /* End of exported constants -------------------------------------------------*/ 01008 01009 /* Exported macros -----------------------------------------------------------*/ 01010 /** @defgroup TIM_Exported_Macros TIM Exported Macros 01011 * @{ 01012 */ 01013 01014 /** @brief Reset TIM handle state. 01015 * @param __HANDLE__ TIM handle. 01016 * @retval None 01017 */ 01018 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 01019 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 01020 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 01021 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 01022 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 01023 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 01024 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 01025 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 01026 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 01027 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 01028 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 01029 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 01030 (__HANDLE__)->Base_MspInitCallback = NULL; \ 01031 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 01032 (__HANDLE__)->IC_MspInitCallback = NULL; \ 01033 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 01034 (__HANDLE__)->OC_MspInitCallback = NULL; \ 01035 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 01036 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 01037 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 01038 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 01039 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 01040 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 01041 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 01042 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 01043 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 01044 } while(0) 01045 #else 01046 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 01047 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 01048 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 01049 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 01050 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 01051 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 01052 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 01053 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 01054 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 01055 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 01056 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 01057 } while(0) 01058 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 01059 01060 /** 01061 * @brief Enable the TIM peripheral. 01062 * @param __HANDLE__ TIM handle 01063 * @retval None 01064 */ 01065 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 01066 01067 /** 01068 * @brief Enable the TIM main Output. 01069 * @param __HANDLE__ TIM handle 01070 * @retval None 01071 */ 01072 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 01073 01074 /** 01075 * @brief Disable the TIM peripheral. 01076 * @param __HANDLE__ TIM handle 01077 * @retval None 01078 */ 01079 #define __HAL_TIM_DISABLE(__HANDLE__) \ 01080 do { \ 01081 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 01082 { \ 01083 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 01084 { \ 01085 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 01086 } \ 01087 } \ 01088 } while(0) 01089 01090 /** 01091 * @brief Disable the TIM main Output. 01092 * @param __HANDLE__ TIM handle 01093 * @retval None 01094 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been 01095 * disabled 01096 */ 01097 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 01098 do { \ 01099 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 01100 { \ 01101 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 01102 { \ 01103 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 01104 } \ 01105 } \ 01106 } while(0) 01107 01108 /** 01109 * @brief Disable the TIM main Output. 01110 * @param __HANDLE__ TIM handle 01111 * @retval None 01112 * @note The Main Output Enable of a timer instance is disabled unconditionally 01113 */ 01114 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 01115 01116 /** @brief Enable the specified TIM interrupt. 01117 * @param __HANDLE__ specifies the TIM Handle. 01118 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 01119 * This parameter can be one of the following values: 01120 * @arg TIM_IT_UPDATE: Update interrupt 01121 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01122 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01123 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01124 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01125 * @arg TIM_IT_COM: Commutation interrupt 01126 * @arg TIM_IT_TRIGGER: Trigger interrupt 01127 * @arg TIM_IT_BREAK: Break interrupt 01128 * @retval None 01129 */ 01130 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 01131 01132 /** @brief Disable the specified TIM interrupt. 01133 * @param __HANDLE__ specifies the TIM Handle. 01134 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 01135 * This parameter can be one of the following values: 01136 * @arg TIM_IT_UPDATE: Update interrupt 01137 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01138 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01139 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01140 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01141 * @arg TIM_IT_COM: Commutation interrupt 01142 * @arg TIM_IT_TRIGGER: Trigger interrupt 01143 * @arg TIM_IT_BREAK: Break interrupt 01144 * @retval None 01145 */ 01146 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 01147 01148 /** @brief Enable the specified DMA request. 01149 * @param __HANDLE__ specifies the TIM Handle. 01150 * @param __DMA__ specifies the TIM DMA request to enable. 01151 * This parameter can be one of the following values: 01152 * @arg TIM_DMA_UPDATE: Update DMA request 01153 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 01154 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 01155 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 01156 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 01157 * @arg TIM_DMA_COM: Commutation DMA request 01158 * @arg TIM_DMA_TRIGGER: Trigger DMA request 01159 * @retval None 01160 */ 01161 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 01162 01163 /** @brief Disable the specified DMA request. 01164 * @param __HANDLE__ specifies the TIM Handle. 01165 * @param __DMA__ specifies the TIM DMA request to disable. 01166 * This parameter can be one of the following values: 01167 * @arg TIM_DMA_UPDATE: Update DMA request 01168 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 01169 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 01170 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 01171 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 01172 * @arg TIM_DMA_COM: Commutation DMA request 01173 * @arg TIM_DMA_TRIGGER: Trigger DMA request 01174 * @retval None 01175 */ 01176 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 01177 01178 /** @brief Check whether the specified TIM interrupt flag is set or not. 01179 * @param __HANDLE__ specifies the TIM Handle. 01180 * @param __FLAG__ specifies the TIM interrupt flag to check. 01181 * This parameter can be one of the following values: 01182 * @arg TIM_FLAG_UPDATE: Update interrupt flag 01183 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 01184 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 01185 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 01186 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 01187 * @arg TIM_FLAG_COM: Commutation interrupt flag 01188 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 01189 * @arg TIM_FLAG_BREAK: Break interrupt flag 01190 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 01191 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 01192 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 01193 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 01194 * @retval The new state of __FLAG__ (TRUE or FALSE). 01195 */ 01196 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 01197 01198 /** @brief Clear the specified TIM interrupt flag. 01199 * @param __HANDLE__ specifies the TIM Handle. 01200 * @param __FLAG__ specifies the TIM interrupt flag to clear. 01201 * This parameter can be one of the following values: 01202 * @arg TIM_FLAG_UPDATE: Update interrupt flag 01203 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 01204 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 01205 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 01206 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 01207 * @arg TIM_FLAG_COM: Commutation interrupt flag 01208 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 01209 * @arg TIM_FLAG_BREAK: Break interrupt flag 01210 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 01211 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 01212 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 01213 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 01214 * @retval The new state of __FLAG__ (TRUE or FALSE). 01215 */ 01216 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 01217 01218 /** 01219 * @brief Check whether the specified TIM interrupt source is enabled or not. 01220 * @param __HANDLE__ TIM handle 01221 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 01222 * This parameter can be one of the following values: 01223 * @arg TIM_IT_UPDATE: Update interrupt 01224 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01225 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01226 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01227 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01228 * @arg TIM_IT_COM: Commutation interrupt 01229 * @arg TIM_IT_TRIGGER: Trigger interrupt 01230 * @arg TIM_IT_BREAK: Break interrupt 01231 * @retval The state of TIM_IT (SET or RESET). 01232 */ 01233 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 01234 == (__INTERRUPT__)) ? SET : RESET) 01235 01236 /** @brief Clear the TIM interrupt pending bits. 01237 * @param __HANDLE__ TIM handle 01238 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 01239 * This parameter can be one of the following values: 01240 * @arg TIM_IT_UPDATE: Update interrupt 01241 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01242 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01243 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01244 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01245 * @arg TIM_IT_COM: Commutation interrupt 01246 * @arg TIM_IT_TRIGGER: Trigger interrupt 01247 * @arg TIM_IT_BREAK: Break interrupt 01248 * @retval None 01249 */ 01250 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 01251 01252 /** 01253 * @brief Indicates whether or not the TIM Counter is used as downcounter. 01254 * @param __HANDLE__ TIM handle. 01255 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 01256 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode 01257 * or Encoder mode. 01258 */ 01259 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 01260 01261 /** 01262 * @brief Set the TIM Prescaler on runtime. 01263 * @param __HANDLE__ TIM handle. 01264 * @param __PRESC__ specifies the Prescaler new value. 01265 * @retval None 01266 */ 01267 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 01268 01269 /** 01270 * @brief Set the TIM Counter Register value on runtime. 01271 * @param __HANDLE__ TIM handle. 01272 * @param __COUNTER__ specifies the Counter register new value. 01273 * @retval None 01274 */ 01275 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 01276 01277 /** 01278 * @brief Get the TIM Counter Register value on runtime. 01279 * @param __HANDLE__ TIM handle. 01280 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 01281 */ 01282 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 01283 01284 /** 01285 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 01286 * @param __HANDLE__ TIM handle. 01287 * @param __AUTORELOAD__ specifies the Counter register new value. 01288 * @retval None 01289 */ 01290 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 01291 do{ \ 01292 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 01293 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 01294 } while(0) 01295 01296 /** 01297 * @brief Get the TIM Autoreload Register value on runtime. 01298 * @param __HANDLE__ TIM handle. 01299 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 01300 */ 01301 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 01302 01303 /** 01304 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 01305 * @param __HANDLE__ TIM handle. 01306 * @param __CKD__ specifies the clock division value. 01307 * This parameter can be one of the following value: 01308 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 01309 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 01310 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 01311 * @retval None 01312 */ 01313 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 01314 do{ \ 01315 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 01316 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 01317 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 01318 } while(0) 01319 01320 /** 01321 * @brief Get the TIM Clock Division value on runtime. 01322 * @param __HANDLE__ TIM handle. 01323 * @retval The clock division can be one of the following values: 01324 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 01325 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 01326 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 01327 */ 01328 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 01329 01330 /** 01331 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() 01332 * function. 01333 * @param __HANDLE__ TIM handle. 01334 * @param __CHANNEL__ TIM Channels to be configured. 01335 * This parameter can be one of the following values: 01336 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01337 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01338 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01339 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01340 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 01341 * This parameter can be one of the following values: 01342 * @arg TIM_ICPSC_DIV1: no prescaler 01343 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 01344 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 01345 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 01346 * @retval None 01347 */ 01348 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 01349 do{ \ 01350 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 01351 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 01352 } while(0) 01353 01354 /** 01355 * @brief Get the TIM Input Capture prescaler on runtime. 01356 * @param __HANDLE__ TIM handle. 01357 * @param __CHANNEL__ TIM Channels to be configured. 01358 * This parameter can be one of the following values: 01359 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 01360 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 01361 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 01362 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 01363 * @retval The input capture prescaler can be one of the following values: 01364 * @arg TIM_ICPSC_DIV1: no prescaler 01365 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 01366 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 01367 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 01368 */ 01369 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 01370 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 01371 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 01372 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 01373 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 01374 01375 /** 01376 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 01377 * @param __HANDLE__ TIM handle. 01378 * @param __CHANNEL__ TIM Channels to be configured. 01379 * This parameter can be one of the following values: 01380 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01381 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01382 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01383 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01384 * @param __COMPARE__ specifies the Capture Compare register new value. 01385 * @retval None 01386 */ 01387 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 01388 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 01389 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 01390 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 01391 ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) 01392 01393 /** 01394 * @brief Get the TIM Capture Compare Register value on runtime. 01395 * @param __HANDLE__ TIM handle. 01396 * @param __CHANNEL__ TIM Channel associated with the capture compare register 01397 * This parameter can be one of the following values: 01398 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 01399 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 01400 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 01401 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 01402 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 01403 */ 01404 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 01405 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 01406 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 01407 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 01408 ((__HANDLE__)->Instance->CCR4)) 01409 01410 /** 01411 * @brief Set the TIM Output compare preload. 01412 * @param __HANDLE__ TIM handle. 01413 * @param __CHANNEL__ TIM Channels to be configured. 01414 * This parameter can be one of the following values: 01415 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01416 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01417 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01418 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01419 * @retval None 01420 */ 01421 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 01422 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 01423 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 01424 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 01425 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) 01426 01427 /** 01428 * @brief Reset the TIM Output compare preload. 01429 * @param __HANDLE__ TIM handle. 01430 * @param __CHANNEL__ TIM Channels to be configured. 01431 * This parameter can be one of the following values: 01432 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01433 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01434 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01435 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01436 * @retval None 01437 */ 01438 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 01439 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 01440 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 01441 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 01442 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) 01443 01444 /** 01445 * @brief Enable fast mode for a given channel. 01446 * @param __HANDLE__ TIM handle. 01447 * @param __CHANNEL__ TIM Channels to be configured. 01448 * This parameter can be one of the following values: 01449 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01450 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01451 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01452 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01453 * @note When fast mode is enabled an active edge on the trigger input acts 01454 * like a compare match on CCx output. Delay to sample the trigger 01455 * input and to activate CCx output is reduced to 3 clock cycles. 01456 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 01457 * @retval None 01458 */ 01459 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 01460 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 01461 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 01462 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 01463 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) 01464 01465 /** 01466 * @brief Disable fast mode for a given channel. 01467 * @param __HANDLE__ TIM handle. 01468 * @param __CHANNEL__ TIM Channels to be configured. 01469 * This parameter can be one of the following values: 01470 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01471 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01472 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01473 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01474 * @note When fast mode is disabled CCx output behaves normally depending 01475 * on counter and CCRx values even when the trigger is ON. The minimum 01476 * delay to activate CCx output when an active edge occurs on the 01477 * trigger input is 5 clock cycles. 01478 * @retval None 01479 */ 01480 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 01481 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 01482 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 01483 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 01484 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) 01485 01486 /** 01487 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 01488 * @param __HANDLE__ TIM handle. 01489 * @note When the URS bit of the TIMx_CR1 register is set, only counter 01490 * overflow/underflow generates an update interrupt or DMA request (if 01491 * enabled) 01492 * @retval None 01493 */ 01494 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 01495 01496 /** 01497 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 01498 * @param __HANDLE__ TIM handle. 01499 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 01500 * following events generate an update interrupt or DMA request (if 01501 * enabled): 01502 * _ Counter overflow underflow 01503 * _ Setting the UG bit 01504 * _ Update generation through the slave mode controller 01505 * @retval None 01506 */ 01507 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 01508 01509 /** 01510 * @brief Set the TIM Capture x input polarity on runtime. 01511 * @param __HANDLE__ TIM handle. 01512 * @param __CHANNEL__ TIM Channels to be configured. 01513 * This parameter can be one of the following values: 01514 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01515 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01516 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01517 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01518 * @param __POLARITY__ Polarity for TIx source 01519 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 01520 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 01521 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 01522 * @retval None 01523 */ 01524 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 01525 do{ \ 01526 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 01527 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 01528 }while(0) 01529 01530 /** 01531 * @} 01532 */ 01533 /* End of exported macros ----------------------------------------------------*/ 01534 01535 /* Private constants ---------------------------------------------------------*/ 01536 /** @defgroup TIM_Private_Constants TIM Private Constants 01537 * @{ 01538 */ 01539 /* The counter of a timer instance is disabled only if all the CCx and CCxN 01540 channels have been disabled */ 01541 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 01542 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 01543 /** 01544 * @} 01545 */ 01546 /* End of private constants --------------------------------------------------*/ 01547 01548 /* Private macros ------------------------------------------------------------*/ 01549 /** @defgroup TIM_Private_Macros TIM Private Macros 01550 * @{ 01551 */ 01552 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 01553 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) 01554 01555 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 01556 ((__BASE__) == TIM_DMABASE_CR2) || \ 01557 ((__BASE__) == TIM_DMABASE_SMCR) || \ 01558 ((__BASE__) == TIM_DMABASE_DIER) || \ 01559 ((__BASE__) == TIM_DMABASE_SR) || \ 01560 ((__BASE__) == TIM_DMABASE_EGR) || \ 01561 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 01562 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 01563 ((__BASE__) == TIM_DMABASE_CCER) || \ 01564 ((__BASE__) == TIM_DMABASE_CNT) || \ 01565 ((__BASE__) == TIM_DMABASE_PSC) || \ 01566 ((__BASE__) == TIM_DMABASE_ARR) || \ 01567 ((__BASE__) == TIM_DMABASE_RCR) || \ 01568 ((__BASE__) == TIM_DMABASE_CCR1) || \ 01569 ((__BASE__) == TIM_DMABASE_CCR2) || \ 01570 ((__BASE__) == TIM_DMABASE_CCR3) || \ 01571 ((__BASE__) == TIM_DMABASE_CCR4) || \ 01572 ((__BASE__) == TIM_DMABASE_BDTR)) 01573 01574 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 01575 01576 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 01577 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 01578 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 01579 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 01580 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 01581 01582 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 01583 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 01584 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 01585 01586 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 01587 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 01588 01589 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 01590 ((__STATE__) == TIM_OCFAST_ENABLE)) 01591 01592 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 01593 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 01594 01595 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 01596 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 01597 01598 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 01599 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 01600 01601 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 01602 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 01603 01604 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 01605 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 01606 01607 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 01608 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 01609 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 01610 01611 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 01612 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 01613 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 01614 01615 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 01616 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 01617 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 01618 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 01619 01620 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 01621 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 01622 01623 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 01624 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 01625 ((__MODE__) == TIM_ENCODERMODE_TI12)) 01626 01627 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 01628 01629 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 01630 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 01631 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 01632 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 01633 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 01634 01635 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 01636 ((__CHANNEL__) == TIM_CHANNEL_2)) 01637 01638 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 01639 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 01640 ((__CHANNEL__) == TIM_CHANNEL_3)) 01641 01642 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 01643 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 01644 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 01645 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 01646 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 01647 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 01648 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 01649 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 01650 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 01651 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) 01652 01653 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 01654 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 01655 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 01656 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 01657 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 01658 01659 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 01660 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 01661 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 01662 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 01663 01664 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 01665 01666 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 01667 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 01668 01669 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 01670 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 01671 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 01672 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 01673 01674 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 01675 01676 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 01677 ((__STATE__) == TIM_OSSR_DISABLE)) 01678 01679 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 01680 ((__STATE__) == TIM_OSSI_DISABLE)) 01681 01682 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 01683 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 01684 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 01685 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 01686 01687 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 01688 01689 01690 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 01691 ((__STATE__) == TIM_BREAK_DISABLE)) 01692 01693 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 01694 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 01695 01696 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 01697 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 01698 01699 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 01700 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 01701 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 01702 ((__SOURCE__) == TIM_TRGO_OC1) || \ 01703 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 01704 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 01705 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 01706 ((__SOURCE__) == TIM_TRGO_OC4REF)) 01707 01708 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 01709 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 01710 01711 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 01712 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 01713 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 01714 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 01715 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) 01716 01717 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 01718 ((__MODE__) == TIM_OCMODE_PWM2)) 01719 01720 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 01721 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 01722 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 01723 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 01724 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 01725 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) 01726 01727 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 01728 ((__SELECTION__) == TIM_TS_ITR1) || \ 01729 ((__SELECTION__) == TIM_TS_ITR2) || \ 01730 ((__SELECTION__) == TIM_TS_ITR3) || \ 01731 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 01732 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 01733 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 01734 ((__SELECTION__) == TIM_TS_ETRF)) 01735 01736 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 01737 ((__SELECTION__) == TIM_TS_ITR1) || \ 01738 ((__SELECTION__) == TIM_TS_ITR2) || \ 01739 ((__SELECTION__) == TIM_TS_ITR3) || \ 01740 ((__SELECTION__) == TIM_TS_NONE)) 01741 01742 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 01743 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 01744 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 01745 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 01746 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 01747 01748 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 01749 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 01750 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 01751 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 01752 01753 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 01754 01755 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 01756 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 01757 01758 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 01759 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 01760 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 01761 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 01762 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 01763 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 01764 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 01765 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 01766 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 01767 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 01768 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 01769 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 01770 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 01771 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 01772 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 01773 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 01774 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 01775 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 01776 01777 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) 01778 01779 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 01780 01781 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 01782 01783 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) 01784 01785 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 01786 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 01787 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 01788 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 01789 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 01790 01791 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 01792 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 01793 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 01794 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 01795 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 01796 01797 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 01798 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 01799 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 01800 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 01801 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 01802 01803 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 01804 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 01805 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 01806 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\ 01807 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P))) 01808 01809 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 01810 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 01811 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 01812 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 01813 (__HANDLE__)->ChannelState[3]) 01814 01815 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 01816 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 01817 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 01818 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 01819 ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) 01820 01821 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 01822 (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ 01823 (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ 01824 (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ 01825 (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ 01826 } while(0) 01827 01828 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ 01829 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ 01830 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ 01831 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ 01832 (__HANDLE__)->ChannelNState[3]) 01833 01834 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 01835 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ 01836 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ 01837 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ 01838 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) 01839 01840 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 01841 (__HANDLE__)->ChannelNState[0] = \ 01842 (__CHANNEL_STATE__); \ 01843 (__HANDLE__)->ChannelNState[1] = \ 01844 (__CHANNEL_STATE__); \ 01845 (__HANDLE__)->ChannelNState[2] = \ 01846 (__CHANNEL_STATE__); \ 01847 (__HANDLE__)->ChannelNState[3] = \ 01848 (__CHANNEL_STATE__); \ 01849 } while(0) 01850 01851 /** 01852 * @} 01853 */ 01854 /* End of private macros -----------------------------------------------------*/ 01855 01856 /* Include TIM HAL Extended module */ 01857 #include "stm32f1xx_hal_tim_ex.h" 01858 01859 /* Exported functions --------------------------------------------------------*/ 01860 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 01861 * @{ 01862 */ 01863 01864 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 01865 * @brief Time Base functions 01866 * @{ 01867 */ 01868 /* Time Base functions ********************************************************/ 01869 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 01870 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 01871 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 01872 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 01873 /* Blocking mode: Polling */ 01874 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 01875 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 01876 /* Non-Blocking mode: Interrupt */ 01877 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 01878 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 01879 /* Non-Blocking mode: DMA */ 01880 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 01881 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 01882 /** 01883 * @} 01884 */ 01885 01886 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 01887 * @brief TIM Output Compare functions 01888 * @{ 01889 */ 01890 /* Timer Output Compare functions *********************************************/ 01891 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 01892 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 01893 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 01894 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 01895 /* Blocking mode: Polling */ 01896 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01897 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01898 /* Non-Blocking mode: Interrupt */ 01899 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01900 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01901 /* Non-Blocking mode: DMA */ 01902 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 01903 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01904 /** 01905 * @} 01906 */ 01907 01908 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 01909 * @brief TIM PWM functions 01910 * @{ 01911 */ 01912 /* Timer PWM functions ********************************************************/ 01913 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 01914 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 01915 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 01916 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 01917 /* Blocking mode: Polling */ 01918 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01919 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01920 /* Non-Blocking mode: Interrupt */ 01921 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01922 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01923 /* Non-Blocking mode: DMA */ 01924 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 01925 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01926 /** 01927 * @} 01928 */ 01929 01930 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 01931 * @brief TIM Input Capture functions 01932 * @{ 01933 */ 01934 /* Timer Input Capture functions **********************************************/ 01935 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 01936 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 01937 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 01938 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 01939 /* Blocking mode: Polling */ 01940 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01941 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01942 /* Non-Blocking mode: Interrupt */ 01943 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01944 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01945 /* Non-Blocking mode: DMA */ 01946 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 01947 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01948 /** 01949 * @} 01950 */ 01951 01952 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 01953 * @brief TIM One Pulse functions 01954 * @{ 01955 */ 01956 /* Timer One Pulse functions **************************************************/ 01957 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 01958 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 01959 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 01960 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 01961 /* Blocking mode: Polling */ 01962 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01963 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01964 /* Non-Blocking mode: Interrupt */ 01965 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01966 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01967 /** 01968 * @} 01969 */ 01970 01971 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 01972 * @brief TIM Encoder functions 01973 * @{ 01974 */ 01975 /* Timer Encoder functions ****************************************************/ 01976 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 01977 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 01978 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 01979 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 01980 /* Blocking mode: Polling */ 01981 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01982 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01983 /* Non-Blocking mode: Interrupt */ 01984 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01985 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01986 /* Non-Blocking mode: DMA */ 01987 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 01988 uint32_t *pData2, uint16_t Length); 01989 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01990 /** 01991 * @} 01992 */ 01993 01994 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 01995 * @brief IRQ handler management 01996 * @{ 01997 */ 01998 /* Interrupt Handler functions ***********************************************/ 01999 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 02000 /** 02001 * @} 02002 */ 02003 02004 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 02005 * @brief Peripheral Control functions 02006 * @{ 02007 */ 02008 /* Control functions *********************************************************/ 02009 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 02010 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 02011 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 02012 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 02013 uint32_t OutputChannel, uint32_t InputChannel); 02014 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, 02015 uint32_t Channel); 02016 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 02017 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 02018 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 02019 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 02020 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 02021 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 02022 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 02023 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 02024 uint32_t BurstLength, uint32_t DataLength); 02025 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 02026 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 02027 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 02028 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 02029 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 02030 uint32_t BurstLength, uint32_t DataLength); 02031 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 02032 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 02033 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 02034 /** 02035 * @} 02036 */ 02037 02038 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 02039 * @brief TIM Callbacks functions 02040 * @{ 02041 */ 02042 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 02043 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 02044 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 02045 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 02046 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 02047 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 02048 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 02049 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 02050 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 02051 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 02052 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 02053 02054 /* Callbacks Register/UnRegister functions ***********************************/ 02055 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 02056 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 02057 pTIM_CallbackTypeDef pCallback); 02058 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 02059 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 02060 02061 /** 02062 * @} 02063 */ 02064 02065 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 02066 * @brief Peripheral State functions 02067 * @{ 02068 */ 02069 /* Peripheral State functions ************************************************/ 02070 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 02071 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 02072 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 02073 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 02074 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 02075 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 02076 02077 /* Peripheral Channel state functions ************************************************/ 02078 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); 02079 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); 02080 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); 02081 /** 02082 * @} 02083 */ 02084 02085 /** 02086 * @} 02087 */ 02088 /* End of exported functions -------------------------------------------------*/ 02089 02090 /* Private functions----------------------------------------------------------*/ 02091 /** @defgroup TIM_Private_Functions TIM Private Functions 02092 * @{ 02093 */ 02094 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 02095 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 02096 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 02097 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 02098 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 02099 02100 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 02101 void TIM_DMAError(DMA_HandleTypeDef *hdma); 02102 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 02103 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 02104 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 02105 02106 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 02107 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 02108 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 02109 02110 /** 02111 * @} 02112 */ 02113 /* End of private functions --------------------------------------------------*/ 02114 02115 /** 02116 * @} 02117 */ 02118 02119 /** 02120 * @} 02121 */ 02122 02123 #ifdef __cplusplus 02124 } 02125 #endif 02126 02127 #endif /* STM32F1xx_HAL_TIM_H */ 02128 02129 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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