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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_ll_dma.c 00004 * @author MCD Application Team 00005 * @brief DMA LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 #if defined(USE_FULL_LL_DRIVER) 00021 00022 /* Includes ------------------------------------------------------------------*/ 00023 #include "stm32f1xx_ll_dma.h" 00024 #include "stm32f1xx_ll_bus.h" 00025 #ifdef USE_FULL_ASSERT 00026 #include "stm32_assert.h" 00027 #else 00028 #define assert_param(expr) ((void)0U) 00029 #endif 00030 00031 /** @addtogroup STM32F1xx_LL_Driver 00032 * @{ 00033 */ 00034 00035 #if defined (DMA1) || defined (DMA2) 00036 00037 /** @defgroup DMA_LL DMA 00038 * @{ 00039 */ 00040 00041 /* Private types -------------------------------------------------------------*/ 00042 /* Private variables ---------------------------------------------------------*/ 00043 /* Private constants ---------------------------------------------------------*/ 00044 /* Private macros ------------------------------------------------------------*/ 00045 /** @addtogroup DMA_LL_Private_Macros 00046 * @{ 00047 */ 00048 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ 00049 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ 00050 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) 00051 00052 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ 00053 ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) 00054 00055 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ 00056 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) 00057 00058 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ 00059 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) 00060 00061 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ 00062 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ 00063 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) 00064 00065 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ 00066 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ 00067 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) 00068 00069 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) 00070 00071 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ 00072 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ 00073 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ 00074 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) 00075 00076 #if defined (DMA2) 00077 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ 00078 (((CHANNEL) == LL_DMA_CHANNEL_1) || \ 00079 ((CHANNEL) == LL_DMA_CHANNEL_2) || \ 00080 ((CHANNEL) == LL_DMA_CHANNEL_3) || \ 00081 ((CHANNEL) == LL_DMA_CHANNEL_4) || \ 00082 ((CHANNEL) == LL_DMA_CHANNEL_5) || \ 00083 ((CHANNEL) == LL_DMA_CHANNEL_6) || \ 00084 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ 00085 (((INSTANCE) == DMA2) && \ 00086 (((CHANNEL) == LL_DMA_CHANNEL_1) || \ 00087 ((CHANNEL) == LL_DMA_CHANNEL_2) || \ 00088 ((CHANNEL) == LL_DMA_CHANNEL_3) || \ 00089 ((CHANNEL) == LL_DMA_CHANNEL_4) || \ 00090 ((CHANNEL) == LL_DMA_CHANNEL_5)))) 00091 #else 00092 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ 00093 (((CHANNEL) == LL_DMA_CHANNEL_1) || \ 00094 ((CHANNEL) == LL_DMA_CHANNEL_2) || \ 00095 ((CHANNEL) == LL_DMA_CHANNEL_3) || \ 00096 ((CHANNEL) == LL_DMA_CHANNEL_4) || \ 00097 ((CHANNEL) == LL_DMA_CHANNEL_5) || \ 00098 ((CHANNEL) == LL_DMA_CHANNEL_6) || \ 00099 ((CHANNEL) == LL_DMA_CHANNEL_7)))) 00100 #endif 00101 /** 00102 * @} 00103 */ 00104 00105 /* Private function prototypes -----------------------------------------------*/ 00106 /* Exported functions --------------------------------------------------------*/ 00107 /** @addtogroup DMA_LL_Exported_Functions 00108 * @{ 00109 */ 00110 00111 /** @addtogroup DMA_LL_EF_Init 00112 * @{ 00113 */ 00114 00115 /** 00116 * @brief De-initialize the DMA registers to their default reset values. 00117 * @param DMAx DMAx Instance 00118 * @param Channel This parameter can be one of the following values: 00119 * @arg @ref LL_DMA_CHANNEL_1 00120 * @arg @ref LL_DMA_CHANNEL_2 00121 * @arg @ref LL_DMA_CHANNEL_3 00122 * @arg @ref LL_DMA_CHANNEL_4 00123 * @arg @ref LL_DMA_CHANNEL_5 00124 * @arg @ref LL_DMA_CHANNEL_6 00125 * @arg @ref LL_DMA_CHANNEL_7 00126 * @retval An ErrorStatus enumeration value: 00127 * - SUCCESS: DMA registers are de-initialized 00128 * - ERROR: DMA registers are not de-initialized 00129 */ 00130 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) 00131 { 00132 DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; 00133 ErrorStatus status = SUCCESS; 00134 00135 /* Check the DMA Instance DMAx and Channel parameters*/ 00136 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); 00137 00138 tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); 00139 00140 /* Disable the selected DMAx_Channely */ 00141 CLEAR_BIT(tmp->CCR, DMA_CCR_EN); 00142 00143 /* Reset DMAx_Channely control register */ 00144 LL_DMA_WriteReg(tmp, CCR, 0U); 00145 00146 /* Reset DMAx_Channely remaining bytes register */ 00147 LL_DMA_WriteReg(tmp, CNDTR, 0U); 00148 00149 /* Reset DMAx_Channely peripheral address register */ 00150 LL_DMA_WriteReg(tmp, CPAR, 0U); 00151 00152 /* Reset DMAx_Channely memory address register */ 00153 LL_DMA_WriteReg(tmp, CMAR, 0U); 00154 00155 if (Channel == LL_DMA_CHANNEL_1) 00156 { 00157 /* Reset interrupt pending bits for DMAx Channel1 */ 00158 LL_DMA_ClearFlag_GI1(DMAx); 00159 } 00160 else if (Channel == LL_DMA_CHANNEL_2) 00161 { 00162 /* Reset interrupt pending bits for DMAx Channel2 */ 00163 LL_DMA_ClearFlag_GI2(DMAx); 00164 } 00165 else if (Channel == LL_DMA_CHANNEL_3) 00166 { 00167 /* Reset interrupt pending bits for DMAx Channel3 */ 00168 LL_DMA_ClearFlag_GI3(DMAx); 00169 } 00170 else if (Channel == LL_DMA_CHANNEL_4) 00171 { 00172 /* Reset interrupt pending bits for DMAx Channel4 */ 00173 LL_DMA_ClearFlag_GI4(DMAx); 00174 } 00175 else if (Channel == LL_DMA_CHANNEL_5) 00176 { 00177 /* Reset interrupt pending bits for DMAx Channel5 */ 00178 LL_DMA_ClearFlag_GI5(DMAx); 00179 } 00180 00181 else if (Channel == LL_DMA_CHANNEL_6) 00182 { 00183 /* Reset interrupt pending bits for DMAx Channel6 */ 00184 LL_DMA_ClearFlag_GI6(DMAx); 00185 } 00186 else if (Channel == LL_DMA_CHANNEL_7) 00187 { 00188 /* Reset interrupt pending bits for DMAx Channel7 */ 00189 LL_DMA_ClearFlag_GI7(DMAx); 00190 } 00191 else 00192 { 00193 status = ERROR; 00194 } 00195 00196 return status; 00197 } 00198 00199 /** 00200 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. 00201 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : 00202 * @arg @ref __LL_DMA_GET_INSTANCE 00203 * @arg @ref __LL_DMA_GET_CHANNEL 00204 * @param DMAx DMAx Instance 00205 * @param Channel This parameter can be one of the following values: 00206 * @arg @ref LL_DMA_CHANNEL_1 00207 * @arg @ref LL_DMA_CHANNEL_2 00208 * @arg @ref LL_DMA_CHANNEL_3 00209 * @arg @ref LL_DMA_CHANNEL_4 00210 * @arg @ref LL_DMA_CHANNEL_5 00211 * @arg @ref LL_DMA_CHANNEL_6 00212 * @arg @ref LL_DMA_CHANNEL_7 00213 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. 00214 * @retval An ErrorStatus enumeration value: 00215 * - SUCCESS: DMA registers are initialized 00216 * - ERROR: Not applicable 00217 */ 00218 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) 00219 { 00220 /* Check the DMA Instance DMAx and Channel parameters*/ 00221 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); 00222 00223 /* Check the DMA parameters from DMA_InitStruct */ 00224 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); 00225 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); 00226 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); 00227 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); 00228 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); 00229 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); 00230 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); 00231 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); 00232 00233 /*---------------------------- DMAx CCR Configuration ------------------------ 00234 * Configure DMAx_Channely: data transfer direction, data transfer mode, 00235 * peripheral and memory increment mode, 00236 * data size alignment and priority level with parameters : 00237 * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits 00238 * - Mode: DMA_CCR_CIRC bit 00239 * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit 00240 * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit 00241 * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits 00242 * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits 00243 * - Priority: DMA_CCR_PL[1:0] bits 00244 */ 00245 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ 00246 DMA_InitStruct->Mode | \ 00247 DMA_InitStruct->PeriphOrM2MSrcIncMode | \ 00248 DMA_InitStruct->MemoryOrM2MDstIncMode | \ 00249 DMA_InitStruct->PeriphOrM2MSrcDataSize | \ 00250 DMA_InitStruct->MemoryOrM2MDstDataSize | \ 00251 DMA_InitStruct->Priority); 00252 00253 /*-------------------------- DMAx CMAR Configuration ------------------------- 00254 * Configure the memory or destination base address with parameter : 00255 * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits 00256 */ 00257 LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); 00258 00259 /*-------------------------- DMAx CPAR Configuration ------------------------- 00260 * Configure the peripheral or source base address with parameter : 00261 * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits 00262 */ 00263 LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); 00264 00265 /*--------------------------- DMAx CNDTR Configuration ----------------------- 00266 * Configure the peripheral base address with parameter : 00267 * - NbData: DMA_CNDTR_NDT[15:0] bits 00268 */ 00269 LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); 00270 00271 return SUCCESS; 00272 } 00273 00274 /** 00275 * @brief Set each @ref LL_DMA_InitTypeDef field to default value. 00276 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. 00277 * @retval None 00278 */ 00279 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) 00280 { 00281 /* Set DMA_InitStruct fields to default values */ 00282 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; 00283 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; 00284 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; 00285 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; 00286 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; 00287 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; 00288 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; 00289 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; 00290 DMA_InitStruct->NbData = 0x00000000U; 00291 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; 00292 } 00293 00294 /** 00295 * @} 00296 */ 00297 00298 /** 00299 * @} 00300 */ 00301 00302 /** 00303 * @} 00304 */ 00305 00306 #endif /* DMA1 || DMA2 */ 00307 00308 /** 00309 * @} 00310 */ 00311 00312 #endif /* USE_FULL_LL_DRIVER */ 00313 00314 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1