STM32F479xx HAL User Manual
Defines
AHB1 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB1 peripheral clock. More...

Defines

#define __HAL_RCC_GPIOA_CLK_ENABLE()
#define __HAL_RCC_GPIOB_CLK_ENABLE()
#define __HAL_RCC_GPIOC_CLK_ENABLE()
#define __HAL_RCC_GPIOH_CLK_ENABLE()
#define __HAL_RCC_DMA1_CLK_ENABLE()
#define __HAL_RCC_DMA2_CLK_ENABLE()
#define __HAL_RCC_GPIOA_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
#define __HAL_RCC_GPIOB_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
#define __HAL_RCC_GPIOC_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
#define __HAL_RCC_GPIOH_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
#define __HAL_RCC_DMA1_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
#define __HAL_RCC_DMA2_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))

Detailed Description

Enable or disable the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_DMA1_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))

Definition at line 433 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        UNUSED(tmpreg); \
                                         } while(0U)

Definition at line 414 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))

Definition at line 434 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 421 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))

Definition at line 429 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 386 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))

Definition at line 430 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 393 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))

Definition at line 431 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 400 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))

Definition at line 432 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
                                        UNUSED(tmpreg); \
                                         } while(0U)

Definition at line 407 of file stm32f4xx_hal_rcc.h.

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