Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Defines
#define	__HAL_RCC_TIM5_CLK_ENABLE()
#define	__HAL_RCC_WWDG_CLK_ENABLE()
#define	__HAL_RCC_SPI2_CLK_ENABLE()
#define	__HAL_RCC_USART2_CLK_ENABLE()
#define	__HAL_RCC_I2C1_CLK_ENABLE()
#define	__HAL_RCC_I2C2_CLK_ENABLE()
#define	__HAL_RCC_PWR_CLK_ENABLE()
#define	__HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define	__HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define	__HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define	__HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define	__HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define	__HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#define	__HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note:: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_I2C1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

Definition at line 524 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 498 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

Definition at line 525 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 505 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Definition at line 526 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PWR_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 512 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableOverDrive(), HAL_PWREx_EnableOverDrive(), HAL_PWREx_EnterUnderDriveSTOPMode(), HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

Definition at line 522 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 484 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

Definition at line 520 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 470 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

Definition at line 523 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 491 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

Definition at line 521 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 477 of file stm32f4xx_hal_rcc.h.

Defines

Detailed Description

Define Documentation