STM32F479xx HAL User Manual: stm32f4xx_ll

Header file of BUS LL module. More...

#include "stm32f4xx.h"

Defines
#define	LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define	LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
#define	LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
#define	LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
#define	LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
#define	LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
#define	LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
#define	LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
#define	LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
#define	LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
#define	LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN
#define	LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN
#define	LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
#define	LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
#define	LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN
#define	LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
#define	LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
#define	LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
#define	LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
#define	LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
#define	LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
#define	LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
#define	LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
#define	LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
#define	LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
#define	LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
#define	LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
#define	LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN
#define	LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define	LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
#define	LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
#define	LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
#define	LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
#define	LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
#define	LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define	LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
#define	LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
#define	LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define	LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
#define	LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
#define	LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
#define	LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
#define	LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
#define	LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
#define	LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
#define	LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
#define	LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
#define	LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
#define	LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
#define	LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
#define	LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
#define	LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
#define	LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
#define	LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
#define	LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
#define	LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
#define	LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
#define	LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
#define	LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
#define	LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
#define	LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
#define	LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN
#define	LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN
#define	LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define	LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define	LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
#define	LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define	LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
#define	LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
#define	LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
#define	LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
#define	LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
#define	LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define	LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
#define	LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
#define	LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
#define	LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
#define	LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
#define	LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
#define	LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
#define	LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
#define	LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
#define	LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
#define	LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
Functions
__STATIC_INLINE void	LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t	LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB1 peripherals clock.
__STATIC_INLINE void	LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
	Force AHB1 peripherals reset.
__STATIC_INLINE void	LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB1 peripherals reset.
__STATIC_INLINE void	LL_AHB1_GRP1_EnableClockLowPower (uint32_t Periphs)
	Enable AHB1 peripheral clocks in low-power mode.
__STATIC_INLINE void	LL_AHB1_GRP1_DisableClockLowPower (uint32_t Periphs)
	Disable AHB1 peripheral clocks in low-power mode.
__STATIC_INLINE void	LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB2 peripherals clock.
__STATIC_INLINE uint32_t	LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB2 peripherals clock.
__STATIC_INLINE void	LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
	Force AHB2 peripherals reset.
__STATIC_INLINE void	LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB2 peripherals reset.
__STATIC_INLINE void	LL_AHB2_GRP1_EnableClockLowPower (uint32_t Periphs)
	Enable AHB2 peripheral clocks in low-power mode.
__STATIC_INLINE void	LL_AHB2_GRP1_DisableClockLowPower (uint32_t Periphs)
	Disable AHB2 peripheral clocks in low-power mode.
__STATIC_INLINE void	LL_AHB3_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB3 peripherals clock.
__STATIC_INLINE uint32_t	LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_AHB3_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB3 peripherals clock.
__STATIC_INLINE void	LL_AHB3_GRP1_ForceReset (uint32_t Periphs)
	Force AHB3 peripherals reset.
__STATIC_INLINE void	LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB3 peripherals reset.
__STATIC_INLINE void	LL_AHB3_GRP1_EnableClockLowPower (uint32_t Periphs)
	Enable AHB3 peripheral clocks in low-power mode.
__STATIC_INLINE void	LL_AHB3_GRP1_DisableClockLowPower (uint32_t Periphs)
	Disable AHB3 peripheral clocks in low-power mode.
__STATIC_INLINE void	LL_APB1_GRP1_EnableClock (uint32_t Periphs)
	Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t	LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_APB1_GRP1_DisableClock (uint32_t Periphs)
	Disable APB1 peripherals clock.
__STATIC_INLINE void	LL_APB1_GRP1_ForceReset (uint32_t Periphs)
	Force APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
	Release APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP1_EnableClockLowPower (uint32_t Periphs)
	Enable APB1 peripheral clocks in low-power mode.
__STATIC_INLINE void	LL_APB1_GRP1_DisableClockLowPower (uint32_t Periphs)
	Disable APB1 peripheral clocks in low-power mode.
__STATIC_INLINE void	LL_APB2_GRP1_EnableClock (uint32_t Periphs)
	Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t	LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_APB2_GRP1_DisableClock (uint32_t Periphs)
	Disable APB2 peripherals clock.
__STATIC_INLINE void	LL_APB2_GRP1_ForceReset (uint32_t Periphs)
	Force APB2 peripherals reset.
__STATIC_INLINE void	LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
	Release APB2 peripherals reset.
__STATIC_INLINE void	LL_APB2_GRP1_EnableClockLowPower (uint32_t Periphs)
	Enable APB2 peripheral clocks in low-power mode.
__STATIC_INLINE void	LL_APB2_GRP1_DisableClockLowPower (uint32_t Periphs)
	Disable APB2 peripheral clocks in low-power mode.

Detailed Description

Header file of BUS LL module.

Author:

MCD Application Team

                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.

Attention:

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32f4xx_ll_bus.h.

Defines

Functions

Detailed Description

© Copyright (c) 2017 STMicroelectronics. All rights reserved.