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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_bus.h 00004 * @author MCD Application Team 00005 * @brief Header file of BUS LL module. 00006 00007 @verbatim 00008 ##### RCC Limitations ##### 00009 ============================================================================== 00010 [..] 00011 A delay between an RCC peripheral clock enable and the effective peripheral 00012 enabling should be taken into account in order to manage the peripheral read/write 00013 from/to registers. 00014 (+) This delay depends on the peripheral mapping. 00015 (++) AHB & APB peripherals, 1 dummy read is necessary 00016 00017 [..] 00018 Workarounds: 00019 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 00020 inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 00021 00022 @endverbatim 00023 ****************************************************************************** 00024 * @attention 00025 * 00026 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00027 * All rights reserved.</center></h2> 00028 * 00029 * This software component is licensed by ST under BSD 3-Clause license, 00030 * the "License"; You may not use this file except in compliance with the 00031 * License. You may obtain a copy of the License at: 00032 * opensource.org/licenses/BSD-3-Clause 00033 * 00034 ****************************************************************************** 00035 */ 00036 00037 /* Define to prevent recursive inclusion -------------------------------------*/ 00038 #ifndef __STM32F4xx_LL_BUS_H 00039 #define __STM32F4xx_LL_BUS_H 00040 00041 #ifdef __cplusplus 00042 extern "C" { 00043 #endif 00044 00045 /* Includes ------------------------------------------------------------------*/ 00046 #include "stm32f4xx.h" 00047 00048 /** @addtogroup STM32F4xx_LL_Driver 00049 * @{ 00050 */ 00051 00052 #if defined(RCC) 00053 00054 /** @defgroup BUS_LL BUS 00055 * @{ 00056 */ 00057 00058 /* Private types -------------------------------------------------------------*/ 00059 /* Private variables ---------------------------------------------------------*/ 00060 /* Private constants ---------------------------------------------------------*/ 00061 /* Private macros ------------------------------------------------------------*/ 00062 /* Exported types ------------------------------------------------------------*/ 00063 /* Exported constants --------------------------------------------------------*/ 00064 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 00065 * @{ 00066 */ 00067 00068 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 00069 * @{ 00070 */ 00071 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 00072 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN 00073 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN 00074 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN 00075 #if defined(GPIOD) 00076 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN 00077 #endif /* GPIOD */ 00078 #if defined(GPIOE) 00079 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN 00080 #endif /* GPIOE */ 00081 #if defined(GPIOF) 00082 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN 00083 #endif /* GPIOF */ 00084 #if defined(GPIOG) 00085 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN 00086 #endif /* GPIOG */ 00087 #if defined(GPIOH) 00088 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN 00089 #endif /* GPIOH */ 00090 #if defined(GPIOI) 00091 #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN 00092 #endif /* GPIOI */ 00093 #if defined(GPIOJ) 00094 #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN 00095 #endif /* GPIOJ */ 00096 #if defined(GPIOK) 00097 #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN 00098 #endif /* GPIOK */ 00099 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 00100 #if defined(RCC_AHB1ENR_BKPSRAMEN) 00101 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN 00102 #endif /* RCC_AHB1ENR_BKPSRAMEN */ 00103 #if defined(RCC_AHB1ENR_CCMDATARAMEN) 00104 #define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN 00105 #endif /* RCC_AHB1ENR_CCMDATARAMEN */ 00106 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN 00107 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 00108 #if defined(RCC_AHB1ENR_RNGEN) 00109 #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN 00110 #endif /* RCC_AHB1ENR_RNGEN */ 00111 #if defined(DMA2D) 00112 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN 00113 #endif /* DMA2D */ 00114 #if defined(ETH) 00115 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN 00116 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN 00117 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN 00118 #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN 00119 #endif /* ETH */ 00120 #if defined(USB_OTG_HS) 00121 #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN 00122 #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN 00123 #endif /* USB_OTG_HS */ 00124 #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN 00125 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN 00126 #if defined(RCC_AHB1LPENR_SRAM2LPEN) 00127 #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN 00128 #endif /* RCC_AHB1LPENR_SRAM2LPEN */ 00129 #if defined(RCC_AHB1LPENR_SRAM3LPEN) 00130 #define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN 00131 #endif /* RCC_AHB1LPENR_SRAM3LPEN */ 00132 /** 00133 * @} 00134 */ 00135 00136 #if defined(RCC_AHB2_SUPPORT) 00137 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 00138 * @{ 00139 */ 00140 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 00141 #if defined(DCMI) 00142 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN 00143 #endif /* DCMI */ 00144 #if defined(CRYP) 00145 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN 00146 #endif /* CRYP */ 00147 #if defined(AES) 00148 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN 00149 #endif /* AES */ 00150 #if defined(HASH) 00151 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN 00152 #endif /* HASH */ 00153 #if defined(RCC_AHB2ENR_RNGEN) 00154 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 00155 #endif /* RCC_AHB2ENR_RNGEN */ 00156 #if defined(USB_OTG_FS) 00157 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN 00158 #endif /* USB_OTG_FS */ 00159 /** 00160 * @} 00161 */ 00162 #endif /* RCC_AHB2_SUPPORT */ 00163 00164 #if defined(RCC_AHB3_SUPPORT) 00165 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 00166 * @{ 00167 */ 00168 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU 00169 #if defined(FSMC_Bank1) 00170 #define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN 00171 #endif /* FSMC_Bank1 */ 00172 #if defined(FMC_Bank1) 00173 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 00174 #endif /* FMC_Bank1 */ 00175 #if defined(QUADSPI) 00176 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 00177 #endif /* QUADSPI */ 00178 /** 00179 * @} 00180 */ 00181 #endif /* RCC_AHB3_SUPPORT */ 00182 00183 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 00184 * @{ 00185 */ 00186 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 00187 #if defined(TIM2) 00188 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN 00189 #endif /* TIM2 */ 00190 #if defined(TIM3) 00191 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN 00192 #endif /* TIM3 */ 00193 #if defined(TIM4) 00194 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN 00195 #endif /* TIM4 */ 00196 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN 00197 #if defined(TIM6) 00198 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN 00199 #endif /* TIM6 */ 00200 #if defined(TIM7) 00201 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN 00202 #endif /* TIM7 */ 00203 #if defined(TIM12) 00204 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN 00205 #endif /* TIM12 */ 00206 #if defined(TIM13) 00207 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN 00208 #endif /* TIM13 */ 00209 #if defined(TIM14) 00210 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN 00211 #endif /* TIM14 */ 00212 #if defined(LPTIM1) 00213 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN 00214 #endif /* LPTIM1 */ 00215 #if defined(RCC_APB1ENR_RTCAPBEN) 00216 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN 00217 #endif /* RCC_APB1ENR_RTCAPBEN */ 00218 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN 00219 #if defined(SPI2) 00220 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN 00221 #endif /* SPI2 */ 00222 #if defined(SPI3) 00223 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN 00224 #endif /* SPI3 */ 00225 #if defined(SPDIFRX) 00226 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN 00227 #endif /* SPDIFRX */ 00228 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN 00229 #if defined(USART3) 00230 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN 00231 #endif /* USART3 */ 00232 #if defined(UART4) 00233 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN 00234 #endif /* UART4 */ 00235 #if defined(UART5) 00236 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN 00237 #endif /* UART5 */ 00238 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN 00239 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN 00240 #if defined(I2C3) 00241 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN 00242 #endif /* I2C3 */ 00243 #if defined(FMPI2C1) 00244 #define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN 00245 #endif /* FMPI2C1 */ 00246 #if defined(CAN1) 00247 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN 00248 #endif /* CAN1 */ 00249 #if defined(CAN2) 00250 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN 00251 #endif /* CAN2 */ 00252 #if defined(CAN3) 00253 #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN 00254 #endif /* CAN3 */ 00255 #if defined(CEC) 00256 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN 00257 #endif /* CEC */ 00258 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN 00259 #if defined(DAC1) 00260 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN 00261 #endif /* DAC1 */ 00262 #if defined(UART7) 00263 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN 00264 #endif /* UART7 */ 00265 #if defined(UART8) 00266 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN 00267 #endif /* UART8 */ 00268 /** 00269 * @} 00270 */ 00271 00272 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 00273 * @{ 00274 */ 00275 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 00276 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 00277 #if defined(TIM8) 00278 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 00279 #endif /* TIM8 */ 00280 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 00281 #if defined(USART6) 00282 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN 00283 #endif /* USART6 */ 00284 #if defined(UART9) 00285 #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN 00286 #endif /* UART9 */ 00287 #if defined(UART10) 00288 #define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN 00289 #endif /* UART10 */ 00290 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN 00291 #if defined(ADC2) 00292 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN 00293 #endif /* ADC2 */ 00294 #if defined(ADC3) 00295 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN 00296 #endif /* ADC3 */ 00297 #if defined(SDIO) 00298 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN 00299 #endif /* SDIO */ 00300 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 00301 #if defined(SPI4) 00302 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN 00303 #endif /* SPI4 */ 00304 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN 00305 #if defined(RCC_APB2ENR_EXTITEN) 00306 #define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN 00307 #endif /* RCC_APB2ENR_EXTITEN */ 00308 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN 00309 #if defined(TIM10) 00310 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN 00311 #endif /* TIM10 */ 00312 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN 00313 #if defined(SPI5) 00314 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN 00315 #endif /* SPI5 */ 00316 #if defined(SPI6) 00317 #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN 00318 #endif /* SPI6 */ 00319 #if defined(SAI1) 00320 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN 00321 #endif /* SAI1 */ 00322 #if defined(SAI2) 00323 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN 00324 #endif /* SAI2 */ 00325 #if defined(LTDC) 00326 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN 00327 #endif /* LTDC */ 00328 #if defined(DSI) 00329 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN 00330 #endif /* DSI */ 00331 #if defined(DFSDM1_Channel0) 00332 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN 00333 #endif /* DFSDM1_Channel0 */ 00334 #if defined(DFSDM2_Channel0) 00335 #define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN 00336 #endif /* DFSDM2_Channel0 */ 00337 #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST 00338 /** 00339 * @} 00340 */ 00341 00342 /** 00343 * @} 00344 */ 00345 00346 /* Exported macro ------------------------------------------------------------*/ 00347 /* Exported functions --------------------------------------------------------*/ 00348 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 00349 * @{ 00350 */ 00351 00352 /** @defgroup BUS_LL_EF_AHB1 AHB1 00353 * @{ 00354 */ 00355 00356 /** 00357 * @brief Enable AHB1 peripherals clock. 00358 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n 00359 * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n 00360 * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n 00361 * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n 00362 * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n 00363 * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n 00364 * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n 00365 * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n 00366 * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n 00367 * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n 00368 * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n 00369 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n 00370 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n 00371 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n 00372 * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n 00373 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n 00374 * AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n 00375 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n 00376 * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n 00377 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n 00378 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n 00379 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n 00380 * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n 00381 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock 00382 * @param Periphs This parameter can be a combination of the following values: 00383 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00384 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00385 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00386 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00387 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00388 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00389 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00390 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00391 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00392 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00393 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00394 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00395 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) 00396 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) 00397 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00398 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00399 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00400 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00401 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00402 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00403 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00404 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 00405 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00406 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) 00407 * 00408 * (*) value not defined in all devices. 00409 * @retval None 00410 */ 00411 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 00412 { 00413 __IO uint32_t tmpreg; 00414 SET_BIT(RCC->AHB1ENR, Periphs); 00415 /* Delay after an RCC peripheral clock enabling */ 00416 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 00417 (void)tmpreg; 00418 } 00419 00420 /** 00421 * @brief Check if AHB1 peripheral clock is enabled or not 00422 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n 00423 * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n 00424 * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n 00425 * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n 00426 * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n 00427 * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n 00428 * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n 00429 * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n 00430 * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n 00431 * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n 00432 * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n 00433 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n 00434 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n 00435 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n 00436 * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n 00437 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n 00438 * AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n 00439 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n 00440 * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n 00441 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n 00442 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n 00443 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n 00444 * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n 00445 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock 00446 * @param Periphs This parameter can be a combination of the following values: 00447 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00448 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00449 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00450 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00451 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00452 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00453 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00454 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00455 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00456 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00457 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00458 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00459 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) 00460 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) 00461 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00462 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00463 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00464 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00465 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00466 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00467 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00468 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 00469 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00470 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) 00471 * 00472 * (*) value not defined in all devices. 00473 * @retval State of Periphs (1 or 0). 00474 */ 00475 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 00476 { 00477 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); 00478 } 00479 00480 /** 00481 * @brief Disable AHB1 peripherals clock. 00482 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n 00483 * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n 00484 * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n 00485 * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n 00486 * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n 00487 * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n 00488 * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n 00489 * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n 00490 * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n 00491 * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n 00492 * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n 00493 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n 00494 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n 00495 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n 00496 * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n 00497 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n 00498 * AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n 00499 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n 00500 * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n 00501 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n 00502 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n 00503 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n 00504 * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n 00505 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock 00506 * @param Periphs This parameter can be a combination of the following values: 00507 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00508 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00509 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00510 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00511 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00512 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00513 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00514 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00515 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00516 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00517 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00518 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00519 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) 00520 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) 00521 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00522 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00523 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00524 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00525 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00526 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00527 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00528 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 00529 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00530 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) 00531 * 00532 * (*) value not defined in all devices. 00533 * @retval None 00534 */ 00535 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 00536 { 00537 CLEAR_BIT(RCC->AHB1ENR, Periphs); 00538 } 00539 00540 /** 00541 * @brief Force AHB1 peripherals reset. 00542 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n 00543 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n 00544 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n 00545 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n 00546 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n 00547 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n 00548 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n 00549 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n 00550 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n 00551 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n 00552 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n 00553 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n 00554 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n 00555 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n 00556 * AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n 00557 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n 00558 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n 00559 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset 00560 * @param Periphs This parameter can be a combination of the following values: 00561 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00562 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00563 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00564 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00565 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00566 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00567 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00568 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00569 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00570 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00571 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00572 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00573 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00574 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00575 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00576 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00577 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00578 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00579 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00580 * 00581 * (*) value not defined in all devices. 00582 * @retval None 00583 */ 00584 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 00585 { 00586 SET_BIT(RCC->AHB1RSTR, Periphs); 00587 } 00588 00589 /** 00590 * @brief Release AHB1 peripherals reset. 00591 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n 00592 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n 00593 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n 00594 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n 00595 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n 00596 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n 00597 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n 00598 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n 00599 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n 00600 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n 00601 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n 00602 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n 00603 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n 00604 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n 00605 * AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n 00606 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n 00607 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n 00608 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset 00609 * @param Periphs This parameter can be a combination of the following values: 00610 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00611 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00612 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00613 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00614 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00615 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00616 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00617 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00618 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00619 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00620 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00621 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00622 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00623 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00624 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00625 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00626 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00627 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00628 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00629 * 00630 * (*) value not defined in all devices. 00631 * @retval None 00632 */ 00633 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 00634 { 00635 CLEAR_BIT(RCC->AHB1RSTR, Periphs); 00636 } 00637 00638 /** 00639 * @brief Enable AHB1 peripheral clocks in low-power mode 00640 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n 00641 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00642 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00643 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00644 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n 00645 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00646 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00647 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00648 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n 00649 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00650 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00651 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00652 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00653 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00654 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n 00655 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n 00656 * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n 00657 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00658 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n 00659 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n 00660 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00661 * AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00662 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00663 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00664 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00665 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00666 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00667 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower 00668 * @param Periphs This parameter can be a combination of the following values: 00669 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00670 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00671 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00672 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00673 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00674 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00675 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00676 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00677 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00678 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00679 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00680 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00681 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) 00682 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF 00683 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 00684 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) 00685 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) 00686 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00687 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00688 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00689 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00690 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00691 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00692 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00693 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 00694 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00695 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) 00696 * 00697 * (*) value not defined in all devices. 00698 * @retval None 00699 */ 00700 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) 00701 { 00702 __IO uint32_t tmpreg; 00703 SET_BIT(RCC->AHB1LPENR, Periphs); 00704 /* Delay after an RCC peripheral clock enabling */ 00705 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); 00706 (void)tmpreg; 00707 } 00708 00709 /** 00710 * @brief Disable AHB1 peripheral clocks in low-power mode 00711 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n 00712 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00713 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00714 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00715 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n 00716 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00717 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00718 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00719 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n 00720 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00721 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00722 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00723 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00724 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00725 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n 00726 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n 00727 * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n 00728 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00729 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n 00730 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n 00731 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00732 * AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00733 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00734 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00735 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00736 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00737 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00738 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower 00739 * @param Periphs This parameter can be a combination of the following values: 00740 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00741 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00742 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00743 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00744 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00745 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00746 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00747 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00748 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00749 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00750 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00751 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00752 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) 00753 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF 00754 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 00755 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) 00756 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) 00757 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00758 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00759 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00760 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00761 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00762 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00763 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00764 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 00765 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00766 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) 00767 * 00768 * (*) value not defined in all devices. 00769 * @retval None 00770 */ 00771 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) 00772 { 00773 CLEAR_BIT(RCC->AHB1LPENR, Periphs); 00774 } 00775 00776 /** 00777 * @} 00778 */ 00779 00780 #if defined(RCC_AHB2_SUPPORT) 00781 /** @defgroup BUS_LL_EF_AHB2 AHB2 00782 * @{ 00783 */ 00784 00785 /** 00786 * @brief Enable AHB2 peripherals clock. 00787 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n 00788 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n 00789 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n 00790 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n 00791 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n 00792 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock 00793 * @param Periphs This parameter can be a combination of the following values: 00794 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00795 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00796 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00797 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00798 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00799 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00800 * 00801 * (*) value not defined in all devices. 00802 * @retval None 00803 */ 00804 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 00805 { 00806 __IO uint32_t tmpreg; 00807 SET_BIT(RCC->AHB2ENR, Periphs); 00808 /* Delay after an RCC peripheral clock enabling */ 00809 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 00810 (void)tmpreg; 00811 } 00812 00813 /** 00814 * @brief Check if AHB2 peripheral clock is enabled or not 00815 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n 00816 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n 00817 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n 00818 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n 00819 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n 00820 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock 00821 * @param Periphs This parameter can be a combination of the following values: 00822 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00823 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00824 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00825 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00826 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00827 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00828 * 00829 * (*) value not defined in all devices. 00830 * @retval State of Periphs (1 or 0). 00831 */ 00832 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 00833 { 00834 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); 00835 } 00836 00837 /** 00838 * @brief Disable AHB2 peripherals clock. 00839 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n 00840 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n 00841 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n 00842 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n 00843 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n 00844 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock 00845 * @param Periphs This parameter can be a combination of the following values: 00846 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00847 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00848 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00849 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00850 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00851 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00852 * 00853 * (*) value not defined in all devices. 00854 * @retval None 00855 */ 00856 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) 00857 { 00858 CLEAR_BIT(RCC->AHB2ENR, Periphs); 00859 } 00860 00861 /** 00862 * @brief Force AHB2 peripherals reset. 00863 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n 00864 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n 00865 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n 00866 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n 00867 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n 00868 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset 00869 * @param Periphs This parameter can be a combination of the following values: 00870 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00871 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00872 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00873 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00874 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00875 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00876 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00877 * 00878 * (*) value not defined in all devices. 00879 * @retval None 00880 */ 00881 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) 00882 { 00883 SET_BIT(RCC->AHB2RSTR, Periphs); 00884 } 00885 00886 /** 00887 * @brief Release AHB2 peripherals reset. 00888 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n 00889 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n 00890 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n 00891 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n 00892 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n 00893 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset 00894 * @param Periphs This parameter can be a combination of the following values: 00895 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00896 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00897 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00898 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00899 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00900 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00901 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00902 * 00903 * (*) value not defined in all devices. 00904 * @retval None 00905 */ 00906 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) 00907 { 00908 CLEAR_BIT(RCC->AHB2RSTR, Periphs); 00909 } 00910 00911 /** 00912 * @brief Enable AHB2 peripheral clocks in low-power mode 00913 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n 00914 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n 00915 * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n 00916 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n 00917 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n 00918 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower 00919 * @param Periphs This parameter can be a combination of the following values: 00920 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00921 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00922 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00923 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00924 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00925 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00926 * 00927 * (*) value not defined in all devices. 00928 * @retval None 00929 */ 00930 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) 00931 { 00932 __IO uint32_t tmpreg; 00933 SET_BIT(RCC->AHB2LPENR, Periphs); 00934 /* Delay after an RCC peripheral clock enabling */ 00935 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); 00936 (void)tmpreg; 00937 } 00938 00939 /** 00940 * @brief Disable AHB2 peripheral clocks in low-power mode 00941 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n 00942 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n 00943 * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n 00944 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n 00945 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n 00946 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower 00947 * @param Periphs This parameter can be a combination of the following values: 00948 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00949 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00950 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00951 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00952 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00953 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00954 * 00955 * (*) value not defined in all devices. 00956 * @retval None 00957 */ 00958 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) 00959 { 00960 CLEAR_BIT(RCC->AHB2LPENR, Periphs); 00961 } 00962 00963 /** 00964 * @} 00965 */ 00966 #endif /* RCC_AHB2_SUPPORT */ 00967 00968 #if defined(RCC_AHB3_SUPPORT) 00969 /** @defgroup BUS_LL_EF_AHB3 AHB3 00970 * @{ 00971 */ 00972 00973 /** 00974 * @brief Enable AHB3 peripherals clock. 00975 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n 00976 * AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n 00977 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock 00978 * @param Periphs This parameter can be a combination of the following values: 00979 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00980 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 00981 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00982 * 00983 * (*) value not defined in all devices. 00984 * @retval None 00985 */ 00986 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) 00987 { 00988 __IO uint32_t tmpreg; 00989 SET_BIT(RCC->AHB3ENR, Periphs); 00990 /* Delay after an RCC peripheral clock enabling */ 00991 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 00992 (void)tmpreg; 00993 } 00994 00995 /** 00996 * @brief Check if AHB3 peripheral clock is enabled or not 00997 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n 00998 * AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n 00999 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock 01000 * @param Periphs This parameter can be a combination of the following values: 01001 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01002 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 01003 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01004 * 01005 * (*) value not defined in all devices. 01006 * @retval State of Periphs (1 or 0). 01007 */ 01008 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 01009 { 01010 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); 01011 } 01012 01013 /** 01014 * @brief Disable AHB3 peripherals clock. 01015 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n 01016 * AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n 01017 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock 01018 * @param Periphs This parameter can be a combination of the following values: 01019 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01020 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 01021 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01022 * 01023 * (*) value not defined in all devices. 01024 * @retval None 01025 */ 01026 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) 01027 { 01028 CLEAR_BIT(RCC->AHB3ENR, Periphs); 01029 } 01030 01031 /** 01032 * @brief Force AHB3 peripherals reset. 01033 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n 01034 * AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n 01035 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset 01036 * @param Periphs This parameter can be a combination of the following values: 01037 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL 01038 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01039 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 01040 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01041 * 01042 * (*) value not defined in all devices. 01043 * @retval None 01044 */ 01045 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) 01046 { 01047 SET_BIT(RCC->AHB3RSTR, Periphs); 01048 } 01049 01050 /** 01051 * @brief Release AHB3 peripherals reset. 01052 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n 01053 * AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n 01054 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset 01055 * @param Periphs This parameter can be a combination of the following values: 01056 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 01057 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01058 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 01059 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01060 * 01061 * (*) value not defined in all devices. 01062 * @retval None 01063 */ 01064 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) 01065 { 01066 CLEAR_BIT(RCC->AHB3RSTR, Periphs); 01067 } 01068 01069 /** 01070 * @brief Enable AHB3 peripheral clocks in low-power mode 01071 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n 01072 * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n 01073 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower 01074 * @param Periphs This parameter can be a combination of the following values: 01075 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01076 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 01077 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01078 * 01079 * (*) value not defined in all devices. 01080 * @retval None 01081 */ 01082 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) 01083 { 01084 __IO uint32_t tmpreg; 01085 SET_BIT(RCC->AHB3LPENR, Periphs); 01086 /* Delay after an RCC peripheral clock enabling */ 01087 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); 01088 (void)tmpreg; 01089 } 01090 01091 /** 01092 * @brief Disable AHB3 peripheral clocks in low-power mode 01093 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n 01094 * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n 01095 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower 01096 * @param Periphs This parameter can be a combination of the following values: 01097 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01098 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 01099 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01100 * 01101 * (*) value not defined in all devices. 01102 * @retval None 01103 */ 01104 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) 01105 { 01106 CLEAR_BIT(RCC->AHB3LPENR, Periphs); 01107 } 01108 01109 /** 01110 * @} 01111 */ 01112 #endif /* RCC_AHB3_SUPPORT */ 01113 01114 /** @defgroup BUS_LL_EF_APB1 APB1 01115 * @{ 01116 */ 01117 01118 /** 01119 * @brief Enable APB1 peripherals clock. 01120 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n 01121 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n 01122 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n 01123 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n 01124 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n 01125 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n 01126 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n 01127 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n 01128 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n 01129 * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n 01130 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n 01131 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n 01132 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n 01133 * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n 01134 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n 01135 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n 01136 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n 01137 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n 01138 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n 01139 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n 01140 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n 01141 * APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n 01142 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n 01143 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n 01144 * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n 01145 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n 01146 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n 01147 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n 01148 * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n 01149 * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n 01150 * APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock 01151 * @param Periphs This parameter can be a combination of the following values: 01152 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01153 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01154 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01155 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01156 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01157 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01158 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01159 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01160 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01161 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01162 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01163 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01164 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01165 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01166 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01167 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01168 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01169 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01170 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01171 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01172 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01173 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01174 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01175 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01176 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01177 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01178 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01179 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01180 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01181 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01182 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01183 * 01184 * (*) value not defined in all devices. 01185 * @retval None 01186 */ 01187 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 01188 { 01189 __IO uint32_t tmpreg; 01190 SET_BIT(RCC->APB1ENR, Periphs); 01191 /* Delay after an RCC peripheral clock enabling */ 01192 tmpreg = READ_BIT(RCC->APB1ENR, Periphs); 01193 (void)tmpreg; 01194 } 01195 01196 /** 01197 * @brief Check if APB1 peripheral clock is enabled or not 01198 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n 01199 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n 01200 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n 01201 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n 01202 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n 01203 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n 01204 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n 01205 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n 01206 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n 01207 * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n 01208 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n 01209 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n 01210 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n 01211 * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n 01212 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n 01213 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n 01214 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n 01215 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n 01216 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n 01217 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n 01218 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n 01219 * APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n 01220 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n 01221 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n 01222 * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n 01223 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n 01224 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n 01225 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n 01226 * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n 01227 * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n 01228 * APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock 01229 * @param Periphs This parameter can be a combination of the following values: 01230 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01231 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01232 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01233 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01234 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01235 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01236 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01237 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01238 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01239 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01240 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01241 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01242 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01243 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01244 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01245 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01246 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01247 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01248 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01249 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01250 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01251 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01252 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01253 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01254 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01255 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01256 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01257 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01258 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01259 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01260 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01261 * 01262 * (*) value not defined in all devices. 01263 * @retval State of Periphs (1 or 0). 01264 */ 01265 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 01266 { 01267 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); 01268 } 01269 01270 /** 01271 * @brief Disable APB1 peripherals clock. 01272 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n 01273 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n 01274 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n 01275 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n 01276 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n 01277 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n 01278 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n 01279 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n 01280 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n 01281 * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n 01282 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n 01283 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n 01284 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n 01285 * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n 01286 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n 01287 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n 01288 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n 01289 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n 01290 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n 01291 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n 01292 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n 01293 * APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n 01294 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n 01295 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n 01296 * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n 01297 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n 01298 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n 01299 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n 01300 * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n 01301 * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n 01302 * APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock 01303 * @param Periphs This parameter can be a combination of the following values: 01304 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01305 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01306 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01307 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01308 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01309 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01310 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01311 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01312 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01313 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01314 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01315 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01316 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01317 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01318 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01319 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01320 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01321 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01322 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01323 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01324 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01325 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01326 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01327 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01328 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01329 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01330 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01331 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01332 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01333 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01334 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01335 * 01336 * (*) value not defined in all devices. 01337 * @retval None 01338 */ 01339 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 01340 { 01341 CLEAR_BIT(RCC->APB1ENR, Periphs); 01342 } 01343 01344 /** 01345 * @brief Force APB1 peripherals reset. 01346 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n 01347 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n 01348 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n 01349 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n 01350 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n 01351 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n 01352 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n 01353 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n 01354 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n 01355 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n 01356 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n 01357 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n 01358 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n 01359 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n 01360 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n 01361 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n 01362 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n 01363 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n 01364 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n 01365 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n 01366 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n 01367 * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n 01368 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n 01369 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n 01370 * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n 01371 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n 01372 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n 01373 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n 01374 * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n 01375 * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset 01376 * @param Periphs This parameter can be a combination of the following values: 01377 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01378 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01379 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01380 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01381 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01382 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01383 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01384 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01385 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01386 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01387 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01388 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01389 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01390 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01391 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01392 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01393 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01394 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01395 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01396 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01397 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01398 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01399 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01400 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01401 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01402 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01403 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01404 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01405 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01406 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01407 * 01408 * (*) value not defined in all devices. 01409 * @retval None 01410 */ 01411 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 01412 { 01413 SET_BIT(RCC->APB1RSTR, Periphs); 01414 } 01415 01416 /** 01417 * @brief Release APB1 peripherals reset. 01418 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n 01419 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n 01420 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n 01421 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n 01422 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n 01423 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n 01424 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n 01425 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n 01426 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n 01427 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n 01428 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n 01429 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n 01430 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n 01431 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n 01432 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n 01433 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n 01434 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n 01435 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n 01436 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n 01437 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n 01438 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n 01439 * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n 01440 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n 01441 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n 01442 * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n 01443 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n 01444 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n 01445 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n 01446 * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n 01447 * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset 01448 * @param Periphs This parameter can be a combination of the following values: 01449 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01450 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01451 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01452 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01453 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01454 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01455 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01456 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01457 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01458 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01459 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01460 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01461 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01462 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01463 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01464 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01465 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01466 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01467 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01468 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01469 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01470 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01471 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01472 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01473 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01474 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01475 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01476 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01477 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01478 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01479 * 01480 * (*) value not defined in all devices. 01481 * @retval None 01482 */ 01483 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 01484 { 01485 CLEAR_BIT(RCC->APB1RSTR, Periphs); 01486 } 01487 01488 /** 01489 * @brief Enable APB1 peripheral clocks in low-power mode 01490 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n 01491 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n 01492 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n 01493 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n 01494 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n 01495 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n 01496 * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n 01497 * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n 01498 * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n 01499 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n 01500 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n 01501 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n 01502 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n 01503 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n 01504 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n 01505 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n 01506 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n 01507 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n 01508 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n 01509 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n 01510 * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n 01511 * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n 01512 * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n 01513 * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n 01514 * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n 01515 * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n 01516 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n 01517 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n 01518 * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n 01519 * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n 01520 * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower 01521 * @param Periphs This parameter can be a combination of the following values: 01522 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01523 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01524 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01525 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01526 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01527 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01528 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01529 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01530 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01531 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01532 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01533 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01534 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01535 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01536 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01537 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01538 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01539 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01540 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01541 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01542 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01543 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01544 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01545 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01546 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01547 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01548 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01549 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01550 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01551 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01552 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01553 * 01554 * (*) value not defined in all devices. 01555 * @retval None 01556 */ 01557 __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) 01558 { 01559 __IO uint32_t tmpreg; 01560 SET_BIT(RCC->APB1LPENR, Periphs); 01561 /* Delay after an RCC peripheral clock enabling */ 01562 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); 01563 (void)tmpreg; 01564 } 01565 01566 /** 01567 * @brief Disable APB1 peripheral clocks in low-power mode 01568 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n 01569 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n 01570 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n 01571 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n 01572 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n 01573 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n 01574 * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n 01575 * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n 01576 * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n 01577 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n 01578 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n 01579 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n 01580 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n 01581 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n 01582 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n 01583 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n 01584 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n 01585 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n 01586 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n 01587 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n 01588 * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n 01589 * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n 01590 * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n 01591 * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n 01592 * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n 01593 * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n 01594 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n 01595 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n 01596 * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n 01597 * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n 01598 * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower 01599 * @param Periphs This parameter can be a combination of the following values: 01600 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01601 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01602 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01603 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01604 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01605 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01606 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01607 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01608 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01609 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01610 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01611 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01612 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01613 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01614 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01615 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01616 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01617 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01618 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01619 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01620 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01621 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01622 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01623 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01624 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01625 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01626 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01627 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01628 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01629 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01630 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01631 * 01632 * (*) value not defined in all devices. 01633 * @retval None 01634 */ 01635 __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) 01636 { 01637 CLEAR_BIT(RCC->APB1LPENR, Periphs); 01638 } 01639 01640 /** 01641 * @} 01642 */ 01643 01644 /** @defgroup BUS_LL_EF_APB2 APB2 01645 * @{ 01646 */ 01647 01648 /** 01649 * @brief Enable APB2 peripherals clock. 01650 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 01651 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 01652 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n 01653 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n 01654 * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n 01655 * APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n 01656 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n 01657 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n 01658 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n 01659 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n 01660 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 01661 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n 01662 * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n 01663 * APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n 01664 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n 01665 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n 01666 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n 01667 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n 01668 * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n 01669 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n 01670 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n 01671 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n 01672 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n 01673 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n 01674 * APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock 01675 * @param Periphs This parameter can be a combination of the following values: 01676 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01677 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01678 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01679 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 01680 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 01681 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 01682 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 01683 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 01684 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 01685 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 01686 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01687 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 01688 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01689 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) 01690 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 01691 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 01692 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 01693 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 01694 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 01695 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 01696 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01697 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01698 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01699 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01700 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 01701 01702 * 01703 * (*) value not defined in all devices. 01704 * @retval None 01705 */ 01706 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 01707 { 01708 __IO uint32_t tmpreg; 01709 SET_BIT(RCC->APB2ENR, Periphs); 01710 /* Delay after an RCC peripheral clock enabling */ 01711 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 01712 (void)tmpreg; 01713 } 01714 01715 /** 01716 * @brief Check if APB2 peripheral clock is enabled or not 01717 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n 01718 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n 01719 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n 01720 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n 01721 * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n 01722 * APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n 01723 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n 01724 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n 01725 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n 01726 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n 01727 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n 01728 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n 01729 * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n 01730 * APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n 01731 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n 01732 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n 01733 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n 01734 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n 01735 * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n 01736 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n 01737 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n 01738 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n 01739 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n 01740 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n 01741 * APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock 01742 * @param Periphs This parameter can be a combination of the following values: 01743 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01744 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01745 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01746 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 01747 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 01748 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 01749 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 01750 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 01751 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 01752 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 01753 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01754 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 01755 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01756 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) 01757 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 01758 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 01759 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 01760 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 01761 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 01762 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 01763 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01764 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01765 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01766 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01767 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 01768 * 01769 * (*) value not defined in all devices. 01770 * @retval State of Periphs (1 or 0). 01771 */ 01772 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 01773 { 01774 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); 01775 } 01776 01777 /** 01778 * @brief Disable APB2 peripherals clock. 01779 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n 01780 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n 01781 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n 01782 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n 01783 * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n 01784 * APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n 01785 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n 01786 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n 01787 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n 01788 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n 01789 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n 01790 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n 01791 * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n 01792 * APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n 01793 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n 01794 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n 01795 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n 01796 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n 01797 * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n 01798 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n 01799 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n 01800 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n 01801 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n 01802 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n 01803 * APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock 01804 * @param Periphs This parameter can be a combination of the following values: 01805 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01806 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01807 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01808 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 01809 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 01810 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 01811 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 01812 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 01813 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 01814 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 01815 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01816 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 01817 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01818 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) 01819 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 01820 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 01821 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 01822 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 01823 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 01824 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 01825 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01826 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01827 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01828 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01829 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 01830 * 01831 * (*) value not defined in all devices. 01832 * @retval None 01833 */ 01834 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) 01835 { 01836 CLEAR_BIT(RCC->APB2ENR, Periphs); 01837 } 01838 01839 /** 01840 * @brief Force APB2 peripherals reset. 01841 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n 01842 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n 01843 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n 01844 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n 01845 * APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n 01846 * APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n 01847 * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n 01848 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n 01849 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n 01850 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n 01851 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n 01852 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n 01853 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n 01854 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n 01855 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n 01856 * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n 01857 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n 01858 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n 01859 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n 01860 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n 01861 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n 01862 * APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset 01863 * @param Periphs This parameter can be a combination of the following values: 01864 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 01865 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01866 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01867 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01868 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 01869 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 01870 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 01871 * @arg @ref LL_APB2_GRP1_PERIPH_ADC 01872 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 01873 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01874 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 01875 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01876 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 01877 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 01878 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 01879 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 01880 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 01881 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 01882 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01883 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01884 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01885 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01886 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 01887 * 01888 * (*) value not defined in all devices. 01889 * @retval None 01890 */ 01891 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) 01892 { 01893 SET_BIT(RCC->APB2RSTR, Periphs); 01894 } 01895 01896 /** 01897 * @brief Release APB2 peripherals reset. 01898 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n 01899 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n 01900 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n 01901 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n 01902 * APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n 01903 * APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n 01904 * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n 01905 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n 01906 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n 01907 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n 01908 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n 01909 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n 01910 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n 01911 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n 01912 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n 01913 * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n 01914 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n 01915 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n 01916 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n 01917 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n 01918 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n 01919 * APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset 01920 * @param Periphs This parameter can be a combination of the following values: 01921 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 01922 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01923 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01924 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01925 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 01926 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 01927 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 01928 * @arg @ref LL_APB2_GRP1_PERIPH_ADC 01929 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 01930 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01931 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 01932 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01933 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) 01934 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 01935 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 01936 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 01937 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 01938 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 01939 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 01940 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01941 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01942 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01943 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01944 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 01945 * 01946 * (*) value not defined in all devices. 01947 * @retval None 01948 */ 01949 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) 01950 { 01951 CLEAR_BIT(RCC->APB2RSTR, Periphs); 01952 } 01953 01954 /** 01955 * @brief Enable APB2 peripheral clocks in low-power mode 01956 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n 01957 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n 01958 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n 01959 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n 01960 * APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n 01961 * APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n 01962 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n 01963 * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n 01964 * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n 01965 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n 01966 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n 01967 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n 01968 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n 01969 * APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n 01970 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n 01971 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n 01972 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n 01973 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n 01974 * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n 01975 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n 01976 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n 01977 * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n 01978 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n 01979 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n 01980 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n 01981 * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower 01982 * @param Periphs This parameter can be a combination of the following values: 01983 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01984 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01985 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01986 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 01987 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 01988 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 01989 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 01990 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 01991 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 01992 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 01993 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01994 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 01995 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01996 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) 01997 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 01998 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 01999 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 02000 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 02001 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 02002 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 02003 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 02004 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 02005 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 02006 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 02007 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 02008 * 02009 * (*) value not defined in all devices. 02010 * @retval None 02011 */ 02012 __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) 02013 { 02014 __IO uint32_t tmpreg; 02015 SET_BIT(RCC->APB2LPENR, Periphs); 02016 /* Delay after an RCC peripheral clock enabling */ 02017 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); 02018 (void)tmpreg; 02019 } 02020 02021 /** 02022 * @brief Disable APB2 peripheral clocks in low-power mode 02023 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n 02024 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n 02025 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n 02026 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n 02027 * APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n 02028 * APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n 02029 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n 02030 * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n 02031 * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n 02032 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n 02033 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n 02034 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n 02035 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n 02036 * APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n 02037 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n 02038 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n 02039 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n 02040 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n 02041 * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n 02042 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n 02043 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n 02044 * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n 02045 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n 02046 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n 02047 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n 02048 * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower 02049 * @param Periphs This parameter can be a combination of the following values: 02050 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 02051 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 02052 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 02053 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 02054 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 02055 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 02056 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 02057 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 02058 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 02059 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 02060 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 02061 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 02062 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 02063 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) 02064 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 02065 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 02066 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 02067 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 02068 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 02069 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 02070 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 02071 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 02072 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 02073 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 02074 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 02075 * 02076 * (*) value not defined in all devices. 02077 * @retval None 02078 */ 02079 __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) 02080 { 02081 CLEAR_BIT(RCC->APB2LPENR, Periphs); 02082 } 02083 02084 /** 02085 * @} 02086 */ 02087 02088 /** 02089 * @} 02090 */ 02091 02092 /** 02093 * @} 02094 */ 02095 02096 #endif /* defined(RCC) */ 02097 02098 /** 02099 * @} 02100 */ 02101 02102 #ifdef __cplusplus 02103 } 02104 #endif 02105 02106 #endif /* __STM32F4xx_LL_BUS_H */ 02107 02108 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1