STM32F479xx HAL User Manual: stm32f4xx_ll

Header file of CORTEX LL module. More...

#include "stm32f4xx.h"

Defines
#define	LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define	LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk
#define	LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define	LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define	LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk
#define	LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U
#define	LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define	LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define	LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk \| MPU_CTRL_PRIVDEFENA_Msk)
#define	LL_MPU_REGION_NUMBER0 0x00U
#define	LL_MPU_REGION_NUMBER1 0x01U
#define	LL_MPU_REGION_NUMBER2 0x02U
#define	LL_MPU_REGION_NUMBER3 0x03U
#define	LL_MPU_REGION_NUMBER4 0x04U
#define	LL_MPU_REGION_NUMBER5 0x05U
#define	LL_MPU_REGION_NUMBER6 0x06U
#define	LL_MPU_REGION_NUMBER7 0x07U
#define	LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)
#define	LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)
#define	LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)
#define	LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)
#define	LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)
#define	LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)
#define	LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)
#define	LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)
#define	LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)
#define	LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)
#define	LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)
#define	LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U
#define	LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk
#define	LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define	LL_MPU_ACCESS_NOT_SHAREABLE 0x00U
#define	LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define	LL_MPU_ACCESS_NOT_CACHEABLE 0x00U
#define	LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define	LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U
Functions
__STATIC_INLINE uint32_t	LL_SYSTICK_IsActiveCounterFlag (void)
	This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void	LL_SYSTICK_SetClkSource (uint32_t Source)
	Configures the SysTick clock source.
__STATIC_INLINE uint32_t	LL_SYSTICK_GetClkSource (void)
	Get the SysTick clock source.
__STATIC_INLINE void	LL_SYSTICK_EnableIT (void)
	Enable SysTick exception request.
__STATIC_INLINE void	LL_SYSTICK_DisableIT (void)
	Disable SysTick exception request.
__STATIC_INLINE uint32_t	LL_SYSTICK_IsEnabledIT (void)
	Checks if the SYSTICK interrupt is enabled or disabled.
__STATIC_INLINE void	LL_LPM_EnableSleep (void)
	Processor uses sleep as its low power mode.
__STATIC_INLINE void	LL_LPM_EnableDeepSleep (void)
	Processor uses deep sleep as its low power mode.
__STATIC_INLINE void	LL_LPM_EnableSleepOnExit (void)
	Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void	LL_LPM_DisableSleepOnExit (void)
	Do not sleep when returning to Thread mode.
__STATIC_INLINE void	LL_LPM_EnableEventOnPend (void)
	Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void	LL_LPM_DisableEventOnPend (void)
	Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
__STATIC_INLINE void	LL_HANDLER_EnableFault (uint32_t Fault)
	Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void	LL_HANDLER_DisableFault (uint32_t Fault)
	Disable a fault in System handler control register (SHCSR)
__STATIC_INLINE uint32_t	LL_CPUID_GetImplementer (void)
	Get Implementer code.
__STATIC_INLINE uint32_t	LL_CPUID_GetVariant (void)
	Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t	LL_CPUID_GetConstant (void)
	Get Constant number.
__STATIC_INLINE uint32_t	LL_CPUID_GetParNo (void)
	Get Part number.
__STATIC_INLINE uint32_t	LL_CPUID_GetRevision (void)
	Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
__STATIC_INLINE void	LL_MPU_Enable (uint32_t Options)
	Enable MPU with input options.
__STATIC_INLINE void	LL_MPU_Disable (void)
	Disable MPU.
__STATIC_INLINE uint32_t	LL_MPU_IsEnabled (void)
	Check if MPU is enabled or not.
__STATIC_INLINE void	LL_MPU_EnableRegion (uint32_t Region)
	Enable a MPU region.
__STATIC_INLINE void	LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
	Configure and enable a region.
__STATIC_INLINE void	LL_MPU_DisableRegion (uint32_t Region)
	Disable a region.

Detailed Description

Header file of CORTEX LL module.

Author:

MCD Application Team

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL CORTEX driver contains a set of generic APIs that can be
    used by user:
      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
          functions
      (+) Low power mode configuration (SCB register of Cortex-MCU)
      (+) MPU API to configure and enable regions
          (MPU services provided only on some devices)
      (+) API to access to MCU info (CPUID register)
      (+) API to enable fault handler (SHCSR accesses)

Attention:

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32f4xx_ll_cortex.h.

Defines

Functions

Detailed Description

© Copyright (c) 2017 STMicroelectronics. All rights reserved.