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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_cortex.h 00004 * @author MCD Application Team 00005 * @brief Header file of CORTEX LL module. 00006 @verbatim 00007 ============================================================================== 00008 ##### How to use this driver ##### 00009 ============================================================================== 00010 [..] 00011 The LL CORTEX driver contains a set of generic APIs that can be 00012 used by user: 00013 (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick 00014 functions 00015 (+) Low power mode configuration (SCB register of Cortex-MCU) 00016 (+) MPU API to configure and enable regions 00017 (MPU services provided only on some devices) 00018 (+) API to access to MCU info (CPUID register) 00019 (+) API to enable fault handler (SHCSR accesses) 00020 00021 @endverbatim 00022 ****************************************************************************** 00023 * @attention 00024 * 00025 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00026 * All rights reserved.</center></h2> 00027 * 00028 * This software component is licensed by ST under BSD 3-Clause license, 00029 * the "License"; You may not use this file except in compliance with the 00030 * License. You may obtain a copy of the License at: 00031 * opensource.org/licenses/BSD-3-Clause 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_LL_CORTEX_H 00038 #define __STM32F4xx_LL_CORTEX_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx.h" 00046 00047 /** @addtogroup STM32F4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 /** @defgroup CORTEX_LL CORTEX 00052 * @{ 00053 */ 00054 00055 /* Private types -------------------------------------------------------------*/ 00056 /* Private variables ---------------------------------------------------------*/ 00057 00058 /* Private constants ---------------------------------------------------------*/ 00059 00060 /* Private macros ------------------------------------------------------------*/ 00061 00062 /* Exported types ------------------------------------------------------------*/ 00063 /* Exported constants --------------------------------------------------------*/ 00064 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants 00065 * @{ 00066 */ 00067 00068 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source 00069 * @{ 00070 */ 00071 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ 00072 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ 00073 /** 00074 * @} 00075 */ 00076 00077 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type 00078 * @{ 00079 */ 00080 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ 00081 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ 00082 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ 00083 /** 00084 * @} 00085 */ 00086 00087 #if __MPU_PRESENT 00088 00089 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control 00090 * @{ 00091 */ 00092 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ 00093 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ 00094 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ 00095 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ 00096 /** 00097 * @} 00098 */ 00099 00100 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number 00101 * @{ 00102 */ 00103 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ 00104 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ 00105 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ 00106 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ 00107 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ 00108 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ 00109 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ 00110 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ 00111 /** 00112 * @} 00113 */ 00114 00115 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size 00116 * @{ 00117 */ 00118 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ 00119 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ 00120 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ 00121 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ 00122 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ 00123 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ 00124 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ 00125 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ 00126 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ 00127 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ 00128 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ 00129 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ 00130 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ 00131 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ 00132 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ 00133 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ 00134 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ 00135 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ 00136 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ 00137 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ 00138 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ 00139 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ 00140 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ 00141 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ 00142 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ 00143 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ 00144 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ 00145 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ 00146 /** 00147 * @} 00148 */ 00149 00150 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges 00151 * @{ 00152 */ 00153 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ 00154 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ 00155 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ 00156 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ 00157 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ 00158 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ 00159 /** 00160 * @} 00161 */ 00162 00163 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level 00164 * @{ 00165 */ 00166 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ 00167 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ 00168 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ 00169 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ 00170 /** 00171 * @} 00172 */ 00173 00174 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access 00175 * @{ 00176 */ 00177 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ 00178 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ 00179 /** 00180 * @} 00181 */ 00182 00183 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access 00184 * @{ 00185 */ 00186 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ 00187 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ 00188 /** 00189 * @} 00190 */ 00191 00192 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access 00193 * @{ 00194 */ 00195 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ 00196 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ 00197 /** 00198 * @} 00199 */ 00200 00201 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access 00202 * @{ 00203 */ 00204 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ 00205 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ 00206 /** 00207 * @} 00208 */ 00209 #endif /* __MPU_PRESENT */ 00210 /** 00211 * @} 00212 */ 00213 00214 /* Exported macro ------------------------------------------------------------*/ 00215 00216 /* Exported functions --------------------------------------------------------*/ 00217 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions 00218 * @{ 00219 */ 00220 00221 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK 00222 * @{ 00223 */ 00224 00225 /** 00226 * @brief This function checks if the Systick counter flag is active or not. 00227 * @note It can be used in timeout function on application side. 00228 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag 00229 * @retval State of bit (1 or 0). 00230 */ 00231 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) 00232 { 00233 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); 00234 } 00235 00236 /** 00237 * @brief Configures the SysTick clock source 00238 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource 00239 * @param Source This parameter can be one of the following values: 00240 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 00241 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK 00242 * @retval None 00243 */ 00244 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) 00245 { 00246 if (Source == LL_SYSTICK_CLKSOURCE_HCLK) 00247 { 00248 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 00249 } 00250 else 00251 { 00252 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 00253 } 00254 } 00255 00256 /** 00257 * @brief Get the SysTick clock source 00258 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource 00259 * @retval Returned value can be one of the following values: 00260 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 00261 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK 00262 */ 00263 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) 00264 { 00265 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 00266 } 00267 00268 /** 00269 * @brief Enable SysTick exception request 00270 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT 00271 * @retval None 00272 */ 00273 __STATIC_INLINE void LL_SYSTICK_EnableIT(void) 00274 { 00275 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 00276 } 00277 00278 /** 00279 * @brief Disable SysTick exception request 00280 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT 00281 * @retval None 00282 */ 00283 __STATIC_INLINE void LL_SYSTICK_DisableIT(void) 00284 { 00285 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 00286 } 00287 00288 /** 00289 * @brief Checks if the SYSTICK interrupt is enabled or disabled. 00290 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT 00291 * @retval State of bit (1 or 0). 00292 */ 00293 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) 00294 { 00295 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); 00296 } 00297 00298 /** 00299 * @} 00300 */ 00301 00302 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE 00303 * @{ 00304 */ 00305 00306 /** 00307 * @brief Processor uses sleep as its low power mode 00308 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep 00309 * @retval None 00310 */ 00311 __STATIC_INLINE void LL_LPM_EnableSleep(void) 00312 { 00313 /* Clear SLEEPDEEP bit of Cortex System Control Register */ 00314 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00315 } 00316 00317 /** 00318 * @brief Processor uses deep sleep as its low power mode 00319 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep 00320 * @retval None 00321 */ 00322 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) 00323 { 00324 /* Set SLEEPDEEP bit of Cortex System Control Register */ 00325 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00326 } 00327 00328 /** 00329 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. 00330 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an 00331 * empty main application. 00332 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit 00333 * @retval None 00334 */ 00335 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) 00336 { 00337 /* Set SLEEPONEXIT bit of Cortex System Control Register */ 00338 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 00339 } 00340 00341 /** 00342 * @brief Do not sleep when returning to Thread mode. 00343 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit 00344 * @retval None 00345 */ 00346 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) 00347 { 00348 /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 00349 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 00350 } 00351 00352 /** 00353 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the 00354 * processor. 00355 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend 00356 * @retval None 00357 */ 00358 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) 00359 { 00360 /* Set SEVEONPEND bit of Cortex System Control Register */ 00361 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 00362 } 00363 00364 /** 00365 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are 00366 * excluded 00367 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend 00368 * @retval None 00369 */ 00370 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) 00371 { 00372 /* Clear SEVEONPEND bit of Cortex System Control Register */ 00373 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 00374 } 00375 00376 /** 00377 * @} 00378 */ 00379 00380 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER 00381 * @{ 00382 */ 00383 00384 /** 00385 * @brief Enable a fault in System handler control register (SHCSR) 00386 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault 00387 * @param Fault This parameter can be a combination of the following values: 00388 * @arg @ref LL_HANDLER_FAULT_USG 00389 * @arg @ref LL_HANDLER_FAULT_BUS 00390 * @arg @ref LL_HANDLER_FAULT_MEM 00391 * @retval None 00392 */ 00393 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) 00394 { 00395 /* Enable the system handler fault */ 00396 SET_BIT(SCB->SHCSR, Fault); 00397 } 00398 00399 /** 00400 * @brief Disable a fault in System handler control register (SHCSR) 00401 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault 00402 * @param Fault This parameter can be a combination of the following values: 00403 * @arg @ref LL_HANDLER_FAULT_USG 00404 * @arg @ref LL_HANDLER_FAULT_BUS 00405 * @arg @ref LL_HANDLER_FAULT_MEM 00406 * @retval None 00407 */ 00408 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) 00409 { 00410 /* Disable the system handler fault */ 00411 CLEAR_BIT(SCB->SHCSR, Fault); 00412 } 00413 00414 /** 00415 * @} 00416 */ 00417 00418 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO 00419 * @{ 00420 */ 00421 00422 /** 00423 * @brief Get Implementer code 00424 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer 00425 * @retval Value should be equal to 0x41 for ARM 00426 */ 00427 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) 00428 { 00429 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); 00430 } 00431 00432 /** 00433 * @brief Get Variant number (The r value in the rnpn product revision identifier) 00434 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant 00435 * @retval Value between 0 and 255 (0x0: revision 0) 00436 */ 00437 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) 00438 { 00439 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); 00440 } 00441 00442 /** 00443 * @brief Get Constant number 00444 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant 00445 * @retval Value should be equal to 0xF for Cortex-M4 devices 00446 */ 00447 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) 00448 { 00449 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); 00450 } 00451 00452 /** 00453 * @brief Get Part number 00454 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo 00455 * @retval Value should be equal to 0xC24 for Cortex-M4 00456 */ 00457 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) 00458 { 00459 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); 00460 } 00461 00462 /** 00463 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) 00464 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision 00465 * @retval Value between 0 and 255 (0x1: patch 1) 00466 */ 00467 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) 00468 { 00469 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); 00470 } 00471 00472 /** 00473 * @} 00474 */ 00475 00476 #if __MPU_PRESENT 00477 /** @defgroup CORTEX_LL_EF_MPU MPU 00478 * @{ 00479 */ 00480 00481 /** 00482 * @brief Enable MPU with input options 00483 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable 00484 * @param Options This parameter can be one of the following values: 00485 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 00486 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI 00487 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT 00488 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF 00489 * @retval None 00490 */ 00491 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) 00492 { 00493 /* Enable the MPU*/ 00494 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); 00495 /* Ensure MPU settings take effects */ 00496 __DSB(); 00497 /* Sequence instruction fetches using update settings */ 00498 __ISB(); 00499 } 00500 00501 /** 00502 * @brief Disable MPU 00503 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable 00504 * @retval None 00505 */ 00506 __STATIC_INLINE void LL_MPU_Disable(void) 00507 { 00508 /* Make sure outstanding transfers are done */ 00509 __DMB(); 00510 /* Disable MPU*/ 00511 WRITE_REG(MPU->CTRL, 0U); 00512 } 00513 00514 /** 00515 * @brief Check if MPU is enabled or not 00516 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled 00517 * @retval State of bit (1 or 0). 00518 */ 00519 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) 00520 { 00521 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); 00522 } 00523 00524 /** 00525 * @brief Enable a MPU region 00526 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion 00527 * @param Region This parameter can be one of the following values: 00528 * @arg @ref LL_MPU_REGION_NUMBER0 00529 * @arg @ref LL_MPU_REGION_NUMBER1 00530 * @arg @ref LL_MPU_REGION_NUMBER2 00531 * @arg @ref LL_MPU_REGION_NUMBER3 00532 * @arg @ref LL_MPU_REGION_NUMBER4 00533 * @arg @ref LL_MPU_REGION_NUMBER5 00534 * @arg @ref LL_MPU_REGION_NUMBER6 00535 * @arg @ref LL_MPU_REGION_NUMBER7 00536 * @retval None 00537 */ 00538 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) 00539 { 00540 /* Set Region number */ 00541 WRITE_REG(MPU->RNR, Region); 00542 /* Enable the MPU region */ 00543 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 00544 } 00545 00546 /** 00547 * @brief Configure and enable a region 00548 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n 00549 * MPU_RBAR REGION LL_MPU_ConfigRegion\n 00550 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n 00551 * MPU_RASR XN LL_MPU_ConfigRegion\n 00552 * MPU_RASR AP LL_MPU_ConfigRegion\n 00553 * MPU_RASR S LL_MPU_ConfigRegion\n 00554 * MPU_RASR C LL_MPU_ConfigRegion\n 00555 * MPU_RASR B LL_MPU_ConfigRegion\n 00556 * MPU_RASR SIZE LL_MPU_ConfigRegion 00557 * @param Region This parameter can be one of the following values: 00558 * @arg @ref LL_MPU_REGION_NUMBER0 00559 * @arg @ref LL_MPU_REGION_NUMBER1 00560 * @arg @ref LL_MPU_REGION_NUMBER2 00561 * @arg @ref LL_MPU_REGION_NUMBER3 00562 * @arg @ref LL_MPU_REGION_NUMBER4 00563 * @arg @ref LL_MPU_REGION_NUMBER5 00564 * @arg @ref LL_MPU_REGION_NUMBER6 00565 * @arg @ref LL_MPU_REGION_NUMBER7 00566 * @param Address Value of region base address 00567 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF 00568 * @param Attributes This parameter can be a combination of the following values: 00569 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B 00570 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB 00571 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB 00572 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB 00573 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB 00574 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB 00575 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS 00576 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO 00577 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 00578 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE 00579 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE 00580 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE 00581 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE 00582 * @retval None 00583 */ 00584 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) 00585 { 00586 /* Set Region number */ 00587 WRITE_REG(MPU->RNR, Region); 00588 /* Set base address */ 00589 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); 00590 /* Configure MPU */ 00591 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); 00592 } 00593 00594 /** 00595 * @brief Disable a region 00596 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n 00597 * MPU_RASR ENABLE LL_MPU_DisableRegion 00598 * @param Region This parameter can be one of the following values: 00599 * @arg @ref LL_MPU_REGION_NUMBER0 00600 * @arg @ref LL_MPU_REGION_NUMBER1 00601 * @arg @ref LL_MPU_REGION_NUMBER2 00602 * @arg @ref LL_MPU_REGION_NUMBER3 00603 * @arg @ref LL_MPU_REGION_NUMBER4 00604 * @arg @ref LL_MPU_REGION_NUMBER5 00605 * @arg @ref LL_MPU_REGION_NUMBER6 00606 * @arg @ref LL_MPU_REGION_NUMBER7 00607 * @retval None 00608 */ 00609 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) 00610 { 00611 /* Set Region number */ 00612 WRITE_REG(MPU->RNR, Region); 00613 /* Disable the MPU region */ 00614 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 00615 } 00616 00617 /** 00618 * @} 00619 */ 00620 00621 #endif /* __MPU_PRESENT */ 00622 /** 00623 * @} 00624 */ 00625 00626 /** 00627 * @} 00628 */ 00629 00630 /** 00631 * @} 00632 */ 00633 00634 #ifdef __cplusplus 00635 } 00636 #endif 00637 00638 #endif /* __STM32F4xx_LL_CORTEX_H */ 00639 00640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1