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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_dac.h 00004 * @author MCD Application Team 00005 * @brief Header file of DAC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32F4xx_LL_DAC_H 00022 #define STM32F4xx_LL_DAC_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f4xx.h" 00030 00031 /** @addtogroup STM32F4xx_LL_Driver 00032 * @{ 00033 */ 00034 00035 #if defined(DAC) 00036 00037 /** @defgroup DAC_LL DAC 00038 * @{ 00039 */ 00040 00041 /* Private types -------------------------------------------------------------*/ 00042 /* Private variables ---------------------------------------------------------*/ 00043 00044 /* Private constants ---------------------------------------------------------*/ 00045 /** @defgroup DAC_LL_Private_Constants DAC Private Constants 00046 * @{ 00047 */ 00048 00049 /* Internal masks for DAC channels definition */ 00050 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ 00051 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ 00052 /* - channel bits position into register SWTRIG */ 00053 /* - channel register offset of data holding register DHRx */ 00054 /* - channel register offset of data output register DORx */ 00055 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers 00056 CR, MCR, CCR, SHHR, SHRR of channel 1 */ 00057 #if defined(DAC_CHANNEL2_SUPPORT) 00058 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers 00059 CR, MCR, CCR, SHHR, SHRR of channel 2 */ 00060 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) 00061 #else 00062 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET) 00063 #endif /* DAC_CHANNEL2_SUPPORT */ 00064 00065 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ 00066 #if defined(DAC_CHANNEL2_SUPPORT) 00067 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ 00068 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) 00069 #else 00070 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) 00071 #endif /* DAC_CHANNEL2_SUPPORT */ 00072 00073 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ 00074 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus 00075 DHR12Rx channel 1 (shifted left of 20 bits) */ 00076 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus 00077 DHR12Rx channel 1 (shifted left of 24 bits) */ 00078 #if defined(DAC_CHANNEL2_SUPPORT) 00079 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus 00080 DHR12Rx channel 1 (shifted left of 16 bits) */ 00081 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus 00082 DHR12Rx channel 1 (shifted left of 20 bits) */ 00083 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus 00084 DHR12Rx channel 1 (shifted left of 24 bits) */ 00085 #endif /* DAC_CHANNEL2_SUPPORT */ 00086 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL 00087 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL 00088 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL 00089 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ 00090 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) 00091 00092 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ 00093 #if defined(DAC_CHANNEL2_SUPPORT) 00094 #define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus 00095 DORx channel 2 (shifted left of 28 bits) */ 00096 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) 00097 #endif /* DAC_CHANNEL2_SUPPORT */ 00098 00099 00100 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, 00101 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ 00102 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted 00103 to position 0 */ 00104 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted 00105 to position 0 */ 00106 00107 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx 00108 channel 1 or 2 versus DHR12Rx channel 1 00109 (shifted left of 16 bits) */ 00110 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx 00111 channel 1 or 2 versus DHR12Rx channel 1 00112 (shifted left of 20 bits) */ 00113 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx 00114 channel 1 or 2 versus DHR12Rx channel 1 00115 (shifted left of 24 bits) */ 00116 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx 00117 channel 1 or 2 versus DORx channel 1 00118 (shifted left of 28 bits) */ 00119 00120 /* DAC registers bits positions */ 00121 #if defined(DAC_CHANNEL2_SUPPORT) 00122 #endif 00123 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos 00124 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos 00125 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos 00126 00127 /* Miscellaneous data */ 00128 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 00129 bits (voltage range determined by analog voltage 00130 references Vref+ and Vref-, refer to reference manual) */ 00131 00132 /** 00133 * @} 00134 */ 00135 00136 00137 /* Private macros ------------------------------------------------------------*/ 00138 /** @defgroup DAC_LL_Private_Macros DAC Private Macros 00139 * @{ 00140 */ 00141 00142 /** 00143 * @brief Driver macro reserved for internal use: set a pointer to 00144 * a register from a register basis from which an offset 00145 * is applied. 00146 * @param __REG__ Register basis from which the offset is applied. 00147 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). 00148 * @retval Pointer to register address 00149 */ 00150 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 00151 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) 00152 00153 /** 00154 * @} 00155 */ 00156 00157 00158 /* Exported types ------------------------------------------------------------*/ 00159 #if defined(USE_FULL_LL_DRIVER) 00160 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure 00161 * @{ 00162 */ 00163 00164 /** 00165 * @brief Structure definition of some features of DAC instance. 00166 */ 00167 typedef struct 00168 { 00169 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: 00170 internal (SW start) or from external peripheral 00171 (timer event, external interrupt line). 00172 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE 00173 00174 This feature can be modified afterwards using unitary 00175 function @ref LL_DAC_SetTriggerSource(). */ 00176 00177 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. 00178 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE 00179 00180 This feature can be modified afterwards using unitary 00181 function @ref LL_DAC_SetWaveAutoGeneration(). */ 00182 00183 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. 00184 If waveform automatic generation mode is set to noise, this parameter 00185 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS 00186 If waveform automatic generation mode is set to triangle, 00187 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE 00188 @note If waveform automatic generation mode is disabled, 00189 this parameter is discarded. 00190 00191 This feature can be modified afterwards using unitary 00192 function @ref LL_DAC_SetWaveNoiseLFSR(), 00193 @ref LL_DAC_SetWaveTriangleAmplitude() 00194 depending on the wave automatic generation selected. */ 00195 00196 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. 00197 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER 00198 00199 This feature can be modified afterwards using unitary 00200 function @ref LL_DAC_SetOutputBuffer(). */ 00201 } LL_DAC_InitTypeDef; 00202 00203 /** 00204 * @} 00205 */ 00206 #endif /* USE_FULL_LL_DRIVER */ 00207 00208 /* Exported constants --------------------------------------------------------*/ 00209 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants 00210 * @{ 00211 */ 00212 00213 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags 00214 * @brief Flags defines which can be used with LL_DAC_ReadReg function 00215 * @{ 00216 */ 00217 /* DAC channel 1 flags */ 00218 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ 00219 #if defined(DAC_CHANNEL2_SUPPORT) 00220 /* DAC channel 2 flags */ 00221 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ 00222 #endif /* DAC_CHANNEL2_SUPPORT */ 00223 /** 00224 * @} 00225 */ 00226 00227 /** @defgroup DAC_LL_EC_IT DAC interruptions 00228 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions 00229 * @{ 00230 */ 00231 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ 00232 #if defined(DAC_CHANNEL2_SUPPORT) 00233 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ 00234 #endif /* DAC_CHANNEL2_SUPPORT */ 00235 /** 00236 * @} 00237 */ 00238 00239 /** @defgroup DAC_LL_EC_CHANNEL DAC channels 00240 * @{ 00241 */ 00242 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ 00243 #if defined(DAC_CHANNEL2_SUPPORT) 00244 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ 00245 #endif /* DAC_CHANNEL2_SUPPORT */ 00246 /** 00247 * @} 00248 */ 00249 00250 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source 00251 * @{ 00252 */ 00253 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ 00254 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */ 00255 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */ 00256 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */ 00257 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */ 00258 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ 00259 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */ 00260 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ 00261 /** 00262 * @} 00263 */ 00264 00265 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode 00266 * @{ 00267 */ 00268 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */ 00269 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ 00270 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ 00271 /** 00272 * @} 00273 */ 00274 00275 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits 00276 * @{ 00277 */ 00278 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ 00279 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ 00280 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ 00281 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ 00282 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ 00283 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ 00284 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ 00285 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ 00286 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ 00287 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ 00288 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ 00289 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ 00290 /** 00291 * @} 00292 */ 00293 00294 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude 00295 * @{ 00296 */ 00297 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ 00298 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ 00299 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ 00300 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ 00301 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ 00302 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ 00303 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ 00304 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ 00305 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ 00306 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ 00307 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ 00308 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ 00309 /** 00310 * @} 00311 */ 00312 00313 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer 00314 * @{ 00315 */ 00316 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ 00317 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ 00318 /** 00319 * @} 00320 */ 00321 00322 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution 00323 * @{ 00324 */ 00325 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */ 00326 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */ 00327 /** 00328 * @} 00329 */ 00330 00331 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose 00332 * @{ 00333 */ 00334 /* List of DAC registers intended to be used (most commonly) with */ 00335 /* DMA transfer. */ 00336 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ 00337 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ 00338 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ 00339 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ 00340 /** 00341 * @} 00342 */ 00343 00344 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays 00345 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, 00346 * not timeout values. 00347 * For details on delays values, refer to descriptions in source code 00348 * above each literal definition. 00349 * @{ 00350 */ 00351 00352 /* Delay for DAC channel voltage settling time from DAC channel startup */ 00353 /* (transition from disable to enable). */ 00354 /* Note: DAC channel startup time depends on board application environment: */ 00355 /* impedance connected to DAC channel output. */ 00356 /* The delay below is specified under conditions: */ 00357 /* - voltage maximum transition (lowest to highest value) */ 00358 /* - until voltage reaches final value +-1LSB */ 00359 /* - DAC channel output buffer enabled */ 00360 /* - load impedance of 5kOhm (min), 50pF (max) */ 00361 /* Literal set to maximum value (refer to device datasheet, */ 00362 /* parameter "tWAKEUP"). */ 00363 /* Unit: us */ 00364 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ 00365 00366 /* Delay for DAC channel voltage settling time. */ 00367 /* Note: DAC channel startup time depends on board application environment: */ 00368 /* impedance connected to DAC channel output. */ 00369 /* The delay below is specified under conditions: */ 00370 /* - voltage maximum transition (lowest to highest value) */ 00371 /* - until voltage reaches final value +-1LSB */ 00372 /* - DAC channel output buffer enabled */ 00373 /* - load impedance of 5kOhm min, 50pF max */ 00374 /* Literal set to maximum value (refer to device datasheet, */ 00375 /* parameter "tSETTLING"). */ 00376 /* Unit: us */ 00377 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */ 00378 00379 /** 00380 * @} 00381 */ 00382 00383 /** 00384 * @} 00385 */ 00386 00387 /* Exported macro ------------------------------------------------------------*/ 00388 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros 00389 * @{ 00390 */ 00391 00392 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros 00393 * @{ 00394 */ 00395 00396 /** 00397 * @brief Write a value in DAC register 00398 * @param __INSTANCE__ DAC Instance 00399 * @param __REG__ Register to be written 00400 * @param __VALUE__ Value to be written in the register 00401 * @retval None 00402 */ 00403 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00404 00405 /** 00406 * @brief Read a value in DAC register 00407 * @param __INSTANCE__ DAC Instance 00408 * @param __REG__ Register to be read 00409 * @retval Register value 00410 */ 00411 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00412 00413 /** 00414 * @} 00415 */ 00416 00417 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro 00418 * @{ 00419 */ 00420 00421 /** 00422 * @brief Helper macro to get DAC channel number in decimal format 00423 * from literals LL_DAC_CHANNEL_x. 00424 * Example: 00425 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) 00426 * will return decimal number "1". 00427 * @note The input can be a value from functions where a channel 00428 * number is returned. 00429 * @param __CHANNEL__ This parameter can be one of the following values: 00430 * @arg @ref LL_DAC_CHANNEL_1 00431 * @arg @ref LL_DAC_CHANNEL_2 (1) 00432 * 00433 * (1) On this STM32 serie, parameter not available on all devices. 00434 * Refer to device datasheet for channels availability. 00435 * @retval 1...2 (value "2" depending on DAC channel 2 availability) 00436 */ 00437 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 00438 ((__CHANNEL__) & DAC_SWTR_CHX_MASK) 00439 00440 /** 00441 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x 00442 * from number in decimal format. 00443 * Example: 00444 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) 00445 * will return a data equivalent to "LL_DAC_CHANNEL_1". 00446 * @note If the input parameter does not correspond to a DAC channel, 00447 * this macro returns value '0'. 00448 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability) 00449 * @retval Returned value can be one of the following values: 00450 * @arg @ref LL_DAC_CHANNEL_1 00451 * @arg @ref LL_DAC_CHANNEL_2 (1) 00452 * 00453 * (1) On this STM32 serie, parameter not available on all devices. 00454 * Refer to device datasheet for channels availability. 00455 */ 00456 #if defined(DAC_CHANNEL2_SUPPORT) 00457 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 00458 (((__DECIMAL_NB__) == 1UL) \ 00459 ? ( \ 00460 LL_DAC_CHANNEL_1 \ 00461 ) \ 00462 : \ 00463 (((__DECIMAL_NB__) == 2UL) \ 00464 ? ( \ 00465 LL_DAC_CHANNEL_2 \ 00466 ) \ 00467 : \ 00468 ( \ 00469 0UL \ 00470 ) \ 00471 ) \ 00472 ) 00473 #else 00474 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 00475 (((__DECIMAL_NB__) == 1UL) \ 00476 ? ( \ 00477 LL_DAC_CHANNEL_1 \ 00478 ) \ 00479 : \ 00480 ( \ 00481 0UL \ 00482 ) \ 00483 ) 00484 #endif /* DAC_CHANNEL2_SUPPORT */ 00485 00486 /** 00487 * @brief Helper macro to define the DAC conversion data full-scale digital 00488 * value corresponding to the selected DAC resolution. 00489 * @note DAC conversion data full-scale corresponds to voltage range 00490 * determined by analog voltage references Vref+ and Vref- 00491 * (refer to reference manual). 00492 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 00493 * @arg @ref LL_DAC_RESOLUTION_12B 00494 * @arg @ref LL_DAC_RESOLUTION_8B 00495 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 00496 */ 00497 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 00498 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL)) 00499 00500 /** 00501 * @brief Helper macro to calculate the DAC conversion data (unit: digital 00502 * value) corresponding to a voltage (unit: mVolt). 00503 * @note This helper macro is intended to provide input data in voltage 00504 * rather than digital value, 00505 * to be used with LL DAC functions such as 00506 * @ref LL_DAC_ConvertData12RightAligned(). 00507 * @note Analog reference voltage (Vref+) must be either known from 00508 * user board environment or can be calculated using ADC measurement 00509 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 00510 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 00511 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel 00512 * (unit: mVolt). 00513 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 00514 * @arg @ref LL_DAC_RESOLUTION_12B 00515 * @arg @ref LL_DAC_RESOLUTION_8B 00516 * @retval DAC conversion data (unit: digital value) 00517 */ 00518 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ 00519 __DAC_VOLTAGE__,\ 00520 __DAC_RESOLUTION__) \ 00521 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 00522 / (__VREFANALOG_VOLTAGE__) \ 00523 ) 00524 00525 /** 00526 * @} 00527 */ 00528 00529 /** 00530 * @} 00531 */ 00532 00533 00534 /* Exported functions --------------------------------------------------------*/ 00535 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions 00536 * @{ 00537 */ 00538 /** 00539 * @brief Set the conversion trigger source for the selected DAC channel. 00540 * @note For conversion trigger source to be effective, DAC trigger 00541 * must be enabled using function @ref LL_DAC_EnableTrigger(). 00542 * @note To set conversion trigger source, DAC channel must be disabled. 00543 * Otherwise, the setting is discarded. 00544 * @note Availability of parameters of trigger sources from timer 00545 * depends on timers availability on the selected device. 00546 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n 00547 * CR TSEL2 LL_DAC_SetTriggerSource 00548 * @param DACx DAC instance 00549 * @param DAC_Channel This parameter can be one of the following values: 00550 * @arg @ref LL_DAC_CHANNEL_1 00551 * @arg @ref LL_DAC_CHANNEL_2 (1) 00552 * 00553 * (1) On this STM32 serie, parameter not available on all devices. 00554 * Refer to device datasheet for channels availability. 00555 * @param TriggerSource This parameter can be one of the following values: 00556 * @arg @ref LL_DAC_TRIG_SOFTWARE 00557 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO 00558 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 00559 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 00560 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 00561 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 00562 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 00563 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 00564 * @retval None 00565 */ 00566 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) 00567 { 00568 MODIFY_REG(DACx->CR, 00569 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00570 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00571 } 00572 00573 /** 00574 * @brief Get the conversion trigger source for the selected DAC channel. 00575 * @note For conversion trigger source to be effective, DAC trigger 00576 * must be enabled using function @ref LL_DAC_EnableTrigger(). 00577 * @note Availability of parameters of trigger sources from timer 00578 * depends on timers availability on the selected device. 00579 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n 00580 * CR TSEL2 LL_DAC_GetTriggerSource 00581 * @param DACx DAC instance 00582 * @param DAC_Channel This parameter can be one of the following values: 00583 * @arg @ref LL_DAC_CHANNEL_1 00584 * @arg @ref LL_DAC_CHANNEL_2 (1) 00585 * 00586 * (1) On this STM32 serie, parameter not available on all devices. 00587 * Refer to device datasheet for channels availability. 00588 * @retval Returned value can be one of the following values: 00589 * @arg @ref LL_DAC_TRIG_SOFTWARE 00590 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO 00591 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 00592 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 00593 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 00594 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 00595 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 00596 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 00597 */ 00598 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00599 { 00600 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00601 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00602 ); 00603 } 00604 00605 /** 00606 * @brief Set the waveform automatic generation mode 00607 * for the selected DAC channel. 00608 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n 00609 * CR WAVE2 LL_DAC_SetWaveAutoGeneration 00610 * @param DACx DAC instance 00611 * @param DAC_Channel This parameter can be one of the following values: 00612 * @arg @ref LL_DAC_CHANNEL_1 00613 * @arg @ref LL_DAC_CHANNEL_2 (1) 00614 * 00615 * (1) On this STM32 serie, parameter not available on all devices. 00616 * Refer to device datasheet for channels availability. 00617 * @param WaveAutoGeneration This parameter can be one of the following values: 00618 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 00619 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 00620 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 00621 * @retval None 00622 */ 00623 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) 00624 { 00625 MODIFY_REG(DACx->CR, 00626 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00627 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00628 } 00629 00630 /** 00631 * @brief Get the waveform automatic generation mode 00632 * for the selected DAC channel. 00633 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n 00634 * CR WAVE2 LL_DAC_GetWaveAutoGeneration 00635 * @param DACx DAC instance 00636 * @param DAC_Channel This parameter can be one of the following values: 00637 * @arg @ref LL_DAC_CHANNEL_1 00638 * @arg @ref LL_DAC_CHANNEL_2 (1) 00639 * 00640 * (1) On this STM32 serie, parameter not available on all devices. 00641 * Refer to device datasheet for channels availability. 00642 * @retval Returned value can be one of the following values: 00643 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 00644 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 00645 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 00646 */ 00647 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00648 { 00649 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00650 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00651 ); 00652 } 00653 00654 /** 00655 * @brief Set the noise waveform generation for the selected DAC channel: 00656 * Noise mode and parameters LFSR (linear feedback shift register). 00657 * @note For wave generation to be effective, DAC channel 00658 * wave generation mode must be enabled using 00659 * function @ref LL_DAC_SetWaveAutoGeneration(). 00660 * @note This setting can be set when the selected DAC channel is disabled 00661 * (otherwise, the setting operation is ignored). 00662 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n 00663 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR 00664 * @param DACx DAC instance 00665 * @param DAC_Channel This parameter can be one of the following values: 00666 * @arg @ref LL_DAC_CHANNEL_1 00667 * @arg @ref LL_DAC_CHANNEL_2 (1) 00668 * 00669 * (1) On this STM32 serie, parameter not available on all devices. 00670 * Refer to device datasheet for channels availability. 00671 * @param NoiseLFSRMask This parameter can be one of the following values: 00672 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 00673 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 00674 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 00675 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 00676 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 00677 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 00678 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 00679 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 00680 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 00681 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 00682 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 00683 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 00684 * @retval None 00685 */ 00686 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) 00687 { 00688 MODIFY_REG(DACx->CR, 00689 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00690 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00691 } 00692 00693 /** 00694 * @brief Get the noise waveform generation for the selected DAC channel: 00695 * Noise mode and parameters LFSR (linear feedback shift register). 00696 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n 00697 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR 00698 * @param DACx DAC instance 00699 * @param DAC_Channel This parameter can be one of the following values: 00700 * @arg @ref LL_DAC_CHANNEL_1 00701 * @arg @ref LL_DAC_CHANNEL_2 (1) 00702 * 00703 * (1) On this STM32 serie, parameter not available on all devices. 00704 * Refer to device datasheet for channels availability. 00705 * @retval Returned value can be one of the following values: 00706 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 00707 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 00708 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 00709 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 00710 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 00711 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 00712 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 00713 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 00714 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 00715 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 00716 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 00717 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 00718 */ 00719 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00720 { 00721 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00722 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00723 ); 00724 } 00725 00726 /** 00727 * @brief Set the triangle waveform generation for the selected DAC channel: 00728 * triangle mode and amplitude. 00729 * @note For wave generation to be effective, DAC channel 00730 * wave generation mode must be enabled using 00731 * function @ref LL_DAC_SetWaveAutoGeneration(). 00732 * @note This setting can be set when the selected DAC channel is disabled 00733 * (otherwise, the setting operation is ignored). 00734 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n 00735 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude 00736 * @param DACx DAC instance 00737 * @param DAC_Channel This parameter can be one of the following values: 00738 * @arg @ref LL_DAC_CHANNEL_1 00739 * @arg @ref LL_DAC_CHANNEL_2 (1) 00740 * 00741 * (1) On this STM32 serie, parameter not available on all devices. 00742 * Refer to device datasheet for channels availability. 00743 * @param TriangleAmplitude This parameter can be one of the following values: 00744 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 00745 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 00746 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 00747 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 00748 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 00749 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 00750 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 00751 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 00752 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 00753 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 00754 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 00755 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 00756 * @retval None 00757 */ 00758 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, 00759 uint32_t TriangleAmplitude) 00760 { 00761 MODIFY_REG(DACx->CR, 00762 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00763 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00764 } 00765 00766 /** 00767 * @brief Get the triangle waveform generation for the selected DAC channel: 00768 * triangle mode and amplitude. 00769 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n 00770 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude 00771 * @param DACx DAC instance 00772 * @param DAC_Channel This parameter can be one of the following values: 00773 * @arg @ref LL_DAC_CHANNEL_1 00774 * @arg @ref LL_DAC_CHANNEL_2 (1) 00775 * 00776 * (1) On this STM32 serie, parameter not available on all devices. 00777 * Refer to device datasheet for channels availability. 00778 * @retval Returned value can be one of the following values: 00779 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 00780 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 00781 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 00782 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 00783 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 00784 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 00785 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 00786 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 00787 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 00788 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 00789 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 00790 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 00791 */ 00792 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00793 { 00794 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00795 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00796 ); 00797 } 00798 00799 /** 00800 * @brief Set the output buffer for the selected DAC channel. 00801 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n 00802 * CR BOFF2 LL_DAC_SetOutputBuffer 00803 * @param DACx DAC instance 00804 * @param DAC_Channel This parameter can be one of the following values: 00805 * @arg @ref LL_DAC_CHANNEL_1 00806 * @arg @ref LL_DAC_CHANNEL_2 (1) 00807 * 00808 * (1) On this STM32 serie, parameter not available on all devices. 00809 * Refer to device datasheet for channels availability. 00810 * @param OutputBuffer This parameter can be one of the following values: 00811 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 00812 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 00813 * @retval None 00814 */ 00815 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) 00816 { 00817 MODIFY_REG(DACx->CR, 00818 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00819 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00820 } 00821 00822 /** 00823 * @brief Get the output buffer state for the selected DAC channel. 00824 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n 00825 * CR BOFF2 LL_DAC_GetOutputBuffer 00826 * @param DACx DAC instance 00827 * @param DAC_Channel This parameter can be one of the following values: 00828 * @arg @ref LL_DAC_CHANNEL_1 00829 * @arg @ref LL_DAC_CHANNEL_2 (1) 00830 * 00831 * (1) On this STM32 serie, parameter not available on all devices. 00832 * Refer to device datasheet for channels availability. 00833 * @retval Returned value can be one of the following values: 00834 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 00835 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 00836 */ 00837 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00838 { 00839 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00840 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00841 ); 00842 } 00843 00844 /** 00845 * @} 00846 */ 00847 00848 /** @defgroup DAC_LL_EF_DMA_Management DMA Management 00849 * @{ 00850 */ 00851 00852 /** 00853 * @brief Enable DAC DMA transfer request of the selected channel. 00854 * @note To configure DMA source address (peripheral address), 00855 * use function @ref LL_DAC_DMA_GetRegAddr(). 00856 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n 00857 * CR DMAEN2 LL_DAC_EnableDMAReq 00858 * @param DACx DAC instance 00859 * @param DAC_Channel This parameter can be one of the following values: 00860 * @arg @ref LL_DAC_CHANNEL_1 00861 * @arg @ref LL_DAC_CHANNEL_2 (1) 00862 * 00863 * (1) On this STM32 serie, parameter not available on all devices. 00864 * Refer to device datasheet for channels availability. 00865 * @retval None 00866 */ 00867 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00868 { 00869 SET_BIT(DACx->CR, 00870 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00871 } 00872 00873 /** 00874 * @brief Disable DAC DMA transfer request of the selected channel. 00875 * @note To configure DMA source address (peripheral address), 00876 * use function @ref LL_DAC_DMA_GetRegAddr(). 00877 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n 00878 * CR DMAEN2 LL_DAC_DisableDMAReq 00879 * @param DACx DAC instance 00880 * @param DAC_Channel This parameter can be one of the following values: 00881 * @arg @ref LL_DAC_CHANNEL_1 00882 * @arg @ref LL_DAC_CHANNEL_2 (1) 00883 * 00884 * (1) On this STM32 serie, parameter not available on all devices. 00885 * Refer to device datasheet for channels availability. 00886 * @retval None 00887 */ 00888 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00889 { 00890 CLEAR_BIT(DACx->CR, 00891 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00892 } 00893 00894 /** 00895 * @brief Get DAC DMA transfer request state of the selected channel. 00896 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) 00897 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n 00898 * CR DMAEN2 LL_DAC_IsDMAReqEnabled 00899 * @param DACx DAC instance 00900 * @param DAC_Channel This parameter can be one of the following values: 00901 * @arg @ref LL_DAC_CHANNEL_1 00902 * @arg @ref LL_DAC_CHANNEL_2 (1) 00903 * 00904 * (1) On this STM32 serie, parameter not available on all devices. 00905 * Refer to device datasheet for channels availability. 00906 * @retval State of bit (1 or 0). 00907 */ 00908 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00909 { 00910 return ((READ_BIT(DACx->CR, 00911 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00912 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 00913 } 00914 00915 /** 00916 * @brief Function to help to configure DMA transfer to DAC: retrieve the 00917 * DAC register address from DAC instance and a list of DAC registers 00918 * intended to be used (most commonly) with DMA transfer. 00919 * @note These DAC registers are data holding registers: 00920 * when DAC conversion is requested, DAC generates a DMA transfer 00921 * request to have data available in DAC data holding registers. 00922 * @note This macro is intended to be used with LL DMA driver, refer to 00923 * function "LL_DMA_ConfigAddresses()". 00924 * Example: 00925 * LL_DMA_ConfigAddresses(DMA1, 00926 * LL_DMA_CHANNEL_1, 00927 * (uint32_t)&< array or variable >, 00928 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, 00929 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), 00930 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); 00931 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 00932 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 00933 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 00934 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 00935 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 00936 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr 00937 * @param DACx DAC instance 00938 * @param DAC_Channel This parameter can be one of the following values: 00939 * @arg @ref LL_DAC_CHANNEL_1 00940 * @arg @ref LL_DAC_CHANNEL_2 (1) 00941 * 00942 * (1) On this STM32 serie, parameter not available on all devices. 00943 * Refer to device datasheet for channels availability. 00944 * @param Register This parameter can be one of the following values: 00945 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED 00946 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED 00947 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED 00948 * @retval DAC register address 00949 */ 00950 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) 00951 { 00952 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ 00953 /* DAC channel selected. */ 00954 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) 00955 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); 00956 } 00957 /** 00958 * @} 00959 */ 00960 00961 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels 00962 * @{ 00963 */ 00964 00965 /** 00966 * @brief Enable DAC selected channel. 00967 * @rmtoll CR EN1 LL_DAC_Enable\n 00968 * CR EN2 LL_DAC_Enable 00969 * @note After enable from off state, DAC channel requires a delay 00970 * for output voltage to reach accuracy +/- 1 LSB. 00971 * Refer to device datasheet, parameter "tWAKEUP". 00972 * @param DACx DAC instance 00973 * @param DAC_Channel This parameter can be one of the following values: 00974 * @arg @ref LL_DAC_CHANNEL_1 00975 * @arg @ref LL_DAC_CHANNEL_2 (1) 00976 * 00977 * (1) On this STM32 serie, parameter not available on all devices. 00978 * Refer to device datasheet for channels availability. 00979 * @retval None 00980 */ 00981 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00982 { 00983 SET_BIT(DACx->CR, 00984 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00985 } 00986 00987 /** 00988 * @brief Disable DAC selected channel. 00989 * @rmtoll CR EN1 LL_DAC_Disable\n 00990 * CR EN2 LL_DAC_Disable 00991 * @param DACx DAC instance 00992 * @param DAC_Channel This parameter can be one of the following values: 00993 * @arg @ref LL_DAC_CHANNEL_1 00994 * @arg @ref LL_DAC_CHANNEL_2 (1) 00995 * 00996 * (1) On this STM32 serie, parameter not available on all devices. 00997 * Refer to device datasheet for channels availability. 00998 * @retval None 00999 */ 01000 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01001 { 01002 CLEAR_BIT(DACx->CR, 01003 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01004 } 01005 01006 /** 01007 * @brief Get DAC enable state of the selected channel. 01008 * (0: DAC channel is disabled, 1: DAC channel is enabled) 01009 * @rmtoll CR EN1 LL_DAC_IsEnabled\n 01010 * CR EN2 LL_DAC_IsEnabled 01011 * @param DACx DAC instance 01012 * @param DAC_Channel This parameter can be one of the following values: 01013 * @arg @ref LL_DAC_CHANNEL_1 01014 * @arg @ref LL_DAC_CHANNEL_2 (1) 01015 * 01016 * (1) On this STM32 serie, parameter not available on all devices. 01017 * Refer to device datasheet for channels availability. 01018 * @retval State of bit (1 or 0). 01019 */ 01020 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01021 { 01022 return ((READ_BIT(DACx->CR, 01023 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01024 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 01025 } 01026 01027 /** 01028 * @brief Enable DAC trigger of the selected channel. 01029 * @note - If DAC trigger is disabled, DAC conversion is performed 01030 * automatically once the data holding register is updated, 01031 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 01032 * @ref LL_DAC_ConvertData12RightAligned(), ... 01033 * - If DAC trigger is enabled, DAC conversion is performed 01034 * only when a hardware of software trigger event is occurring. 01035 * Select trigger source using 01036 * function @ref LL_DAC_SetTriggerSource(). 01037 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n 01038 * CR TEN2 LL_DAC_EnableTrigger 01039 * @param DACx DAC instance 01040 * @param DAC_Channel This parameter can be one of the following values: 01041 * @arg @ref LL_DAC_CHANNEL_1 01042 * @arg @ref LL_DAC_CHANNEL_2 (1) 01043 * 01044 * (1) On this STM32 serie, parameter not available on all devices. 01045 * Refer to device datasheet for channels availability. 01046 * @retval None 01047 */ 01048 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01049 { 01050 SET_BIT(DACx->CR, 01051 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01052 } 01053 01054 /** 01055 * @brief Disable DAC trigger of the selected channel. 01056 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n 01057 * CR TEN2 LL_DAC_DisableTrigger 01058 * @param DACx DAC instance 01059 * @param DAC_Channel This parameter can be one of the following values: 01060 * @arg @ref LL_DAC_CHANNEL_1 01061 * @arg @ref LL_DAC_CHANNEL_2 (1) 01062 * 01063 * (1) On this STM32 serie, parameter not available on all devices. 01064 * Refer to device datasheet for channels availability. 01065 * @retval None 01066 */ 01067 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01068 { 01069 CLEAR_BIT(DACx->CR, 01070 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01071 } 01072 01073 /** 01074 * @brief Get DAC trigger state of the selected channel. 01075 * (0: DAC trigger is disabled, 1: DAC trigger is enabled) 01076 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n 01077 * CR TEN2 LL_DAC_IsTriggerEnabled 01078 * @param DACx DAC instance 01079 * @param DAC_Channel This parameter can be one of the following values: 01080 * @arg @ref LL_DAC_CHANNEL_1 01081 * @arg @ref LL_DAC_CHANNEL_2 (1) 01082 * 01083 * (1) On this STM32 serie, parameter not available on all devices. 01084 * Refer to device datasheet for channels availability. 01085 * @retval State of bit (1 or 0). 01086 */ 01087 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01088 { 01089 return ((READ_BIT(DACx->CR, 01090 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01091 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 01092 } 01093 01094 /** 01095 * @brief Trig DAC conversion by software for the selected DAC channel. 01096 * @note Preliminarily, DAC trigger must be set to software trigger 01097 * using function 01098 * @ref LL_DAC_Init() 01099 * @ref LL_DAC_SetTriggerSource() 01100 * with parameter "LL_DAC_TRIGGER_SOFTWARE". 01101 * and DAC trigger must be enabled using 01102 * function @ref LL_DAC_EnableTrigger(). 01103 * @note For devices featuring DAC with 2 channels: this function 01104 * can perform a SW start of both DAC channels simultaneously. 01105 * Two channels can be selected as parameter. 01106 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) 01107 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n 01108 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion 01109 * @param DACx DAC instance 01110 * @param DAC_Channel This parameter can a combination of the following values: 01111 * @arg @ref LL_DAC_CHANNEL_1 01112 * @arg @ref LL_DAC_CHANNEL_2 (1) 01113 * 01114 * (1) On this STM32 serie, parameter not available on all devices. 01115 * Refer to device datasheet for channels availability. 01116 * @retval None 01117 */ 01118 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01119 { 01120 SET_BIT(DACx->SWTRIGR, 01121 (DAC_Channel & DAC_SWTR_CHX_MASK)); 01122 } 01123 01124 /** 01125 * @brief Set the data to be loaded in the data holding register 01126 * in format 12 bits left alignment (LSB aligned on bit 0), 01127 * for the selected DAC channel. 01128 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n 01129 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned 01130 * @param DACx DAC instance 01131 * @param DAC_Channel This parameter can be one of the following values: 01132 * @arg @ref LL_DAC_CHANNEL_1 01133 * @arg @ref LL_DAC_CHANNEL_2 (1) 01134 * 01135 * (1) On this STM32 serie, parameter not available on all devices. 01136 * Refer to device datasheet for channels availability. 01137 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 01138 * @retval None 01139 */ 01140 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01141 { 01142 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) 01143 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 01144 01145 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); 01146 } 01147 01148 /** 01149 * @brief Set the data to be loaded in the data holding register 01150 * in format 12 bits left alignment (MSB aligned on bit 15), 01151 * for the selected DAC channel. 01152 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n 01153 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned 01154 * @param DACx DAC instance 01155 * @param DAC_Channel This parameter can be one of the following values: 01156 * @arg @ref LL_DAC_CHANNEL_1 01157 * @arg @ref LL_DAC_CHANNEL_2 (1) 01158 * 01159 * (1) On this STM32 serie, parameter not available on all devices. 01160 * Refer to device datasheet for channels availability. 01161 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 01162 * @retval None 01163 */ 01164 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01165 { 01166 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) 01167 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 01168 01169 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); 01170 } 01171 01172 /** 01173 * @brief Set the data to be loaded in the data holding register 01174 * in format 8 bits left alignment (LSB aligned on bit 0), 01175 * for the selected DAC channel. 01176 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n 01177 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned 01178 * @param DACx DAC instance 01179 * @param DAC_Channel This parameter can be one of the following values: 01180 * @arg @ref LL_DAC_CHANNEL_1 01181 * @arg @ref LL_DAC_CHANNEL_2 (1) 01182 * 01183 * (1) On this STM32 serie, parameter not available on all devices. 01184 * Refer to device datasheet for channels availability. 01185 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF 01186 * @retval None 01187 */ 01188 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01189 { 01190 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) 01191 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 01192 01193 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); 01194 } 01195 01196 #if defined(DAC_CHANNEL2_SUPPORT) 01197 /** 01198 * @brief Set the data to be loaded in the data holding register 01199 * in format 12 bits left alignment (LSB aligned on bit 0), 01200 * for both DAC channels. 01201 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n 01202 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned 01203 * @param DACx DAC instance 01204 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 01205 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 01206 * @retval None 01207 */ 01208 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 01209 uint32_t DataChannel2) 01210 { 01211 MODIFY_REG(DACx->DHR12RD, 01212 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), 01213 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 01214 } 01215 01216 /** 01217 * @brief Set the data to be loaded in the data holding register 01218 * in format 12 bits left alignment (MSB aligned on bit 15), 01219 * for both DAC channels. 01220 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n 01221 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned 01222 * @param DACx DAC instance 01223 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 01224 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 01225 * @retval None 01226 */ 01227 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 01228 uint32_t DataChannel2) 01229 { 01230 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ 01231 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ 01232 /* the 4 LSB must be taken into account for the shift value. */ 01233 MODIFY_REG(DACx->DHR12LD, 01234 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), 01235 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); 01236 } 01237 01238 /** 01239 * @brief Set the data to be loaded in the data holding register 01240 * in format 8 bits left alignment (LSB aligned on bit 0), 01241 * for both DAC channels. 01242 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n 01243 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned 01244 * @param DACx DAC instance 01245 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF 01246 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF 01247 * @retval None 01248 */ 01249 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 01250 uint32_t DataChannel2) 01251 { 01252 MODIFY_REG(DACx->DHR8RD, 01253 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), 01254 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 01255 } 01256 #endif /* DAC_CHANNEL2_SUPPORT */ 01257 01258 /** 01259 * @brief Retrieve output data currently generated for the selected DAC channel. 01260 * @note Whatever alignment and resolution settings 01261 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 01262 * @ref LL_DAC_ConvertData12RightAligned(), ...), 01263 * output data format is 12 bits right aligned (LSB aligned on bit 0). 01264 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n 01265 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData 01266 * @param DACx DAC instance 01267 * @param DAC_Channel This parameter can be one of the following values: 01268 * @arg @ref LL_DAC_CHANNEL_1 01269 * @arg @ref LL_DAC_CHANNEL_2 (1) 01270 * 01271 * (1) On this STM32 serie, parameter not available on all devices. 01272 * Refer to device datasheet for channels availability. 01273 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01274 */ 01275 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01276 { 01277 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) 01278 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); 01279 01280 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); 01281 } 01282 01283 /** 01284 * @} 01285 */ 01286 01287 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management 01288 * @{ 01289 */ 01290 01291 /** 01292 * @brief Get DAC underrun flag for DAC channel 1 01293 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 01294 * @param DACx DAC instance 01295 * @retval State of bit (1 or 0). 01296 */ 01297 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) 01298 { 01299 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); 01300 } 01301 01302 #if defined(DAC_CHANNEL2_SUPPORT) 01303 /** 01304 * @brief Get DAC underrun flag for DAC channel 2 01305 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 01306 * @param DACx DAC instance 01307 * @retval State of bit (1 or 0). 01308 */ 01309 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) 01310 { 01311 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); 01312 } 01313 #endif /* DAC_CHANNEL2_SUPPORT */ 01314 01315 /** 01316 * @brief Clear DAC underrun flag for DAC channel 1 01317 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 01318 * @param DACx DAC instance 01319 * @retval None 01320 */ 01321 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) 01322 { 01323 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); 01324 } 01325 01326 #if defined(DAC_CHANNEL2_SUPPORT) 01327 /** 01328 * @brief Clear DAC underrun flag for DAC channel 2 01329 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 01330 * @param DACx DAC instance 01331 * @retval None 01332 */ 01333 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) 01334 { 01335 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); 01336 } 01337 #endif /* DAC_CHANNEL2_SUPPORT */ 01338 01339 /** 01340 * @} 01341 */ 01342 01343 /** @defgroup DAC_LL_EF_IT_Management IT management 01344 * @{ 01345 */ 01346 01347 /** 01348 * @brief Enable DMA underrun interrupt for DAC channel 1 01349 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 01350 * @param DACx DAC instance 01351 * @retval None 01352 */ 01353 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) 01354 { 01355 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 01356 } 01357 01358 #if defined(DAC_CHANNEL2_SUPPORT) 01359 /** 01360 * @brief Enable DMA underrun interrupt for DAC channel 2 01361 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 01362 * @param DACx DAC instance 01363 * @retval None 01364 */ 01365 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) 01366 { 01367 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 01368 } 01369 #endif /* DAC_CHANNEL2_SUPPORT */ 01370 01371 /** 01372 * @brief Disable DMA underrun interrupt for DAC channel 1 01373 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 01374 * @param DACx DAC instance 01375 * @retval None 01376 */ 01377 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) 01378 { 01379 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 01380 } 01381 01382 #if defined(DAC_CHANNEL2_SUPPORT) 01383 /** 01384 * @brief Disable DMA underrun interrupt for DAC channel 2 01385 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 01386 * @param DACx DAC instance 01387 * @retval None 01388 */ 01389 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) 01390 { 01391 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 01392 } 01393 #endif /* DAC_CHANNEL2_SUPPORT */ 01394 01395 /** 01396 * @brief Get DMA underrun interrupt for DAC channel 1 01397 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 01398 * @param DACx DAC instance 01399 * @retval State of bit (1 or 0). 01400 */ 01401 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) 01402 { 01403 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); 01404 } 01405 01406 #if defined(DAC_CHANNEL2_SUPPORT) 01407 /** 01408 * @brief Get DMA underrun interrupt for DAC channel 2 01409 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 01410 * @param DACx DAC instance 01411 * @retval State of bit (1 or 0). 01412 */ 01413 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) 01414 { 01415 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); 01416 } 01417 #endif /* DAC_CHANNEL2_SUPPORT */ 01418 01419 /** 01420 * @} 01421 */ 01422 01423 #if defined(USE_FULL_LL_DRIVER) 01424 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions 01425 * @{ 01426 */ 01427 01428 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); 01429 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); 01430 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); 01431 01432 /** 01433 * @} 01434 */ 01435 #endif /* USE_FULL_LL_DRIVER */ 01436 01437 /** 01438 * @} 01439 */ 01440 01441 /** 01442 * @} 01443 */ 01444 01445 #endif /* DAC */ 01446 01447 /** 01448 * @} 01449 */ 01450 01451 #ifdef __cplusplus 01452 } 01453 #endif 01454 01455 #endif /* STM32F4xx_LL_DAC_H */ 01456 01457 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1