|
STM32F479xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_dma.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F4xx_LL_DMA_H 00022 #define __STM32F4xx_LL_DMA_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f4xx.h" 00030 00031 /** @addtogroup STM32F4xx_LL_Driver 00032 * @{ 00033 */ 00034 00035 #if defined (DMA1) || defined (DMA2) 00036 00037 /** @defgroup DMA_LL DMA 00038 * @{ 00039 */ 00040 00041 /* Private types -------------------------------------------------------------*/ 00042 /* Private variables ---------------------------------------------------------*/ 00043 /** @defgroup DMA_LL_Private_Variables DMA Private Variables 00044 * @{ 00045 */ 00046 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ 00047 static const uint8_t STREAM_OFFSET_TAB[] = 00048 { 00049 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 00050 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), 00051 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 00052 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 00053 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 00054 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 00055 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 00056 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) 00057 }; 00058 00059 /** 00060 * @} 00061 */ 00062 00063 /* Private constants ---------------------------------------------------------*/ 00064 /** @defgroup DMA_LL_Private_Constants DMA Private Constants 00065 * @{ 00066 */ 00067 /** 00068 * @} 00069 */ 00070 00071 00072 /* Private macros ------------------------------------------------------------*/ 00073 /* Exported types ------------------------------------------------------------*/ 00074 #if defined(USE_FULL_LL_DRIVER) 00075 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure 00076 * @{ 00077 */ 00078 typedef struct 00079 { 00080 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer 00081 or as Source base address in case of memory to memory transfer direction. 00082 00083 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 00084 00085 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 00086 or as Destination base address in case of memory to memory transfer direction. 00087 00088 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 00089 00090 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 00091 from memory to memory or from peripheral to memory. 00092 This parameter can be a value of @ref DMA_LL_EC_DIRECTION 00093 00094 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ 00095 00096 uint32_t Mode; /*!< Specifies the normal or circular operation mode. 00097 This parameter can be a value of @ref DMA_LL_EC_MODE 00098 @note The circular buffer mode cannot be used if the memory to memory 00099 data transfer direction is configured on the selected Stream 00100 00101 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ 00102 00103 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction 00104 is incremented or not. 00105 This parameter can be a value of @ref DMA_LL_EC_PERIPH 00106 00107 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ 00108 00109 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction 00110 is incremented or not. 00111 This parameter can be a value of @ref DMA_LL_EC_MEMORY 00112 00113 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ 00114 00115 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) 00116 in case of memory to memory transfer direction. 00117 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN 00118 00119 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ 00120 00121 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) 00122 in case of memory to memory transfer direction. 00123 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN 00124 00125 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ 00126 00127 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 00128 The data unit is equal to the source buffer configuration set in PeripheralSize 00129 or MemorySize parameters depending in the transfer direction. 00130 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF 00131 00132 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ 00133 00134 uint32_t Channel; /*!< Specifies the peripheral channel. 00135 This parameter can be a value of @ref DMA_LL_EC_CHANNEL 00136 00137 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */ 00138 00139 uint32_t Priority; /*!< Specifies the channel priority level. 00140 This parameter can be a value of @ref DMA_LL_EC_PRIORITY 00141 00142 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ 00143 00144 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 00145 This parameter can be a value of @ref DMA_LL_FIFOMODE 00146 @note The Direct mode (FIFO mode disabled) cannot be used if the 00147 memory-to-memory data transfer is configured on the selected stream 00148 00149 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ 00150 00151 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 00152 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD 00153 00154 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ 00155 00156 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 00157 It specifies the amount of data to be transferred in a single non interruptible 00158 transaction. 00159 This parameter can be a value of @ref DMA_LL_EC_MBURST 00160 @note The burst mode is possible only if the address Increment mode is enabled. 00161 00162 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ 00163 00164 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 00165 It specifies the amount of data to be transferred in a single non interruptible 00166 transaction. 00167 This parameter can be a value of @ref DMA_LL_EC_PBURST 00168 @note The burst mode is possible only if the address Increment mode is enabled. 00169 00170 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ 00171 00172 } LL_DMA_InitTypeDef; 00173 /** 00174 * @} 00175 */ 00176 #endif /*USE_FULL_LL_DRIVER*/ 00177 /* Exported constants --------------------------------------------------------*/ 00178 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 00179 * @{ 00180 */ 00181 00182 /** @defgroup DMA_LL_EC_STREAM STREAM 00183 * @{ 00184 */ 00185 #define LL_DMA_STREAM_0 0x00000000U 00186 #define LL_DMA_STREAM_1 0x00000001U 00187 #define LL_DMA_STREAM_2 0x00000002U 00188 #define LL_DMA_STREAM_3 0x00000003U 00189 #define LL_DMA_STREAM_4 0x00000004U 00190 #define LL_DMA_STREAM_5 0x00000005U 00191 #define LL_DMA_STREAM_6 0x00000006U 00192 #define LL_DMA_STREAM_7 0x00000007U 00193 #define LL_DMA_STREAM_ALL 0xFFFF0000U 00194 /** 00195 * @} 00196 */ 00197 00198 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION 00199 * @{ 00200 */ 00201 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 00202 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ 00203 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ 00204 /** 00205 * @} 00206 */ 00207 00208 /** @defgroup DMA_LL_EC_MODE MODE 00209 * @{ 00210 */ 00211 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ 00212 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ 00213 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ 00214 /** 00215 * @} 00216 */ 00217 00218 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE 00219 * @{ 00220 */ 00221 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ 00222 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ 00223 /** 00224 * @} 00225 */ 00226 00227 /** @defgroup DMA_LL_EC_PERIPH PERIPH 00228 * @{ 00229 */ 00230 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ 00231 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ 00232 /** 00233 * @} 00234 */ 00235 00236 /** @defgroup DMA_LL_EC_MEMORY MEMORY 00237 * @{ 00238 */ 00239 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ 00240 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ 00241 /** 00242 * @} 00243 */ 00244 00245 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN 00246 * @{ 00247 */ 00248 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 00249 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 00250 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 00251 /** 00252 * @} 00253 */ 00254 00255 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN 00256 * @{ 00257 */ 00258 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 00259 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 00260 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ 00261 /** 00262 * @} 00263 */ 00264 00265 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE 00266 * @{ 00267 */ 00268 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ 00269 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ 00270 /** 00271 * @} 00272 */ 00273 00274 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY 00275 * @{ 00276 */ 00277 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 00278 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ 00279 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ 00280 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ 00281 /** 00282 * @} 00283 */ 00284 00285 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL 00286 * @{ 00287 */ 00288 #define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */ 00289 #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */ 00290 #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */ 00291 #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */ 00292 #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */ 00293 #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */ 00294 #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */ 00295 #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */ 00296 #if defined (DMA_SxCR_CHSEL_3) 00297 #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */ 00298 #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */ 00299 #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */ 00300 #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */ 00301 #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */ 00302 #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */ 00303 #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */ 00304 #define LL_DMA_CHANNEL_15 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel15 of DMA Instance */ 00305 #endif /* DMA_SxCR_CHSEL_3 */ 00306 /** 00307 * @} 00308 */ 00309 00310 /** @defgroup DMA_LL_EC_MBURST MBURST 00311 * @{ 00312 */ 00313 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ 00314 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ 00315 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ 00316 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ 00317 /** 00318 * @} 00319 */ 00320 00321 /** @defgroup DMA_LL_EC_PBURST PBURST 00322 * @{ 00323 */ 00324 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ 00325 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ 00326 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ 00327 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ 00328 /** 00329 * @} 00330 */ 00331 00332 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE 00333 * @{ 00334 */ 00335 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ 00336 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ 00337 /** 00338 * @} 00339 */ 00340 00341 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 00342 * @{ 00343 */ 00344 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ 00345 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ 00346 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ 00347 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ 00348 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ 00349 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ 00350 /** 00351 * @} 00352 */ 00353 00354 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD 00355 * @{ 00356 */ 00357 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ 00358 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ 00359 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ 00360 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ 00361 /** 00362 * @} 00363 */ 00364 00365 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM 00366 * @{ 00367 */ 00368 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ 00369 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ 00370 /** 00371 * @} 00372 */ 00373 00374 /** 00375 * @} 00376 */ 00377 00378 /* Exported macro ------------------------------------------------------------*/ 00379 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 00380 * @{ 00381 */ 00382 00383 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 00384 * @{ 00385 */ 00386 /** 00387 * @brief Write a value in DMA register 00388 * @param __INSTANCE__ DMA Instance 00389 * @param __REG__ Register to be written 00390 * @param __VALUE__ Value to be written in the register 00391 * @retval None 00392 */ 00393 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00394 00395 /** 00396 * @brief Read a value in DMA register 00397 * @param __INSTANCE__ DMA Instance 00398 * @param __REG__ Register to be read 00399 * @retval Register value 00400 */ 00401 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00402 /** 00403 * @} 00404 */ 00405 00406 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy 00407 * @{ 00408 */ 00409 /** 00410 * @brief Convert DMAx_Streamy into DMAx 00411 * @param __STREAM_INSTANCE__ DMAx_Streamy 00412 * @retval DMAx 00413 */ 00414 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ 00415 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) 00416 00417 /** 00418 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y 00419 * @param __STREAM_INSTANCE__ DMAx_Streamy 00420 * @retval LL_DMA_CHANNEL_y 00421 */ 00422 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ 00423 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ 00424 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ 00425 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ 00426 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ 00427 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ 00428 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ 00429 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ 00430 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ 00431 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ 00432 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ 00433 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ 00434 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ 00435 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ 00436 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ 00437 LL_DMA_STREAM_7) 00438 00439 /** 00440 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy 00441 * @param __DMA_INSTANCE__ DMAx 00442 * @param __STREAM__ LL_DMA_STREAM_y 00443 * @retval DMAx_Streamy 00444 */ 00445 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ 00446 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ 00447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ 00448 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ 00449 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ 00450 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ 00451 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ 00452 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ 00453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ 00454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ 00455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ 00456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ 00457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ 00458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ 00459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ 00460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ 00461 DMA2_Stream7) 00462 00463 /** 00464 * @} 00465 */ 00466 00467 /** 00468 * @} 00469 */ 00470 00471 00472 /* Exported functions --------------------------------------------------------*/ 00473 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 00474 * @{ 00475 */ 00476 00477 /** @defgroup DMA_LL_EF_Configuration Configuration 00478 * @{ 00479 */ 00480 /** 00481 * @brief Enable DMA stream. 00482 * @rmtoll CR EN LL_DMA_EnableStream 00483 * @param DMAx DMAx Instance 00484 * @param Stream This parameter can be one of the following values: 00485 * @arg @ref LL_DMA_STREAM_0 00486 * @arg @ref LL_DMA_STREAM_1 00487 * @arg @ref LL_DMA_STREAM_2 00488 * @arg @ref LL_DMA_STREAM_3 00489 * @arg @ref LL_DMA_STREAM_4 00490 * @arg @ref LL_DMA_STREAM_5 00491 * @arg @ref LL_DMA_STREAM_6 00492 * @arg @ref LL_DMA_STREAM_7 00493 * @retval None 00494 */ 00495 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) 00496 { 00497 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); 00498 } 00499 00500 /** 00501 * @brief Disable DMA stream. 00502 * @rmtoll CR EN LL_DMA_DisableStream 00503 * @param DMAx DMAx Instance 00504 * @param Stream This parameter can be one of the following values: 00505 * @arg @ref LL_DMA_STREAM_0 00506 * @arg @ref LL_DMA_STREAM_1 00507 * @arg @ref LL_DMA_STREAM_2 00508 * @arg @ref LL_DMA_STREAM_3 00509 * @arg @ref LL_DMA_STREAM_4 00510 * @arg @ref LL_DMA_STREAM_5 00511 * @arg @ref LL_DMA_STREAM_6 00512 * @arg @ref LL_DMA_STREAM_7 00513 * @retval None 00514 */ 00515 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) 00516 { 00517 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); 00518 } 00519 00520 /** 00521 * @brief Check if DMA stream is enabled or disabled. 00522 * @rmtoll CR EN LL_DMA_IsEnabledStream 00523 * @param DMAx DMAx Instance 00524 * @param Stream This parameter can be one of the following values: 00525 * @arg @ref LL_DMA_STREAM_0 00526 * @arg @ref LL_DMA_STREAM_1 00527 * @arg @ref LL_DMA_STREAM_2 00528 * @arg @ref LL_DMA_STREAM_3 00529 * @arg @ref LL_DMA_STREAM_4 00530 * @arg @ref LL_DMA_STREAM_5 00531 * @arg @ref LL_DMA_STREAM_6 00532 * @arg @ref LL_DMA_STREAM_7 00533 * @retval State of bit (1 or 0). 00534 */ 00535 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) 00536 { 00537 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); 00538 } 00539 00540 /** 00541 * @brief Configure all parameters linked to DMA transfer. 00542 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n 00543 * CR CIRC LL_DMA_ConfigTransfer\n 00544 * CR PINC LL_DMA_ConfigTransfer\n 00545 * CR MINC LL_DMA_ConfigTransfer\n 00546 * CR PSIZE LL_DMA_ConfigTransfer\n 00547 * CR MSIZE LL_DMA_ConfigTransfer\n 00548 * CR PL LL_DMA_ConfigTransfer\n 00549 * CR PFCTRL LL_DMA_ConfigTransfer 00550 * @param DMAx DMAx Instance 00551 * @param Stream This parameter can be one of the following values: 00552 * @arg @ref LL_DMA_STREAM_0 00553 * @arg @ref LL_DMA_STREAM_1 00554 * @arg @ref LL_DMA_STREAM_2 00555 * @arg @ref LL_DMA_STREAM_3 00556 * @arg @ref LL_DMA_STREAM_4 00557 * @arg @ref LL_DMA_STREAM_5 00558 * @arg @ref LL_DMA_STREAM_6 00559 * @arg @ref LL_DMA_STREAM_7 00560 * @param Configuration This parameter must be a combination of all the following values: 00561 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00562 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL 00563 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 00564 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 00565 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD 00566 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD 00567 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH 00568 *@retval None 00569 */ 00570 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) 00571 { 00572 MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 00573 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, 00574 Configuration); 00575 } 00576 00577 /** 00578 * @brief Set Data transfer direction (read from peripheral or from memory). 00579 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection 00580 * @param DMAx DMAx Instance 00581 * @param Stream This parameter can be one of the following values: 00582 * @arg @ref LL_DMA_STREAM_0 00583 * @arg @ref LL_DMA_STREAM_1 00584 * @arg @ref LL_DMA_STREAM_2 00585 * @arg @ref LL_DMA_STREAM_3 00586 * @arg @ref LL_DMA_STREAM_4 00587 * @arg @ref LL_DMA_STREAM_5 00588 * @arg @ref LL_DMA_STREAM_6 00589 * @arg @ref LL_DMA_STREAM_7 00590 * @param Direction This parameter can be one of the following values: 00591 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00592 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00593 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00594 * @retval None 00595 */ 00596 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) 00597 { 00598 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction); 00599 } 00600 00601 /** 00602 * @brief Get Data transfer direction (read from peripheral or from memory). 00603 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection 00604 * @param DMAx DMAx Instance 00605 * @param Stream This parameter can be one of the following values: 00606 * @arg @ref LL_DMA_STREAM_0 00607 * @arg @ref LL_DMA_STREAM_1 00608 * @arg @ref LL_DMA_STREAM_2 00609 * @arg @ref LL_DMA_STREAM_3 00610 * @arg @ref LL_DMA_STREAM_4 00611 * @arg @ref LL_DMA_STREAM_5 00612 * @arg @ref LL_DMA_STREAM_6 00613 * @arg @ref LL_DMA_STREAM_7 00614 * @retval Returned value can be one of the following values: 00615 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00616 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00617 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00618 */ 00619 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) 00620 { 00621 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR)); 00622 } 00623 00624 /** 00625 * @brief Set DMA mode normal, circular or peripheral flow control. 00626 * @rmtoll CR CIRC LL_DMA_SetMode\n 00627 * CR PFCTRL LL_DMA_SetMode 00628 * @param DMAx DMAx Instance 00629 * @param Stream This parameter can be one of the following values: 00630 * @arg @ref LL_DMA_STREAM_0 00631 * @arg @ref LL_DMA_STREAM_1 00632 * @arg @ref LL_DMA_STREAM_2 00633 * @arg @ref LL_DMA_STREAM_3 00634 * @arg @ref LL_DMA_STREAM_4 00635 * @arg @ref LL_DMA_STREAM_5 00636 * @arg @ref LL_DMA_STREAM_6 00637 * @arg @ref LL_DMA_STREAM_7 00638 * @param Mode This parameter can be one of the following values: 00639 * @arg @ref LL_DMA_MODE_NORMAL 00640 * @arg @ref LL_DMA_MODE_CIRCULAR 00641 * @arg @ref LL_DMA_MODE_PFCTRL 00642 * @retval None 00643 */ 00644 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) 00645 { 00646 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); 00647 } 00648 00649 /** 00650 * @brief Get DMA mode normal, circular or peripheral flow control. 00651 * @rmtoll CR CIRC LL_DMA_GetMode\n 00652 * CR PFCTRL LL_DMA_GetMode 00653 * @param DMAx DMAx Instance 00654 * @param Stream This parameter can be one of the following values: 00655 * @arg @ref LL_DMA_STREAM_0 00656 * @arg @ref LL_DMA_STREAM_1 00657 * @arg @ref LL_DMA_STREAM_2 00658 * @arg @ref LL_DMA_STREAM_3 00659 * @arg @ref LL_DMA_STREAM_4 00660 * @arg @ref LL_DMA_STREAM_5 00661 * @arg @ref LL_DMA_STREAM_6 00662 * @arg @ref LL_DMA_STREAM_7 00663 * @retval Returned value can be one of the following values: 00664 * @arg @ref LL_DMA_MODE_NORMAL 00665 * @arg @ref LL_DMA_MODE_CIRCULAR 00666 * @arg @ref LL_DMA_MODE_PFCTRL 00667 */ 00668 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) 00669 { 00670 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); 00671 } 00672 00673 /** 00674 * @brief Set Peripheral increment mode. 00675 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode 00676 * @param DMAx DMAx Instance 00677 * @param Stream This parameter can be one of the following values: 00678 * @arg @ref LL_DMA_STREAM_0 00679 * @arg @ref LL_DMA_STREAM_1 00680 * @arg @ref LL_DMA_STREAM_2 00681 * @arg @ref LL_DMA_STREAM_3 00682 * @arg @ref LL_DMA_STREAM_4 00683 * @arg @ref LL_DMA_STREAM_5 00684 * @arg @ref LL_DMA_STREAM_6 00685 * @arg @ref LL_DMA_STREAM_7 00686 * @param IncrementMode This parameter can be one of the following values: 00687 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 00688 * @arg @ref LL_DMA_PERIPH_INCREMENT 00689 * @retval None 00690 */ 00691 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) 00692 { 00693 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode); 00694 } 00695 00696 /** 00697 * @brief Get Peripheral increment mode. 00698 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode 00699 * @param DMAx DMAx Instance 00700 * @param Stream This parameter can be one of the following values: 00701 * @arg @ref LL_DMA_STREAM_0 00702 * @arg @ref LL_DMA_STREAM_1 00703 * @arg @ref LL_DMA_STREAM_2 00704 * @arg @ref LL_DMA_STREAM_3 00705 * @arg @ref LL_DMA_STREAM_4 00706 * @arg @ref LL_DMA_STREAM_5 00707 * @arg @ref LL_DMA_STREAM_6 00708 * @arg @ref LL_DMA_STREAM_7 00709 * @retval Returned value can be one of the following values: 00710 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 00711 * @arg @ref LL_DMA_PERIPH_INCREMENT 00712 */ 00713 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 00714 { 00715 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC)); 00716 } 00717 00718 /** 00719 * @brief Set Memory increment mode. 00720 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode 00721 * @param DMAx DMAx Instance 00722 * @param Stream This parameter can be one of the following values: 00723 * @arg @ref LL_DMA_STREAM_0 00724 * @arg @ref LL_DMA_STREAM_1 00725 * @arg @ref LL_DMA_STREAM_2 00726 * @arg @ref LL_DMA_STREAM_3 00727 * @arg @ref LL_DMA_STREAM_4 00728 * @arg @ref LL_DMA_STREAM_5 00729 * @arg @ref LL_DMA_STREAM_6 00730 * @arg @ref LL_DMA_STREAM_7 00731 * @param IncrementMode This parameter can be one of the following values: 00732 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 00733 * @arg @ref LL_DMA_MEMORY_INCREMENT 00734 * @retval None 00735 */ 00736 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) 00737 { 00738 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode); 00739 } 00740 00741 /** 00742 * @brief Get Memory increment mode. 00743 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode 00744 * @param DMAx DMAx Instance 00745 * @param Stream This parameter can be one of the following values: 00746 * @arg @ref LL_DMA_STREAM_0 00747 * @arg @ref LL_DMA_STREAM_1 00748 * @arg @ref LL_DMA_STREAM_2 00749 * @arg @ref LL_DMA_STREAM_3 00750 * @arg @ref LL_DMA_STREAM_4 00751 * @arg @ref LL_DMA_STREAM_5 00752 * @arg @ref LL_DMA_STREAM_6 00753 * @arg @ref LL_DMA_STREAM_7 00754 * @retval Returned value can be one of the following values: 00755 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 00756 * @arg @ref LL_DMA_MEMORY_INCREMENT 00757 */ 00758 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 00759 { 00760 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC)); 00761 } 00762 00763 /** 00764 * @brief Set Peripheral size. 00765 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize 00766 * @param DMAx DMAx Instance 00767 * @param Stream This parameter can be one of the following values: 00768 * @arg @ref LL_DMA_STREAM_0 00769 * @arg @ref LL_DMA_STREAM_1 00770 * @arg @ref LL_DMA_STREAM_2 00771 * @arg @ref LL_DMA_STREAM_3 00772 * @arg @ref LL_DMA_STREAM_4 00773 * @arg @ref LL_DMA_STREAM_5 00774 * @arg @ref LL_DMA_STREAM_6 00775 * @arg @ref LL_DMA_STREAM_7 00776 * @param Size This parameter can be one of the following values: 00777 * @arg @ref LL_DMA_PDATAALIGN_BYTE 00778 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 00779 * @arg @ref LL_DMA_PDATAALIGN_WORD 00780 * @retval None 00781 */ 00782 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 00783 { 00784 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size); 00785 } 00786 00787 /** 00788 * @brief Get Peripheral size. 00789 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize 00790 * @param DMAx DMAx Instance 00791 * @param Stream This parameter can be one of the following values: 00792 * @arg @ref LL_DMA_STREAM_0 00793 * @arg @ref LL_DMA_STREAM_1 00794 * @arg @ref LL_DMA_STREAM_2 00795 * @arg @ref LL_DMA_STREAM_3 00796 * @arg @ref LL_DMA_STREAM_4 00797 * @arg @ref LL_DMA_STREAM_5 00798 * @arg @ref LL_DMA_STREAM_6 00799 * @arg @ref LL_DMA_STREAM_7 00800 * @retval Returned value can be one of the following values: 00801 * @arg @ref LL_DMA_PDATAALIGN_BYTE 00802 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 00803 * @arg @ref LL_DMA_PDATAALIGN_WORD 00804 */ 00805 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) 00806 { 00807 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE)); 00808 } 00809 00810 /** 00811 * @brief Set Memory size. 00812 * @rmtoll CR MSIZE LL_DMA_SetMemorySize 00813 * @param DMAx DMAx Instance 00814 * @param Stream This parameter can be one of the following values: 00815 * @arg @ref LL_DMA_STREAM_0 00816 * @arg @ref LL_DMA_STREAM_1 00817 * @arg @ref LL_DMA_STREAM_2 00818 * @arg @ref LL_DMA_STREAM_3 00819 * @arg @ref LL_DMA_STREAM_4 00820 * @arg @ref LL_DMA_STREAM_5 00821 * @arg @ref LL_DMA_STREAM_6 00822 * @arg @ref LL_DMA_STREAM_7 00823 * @param Size This parameter can be one of the following values: 00824 * @arg @ref LL_DMA_MDATAALIGN_BYTE 00825 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 00826 * @arg @ref LL_DMA_MDATAALIGN_WORD 00827 * @retval None 00828 */ 00829 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 00830 { 00831 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size); 00832 } 00833 00834 /** 00835 * @brief Get Memory size. 00836 * @rmtoll CR MSIZE LL_DMA_GetMemorySize 00837 * @param DMAx DMAx Instance 00838 * @param Stream This parameter can be one of the following values: 00839 * @arg @ref LL_DMA_STREAM_0 00840 * @arg @ref LL_DMA_STREAM_1 00841 * @arg @ref LL_DMA_STREAM_2 00842 * @arg @ref LL_DMA_STREAM_3 00843 * @arg @ref LL_DMA_STREAM_4 00844 * @arg @ref LL_DMA_STREAM_5 00845 * @arg @ref LL_DMA_STREAM_6 00846 * @arg @ref LL_DMA_STREAM_7 00847 * @retval Returned value can be one of the following values: 00848 * @arg @ref LL_DMA_MDATAALIGN_BYTE 00849 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 00850 * @arg @ref LL_DMA_MDATAALIGN_WORD 00851 */ 00852 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) 00853 { 00854 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE)); 00855 } 00856 00857 /** 00858 * @brief Set Peripheral increment offset size. 00859 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize 00860 * @param DMAx DMAx Instance 00861 * @param Stream This parameter can be one of the following values: 00862 * @arg @ref LL_DMA_STREAM_0 00863 * @arg @ref LL_DMA_STREAM_1 00864 * @arg @ref LL_DMA_STREAM_2 00865 * @arg @ref LL_DMA_STREAM_3 00866 * @arg @ref LL_DMA_STREAM_4 00867 * @arg @ref LL_DMA_STREAM_5 00868 * @arg @ref LL_DMA_STREAM_6 00869 * @arg @ref LL_DMA_STREAM_7 00870 * @param OffsetSize This parameter can be one of the following values: 00871 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 00872 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 00873 * @retval None 00874 */ 00875 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) 00876 { 00877 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize); 00878 } 00879 00880 /** 00881 * @brief Get Peripheral increment offset size. 00882 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize 00883 * @param DMAx DMAx Instance 00884 * @param Stream This parameter can be one of the following values: 00885 * @arg @ref LL_DMA_STREAM_0 00886 * @arg @ref LL_DMA_STREAM_1 00887 * @arg @ref LL_DMA_STREAM_2 00888 * @arg @ref LL_DMA_STREAM_3 00889 * @arg @ref LL_DMA_STREAM_4 00890 * @arg @ref LL_DMA_STREAM_5 00891 * @arg @ref LL_DMA_STREAM_6 00892 * @arg @ref LL_DMA_STREAM_7 00893 * @retval Returned value can be one of the following values: 00894 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 00895 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 00896 */ 00897 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) 00898 { 00899 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS)); 00900 } 00901 00902 /** 00903 * @brief Set Stream priority level. 00904 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel 00905 * @param DMAx DMAx Instance 00906 * @param Stream This parameter can be one of the following values: 00907 * @arg @ref LL_DMA_STREAM_0 00908 * @arg @ref LL_DMA_STREAM_1 00909 * @arg @ref LL_DMA_STREAM_2 00910 * @arg @ref LL_DMA_STREAM_3 00911 * @arg @ref LL_DMA_STREAM_4 00912 * @arg @ref LL_DMA_STREAM_5 00913 * @arg @ref LL_DMA_STREAM_6 00914 * @arg @ref LL_DMA_STREAM_7 00915 * @param Priority This parameter can be one of the following values: 00916 * @arg @ref LL_DMA_PRIORITY_LOW 00917 * @arg @ref LL_DMA_PRIORITY_MEDIUM 00918 * @arg @ref LL_DMA_PRIORITY_HIGH 00919 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 00920 * @retval None 00921 */ 00922 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) 00923 { 00924 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority); 00925 } 00926 00927 /** 00928 * @brief Get Stream priority level. 00929 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel 00930 * @param DMAx DMAx Instance 00931 * @param Stream This parameter can be one of the following values: 00932 * @arg @ref LL_DMA_STREAM_0 00933 * @arg @ref LL_DMA_STREAM_1 00934 * @arg @ref LL_DMA_STREAM_2 00935 * @arg @ref LL_DMA_STREAM_3 00936 * @arg @ref LL_DMA_STREAM_4 00937 * @arg @ref LL_DMA_STREAM_5 00938 * @arg @ref LL_DMA_STREAM_6 00939 * @arg @ref LL_DMA_STREAM_7 00940 * @retval Returned value can be one of the following values: 00941 * @arg @ref LL_DMA_PRIORITY_LOW 00942 * @arg @ref LL_DMA_PRIORITY_MEDIUM 00943 * @arg @ref LL_DMA_PRIORITY_HIGH 00944 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 00945 */ 00946 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) 00947 { 00948 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL)); 00949 } 00950 00951 /** 00952 * @brief Set Number of data to transfer. 00953 * @rmtoll NDTR NDT LL_DMA_SetDataLength 00954 * @note This action has no effect if 00955 * stream is enabled. 00956 * @param DMAx DMAx Instance 00957 * @param Stream This parameter can be one of the following values: 00958 * @arg @ref LL_DMA_STREAM_0 00959 * @arg @ref LL_DMA_STREAM_1 00960 * @arg @ref LL_DMA_STREAM_2 00961 * @arg @ref LL_DMA_STREAM_3 00962 * @arg @ref LL_DMA_STREAM_4 00963 * @arg @ref LL_DMA_STREAM_5 00964 * @arg @ref LL_DMA_STREAM_6 00965 * @arg @ref LL_DMA_STREAM_7 00966 * @param NbData Between 0 to 0xFFFFFFFF 00967 * @retval None 00968 */ 00969 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) 00970 { 00971 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData); 00972 } 00973 00974 /** 00975 * @brief Get Number of data to transfer. 00976 * @rmtoll NDTR NDT LL_DMA_GetDataLength 00977 * @note Once the stream is enabled, the return value indicate the 00978 * remaining bytes to be transmitted. 00979 * @param DMAx DMAx Instance 00980 * @param Stream This parameter can be one of the following values: 00981 * @arg @ref LL_DMA_STREAM_0 00982 * @arg @ref LL_DMA_STREAM_1 00983 * @arg @ref LL_DMA_STREAM_2 00984 * @arg @ref LL_DMA_STREAM_3 00985 * @arg @ref LL_DMA_STREAM_4 00986 * @arg @ref LL_DMA_STREAM_5 00987 * @arg @ref LL_DMA_STREAM_6 00988 * @arg @ref LL_DMA_STREAM_7 00989 * @retval Between 0 to 0xFFFFFFFF 00990 */ 00991 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) 00992 { 00993 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT)); 00994 } 00995 00996 /** 00997 * @brief Select Channel number associated to the Stream. 00998 * @rmtoll CR CHSEL LL_DMA_SetChannelSelection 00999 * @param DMAx DMAx Instance 01000 * @param Stream This parameter can be one of the following values: 01001 * @arg @ref LL_DMA_STREAM_0 01002 * @arg @ref LL_DMA_STREAM_1 01003 * @arg @ref LL_DMA_STREAM_2 01004 * @arg @ref LL_DMA_STREAM_3 01005 * @arg @ref LL_DMA_STREAM_4 01006 * @arg @ref LL_DMA_STREAM_5 01007 * @arg @ref LL_DMA_STREAM_6 01008 * @arg @ref LL_DMA_STREAM_7 01009 * @param Channel This parameter can be one of the following values: 01010 * @arg @ref LL_DMA_CHANNEL_0 01011 * @arg @ref LL_DMA_CHANNEL_1 01012 * @arg @ref LL_DMA_CHANNEL_2 01013 * @arg @ref LL_DMA_CHANNEL_3 01014 * @arg @ref LL_DMA_CHANNEL_4 01015 * @arg @ref LL_DMA_CHANNEL_5 01016 * @arg @ref LL_DMA_CHANNEL_6 01017 * @arg @ref LL_DMA_CHANNEL_7 01018 * @retval None 01019 */ 01020 __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel) 01021 { 01022 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel); 01023 } 01024 01025 /** 01026 * @brief Get the Channel number associated to the Stream. 01027 * @rmtoll CR CHSEL LL_DMA_GetChannelSelection 01028 * @param DMAx DMAx Instance 01029 * @param Stream This parameter can be one of the following values: 01030 * @arg @ref LL_DMA_STREAM_0 01031 * @arg @ref LL_DMA_STREAM_1 01032 * @arg @ref LL_DMA_STREAM_2 01033 * @arg @ref LL_DMA_STREAM_3 01034 * @arg @ref LL_DMA_STREAM_4 01035 * @arg @ref LL_DMA_STREAM_5 01036 * @arg @ref LL_DMA_STREAM_6 01037 * @arg @ref LL_DMA_STREAM_7 01038 * @retval Returned value can be one of the following values: 01039 * @arg @ref LL_DMA_CHANNEL_0 01040 * @arg @ref LL_DMA_CHANNEL_1 01041 * @arg @ref LL_DMA_CHANNEL_2 01042 * @arg @ref LL_DMA_CHANNEL_3 01043 * @arg @ref LL_DMA_CHANNEL_4 01044 * @arg @ref LL_DMA_CHANNEL_5 01045 * @arg @ref LL_DMA_CHANNEL_6 01046 * @arg @ref LL_DMA_CHANNEL_7 01047 */ 01048 __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) 01049 { 01050 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL)); 01051 } 01052 01053 /** 01054 * @brief Set Memory burst transfer configuration. 01055 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer 01056 * @param DMAx DMAx Instance 01057 * @param Stream This parameter can be one of the following values: 01058 * @arg @ref LL_DMA_STREAM_0 01059 * @arg @ref LL_DMA_STREAM_1 01060 * @arg @ref LL_DMA_STREAM_2 01061 * @arg @ref LL_DMA_STREAM_3 01062 * @arg @ref LL_DMA_STREAM_4 01063 * @arg @ref LL_DMA_STREAM_5 01064 * @arg @ref LL_DMA_STREAM_6 01065 * @arg @ref LL_DMA_STREAM_7 01066 * @param Mburst This parameter can be one of the following values: 01067 * @arg @ref LL_DMA_MBURST_SINGLE 01068 * @arg @ref LL_DMA_MBURST_INC4 01069 * @arg @ref LL_DMA_MBURST_INC8 01070 * @arg @ref LL_DMA_MBURST_INC16 01071 * @retval None 01072 */ 01073 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) 01074 { 01075 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst); 01076 } 01077 01078 /** 01079 * @brief Get Memory burst transfer configuration. 01080 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer 01081 * @param DMAx DMAx Instance 01082 * @param Stream This parameter can be one of the following values: 01083 * @arg @ref LL_DMA_STREAM_0 01084 * @arg @ref LL_DMA_STREAM_1 01085 * @arg @ref LL_DMA_STREAM_2 01086 * @arg @ref LL_DMA_STREAM_3 01087 * @arg @ref LL_DMA_STREAM_4 01088 * @arg @ref LL_DMA_STREAM_5 01089 * @arg @ref LL_DMA_STREAM_6 01090 * @arg @ref LL_DMA_STREAM_7 01091 * @retval Returned value can be one of the following values: 01092 * @arg @ref LL_DMA_MBURST_SINGLE 01093 * @arg @ref LL_DMA_MBURST_INC4 01094 * @arg @ref LL_DMA_MBURST_INC8 01095 * @arg @ref LL_DMA_MBURST_INC16 01096 */ 01097 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 01098 { 01099 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST)); 01100 } 01101 01102 /** 01103 * @brief Set Peripheral burst transfer configuration. 01104 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer 01105 * @param DMAx DMAx Instance 01106 * @param Stream This parameter can be one of the following values: 01107 * @arg @ref LL_DMA_STREAM_0 01108 * @arg @ref LL_DMA_STREAM_1 01109 * @arg @ref LL_DMA_STREAM_2 01110 * @arg @ref LL_DMA_STREAM_3 01111 * @arg @ref LL_DMA_STREAM_4 01112 * @arg @ref LL_DMA_STREAM_5 01113 * @arg @ref LL_DMA_STREAM_6 01114 * @arg @ref LL_DMA_STREAM_7 01115 * @param Pburst This parameter can be one of the following values: 01116 * @arg @ref LL_DMA_PBURST_SINGLE 01117 * @arg @ref LL_DMA_PBURST_INC4 01118 * @arg @ref LL_DMA_PBURST_INC8 01119 * @arg @ref LL_DMA_PBURST_INC16 01120 * @retval None 01121 */ 01122 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) 01123 { 01124 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst); 01125 } 01126 01127 /** 01128 * @brief Get Peripheral burst transfer configuration. 01129 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer 01130 * @param DMAx DMAx Instance 01131 * @param Stream This parameter can be one of the following values: 01132 * @arg @ref LL_DMA_STREAM_0 01133 * @arg @ref LL_DMA_STREAM_1 01134 * @arg @ref LL_DMA_STREAM_2 01135 * @arg @ref LL_DMA_STREAM_3 01136 * @arg @ref LL_DMA_STREAM_4 01137 * @arg @ref LL_DMA_STREAM_5 01138 * @arg @ref LL_DMA_STREAM_6 01139 * @arg @ref LL_DMA_STREAM_7 01140 * @retval Returned value can be one of the following values: 01141 * @arg @ref LL_DMA_PBURST_SINGLE 01142 * @arg @ref LL_DMA_PBURST_INC4 01143 * @arg @ref LL_DMA_PBURST_INC8 01144 * @arg @ref LL_DMA_PBURST_INC16 01145 */ 01146 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 01147 { 01148 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST)); 01149 } 01150 01151 /** 01152 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 01153 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem 01154 * @param DMAx DMAx Instance 01155 * @param Stream This parameter can be one of the following values: 01156 * @arg @ref LL_DMA_STREAM_0 01157 * @arg @ref LL_DMA_STREAM_1 01158 * @arg @ref LL_DMA_STREAM_2 01159 * @arg @ref LL_DMA_STREAM_3 01160 * @arg @ref LL_DMA_STREAM_4 01161 * @arg @ref LL_DMA_STREAM_5 01162 * @arg @ref LL_DMA_STREAM_6 01163 * @arg @ref LL_DMA_STREAM_7 01164 * @param CurrentMemory This parameter can be one of the following values: 01165 * @arg @ref LL_DMA_CURRENTTARGETMEM0 01166 * @arg @ref LL_DMA_CURRENTTARGETMEM1 01167 * @retval None 01168 */ 01169 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) 01170 { 01171 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory); 01172 } 01173 01174 /** 01175 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 01176 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem 01177 * @param DMAx DMAx Instance 01178 * @param Stream This parameter can be one of the following values: 01179 * @arg @ref LL_DMA_STREAM_0 01180 * @arg @ref LL_DMA_STREAM_1 01181 * @arg @ref LL_DMA_STREAM_2 01182 * @arg @ref LL_DMA_STREAM_3 01183 * @arg @ref LL_DMA_STREAM_4 01184 * @arg @ref LL_DMA_STREAM_5 01185 * @arg @ref LL_DMA_STREAM_6 01186 * @arg @ref LL_DMA_STREAM_7 01187 * @retval Returned value can be one of the following values: 01188 * @arg @ref LL_DMA_CURRENTTARGETMEM0 01189 * @arg @ref LL_DMA_CURRENTTARGETMEM1 01190 */ 01191 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) 01192 { 01193 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT)); 01194 } 01195 01196 /** 01197 * @brief Enable the double buffer mode. 01198 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode 01199 * @param DMAx DMAx Instance 01200 * @param Stream This parameter can be one of the following values: 01201 * @arg @ref LL_DMA_STREAM_0 01202 * @arg @ref LL_DMA_STREAM_1 01203 * @arg @ref LL_DMA_STREAM_2 01204 * @arg @ref LL_DMA_STREAM_3 01205 * @arg @ref LL_DMA_STREAM_4 01206 * @arg @ref LL_DMA_STREAM_5 01207 * @arg @ref LL_DMA_STREAM_6 01208 * @arg @ref LL_DMA_STREAM_7 01209 * @retval None 01210 */ 01211 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 01212 { 01213 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); 01214 } 01215 01216 /** 01217 * @brief Disable the double buffer mode. 01218 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode 01219 * @param DMAx DMAx Instance 01220 * @param Stream This parameter can be one of the following values: 01221 * @arg @ref LL_DMA_STREAM_0 01222 * @arg @ref LL_DMA_STREAM_1 01223 * @arg @ref LL_DMA_STREAM_2 01224 * @arg @ref LL_DMA_STREAM_3 01225 * @arg @ref LL_DMA_STREAM_4 01226 * @arg @ref LL_DMA_STREAM_5 01227 * @arg @ref LL_DMA_STREAM_6 01228 * @arg @ref LL_DMA_STREAM_7 01229 * @retval None 01230 */ 01231 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 01232 { 01233 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); 01234 } 01235 01236 /** 01237 * @brief Get FIFO status. 01238 * @rmtoll FCR FS LL_DMA_GetFIFOStatus 01239 * @param DMAx DMAx Instance 01240 * @param Stream This parameter can be one of the following values: 01241 * @arg @ref LL_DMA_STREAM_0 01242 * @arg @ref LL_DMA_STREAM_1 01243 * @arg @ref LL_DMA_STREAM_2 01244 * @arg @ref LL_DMA_STREAM_3 01245 * @arg @ref LL_DMA_STREAM_4 01246 * @arg @ref LL_DMA_STREAM_5 01247 * @arg @ref LL_DMA_STREAM_6 01248 * @arg @ref LL_DMA_STREAM_7 01249 * @retval Returned value can be one of the following values: 01250 * @arg @ref LL_DMA_FIFOSTATUS_0_25 01251 * @arg @ref LL_DMA_FIFOSTATUS_25_50 01252 * @arg @ref LL_DMA_FIFOSTATUS_50_75 01253 * @arg @ref LL_DMA_FIFOSTATUS_75_100 01254 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY 01255 * @arg @ref LL_DMA_FIFOSTATUS_FULL 01256 */ 01257 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) 01258 { 01259 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); 01260 } 01261 01262 /** 01263 * @brief Disable Fifo mode. 01264 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode 01265 * @param DMAx DMAx Instance 01266 * @param Stream This parameter can be one of the following values: 01267 * @arg @ref LL_DMA_STREAM_0 01268 * @arg @ref LL_DMA_STREAM_1 01269 * @arg @ref LL_DMA_STREAM_2 01270 * @arg @ref LL_DMA_STREAM_3 01271 * @arg @ref LL_DMA_STREAM_4 01272 * @arg @ref LL_DMA_STREAM_5 01273 * @arg @ref LL_DMA_STREAM_6 01274 * @arg @ref LL_DMA_STREAM_7 01275 * @retval None 01276 */ 01277 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 01278 { 01279 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); 01280 } 01281 01282 /** 01283 * @brief Enable Fifo mode. 01284 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode 01285 * @param DMAx DMAx Instance 01286 * @param Stream This parameter can be one of the following values: 01287 * @arg @ref LL_DMA_STREAM_0 01288 * @arg @ref LL_DMA_STREAM_1 01289 * @arg @ref LL_DMA_STREAM_2 01290 * @arg @ref LL_DMA_STREAM_3 01291 * @arg @ref LL_DMA_STREAM_4 01292 * @arg @ref LL_DMA_STREAM_5 01293 * @arg @ref LL_DMA_STREAM_6 01294 * @arg @ref LL_DMA_STREAM_7 01295 * @retval None 01296 */ 01297 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 01298 { 01299 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); 01300 } 01301 01302 /** 01303 * @brief Select FIFO threshold. 01304 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold 01305 * @param DMAx DMAx Instance 01306 * @param Stream This parameter can be one of the following values: 01307 * @arg @ref LL_DMA_STREAM_0 01308 * @arg @ref LL_DMA_STREAM_1 01309 * @arg @ref LL_DMA_STREAM_2 01310 * @arg @ref LL_DMA_STREAM_3 01311 * @arg @ref LL_DMA_STREAM_4 01312 * @arg @ref LL_DMA_STREAM_5 01313 * @arg @ref LL_DMA_STREAM_6 01314 * @arg @ref LL_DMA_STREAM_7 01315 * @param Threshold This parameter can be one of the following values: 01316 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 01317 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 01318 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 01319 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 01320 * @retval None 01321 */ 01322 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) 01323 { 01324 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold); 01325 } 01326 01327 /** 01328 * @brief Get FIFO threshold. 01329 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold 01330 * @param DMAx DMAx Instance 01331 * @param Stream This parameter can be one of the following values: 01332 * @arg @ref LL_DMA_STREAM_0 01333 * @arg @ref LL_DMA_STREAM_1 01334 * @arg @ref LL_DMA_STREAM_2 01335 * @arg @ref LL_DMA_STREAM_3 01336 * @arg @ref LL_DMA_STREAM_4 01337 * @arg @ref LL_DMA_STREAM_5 01338 * @arg @ref LL_DMA_STREAM_6 01339 * @arg @ref LL_DMA_STREAM_7 01340 * @retval Returned value can be one of the following values: 01341 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 01342 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 01343 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 01344 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 01345 */ 01346 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) 01347 { 01348 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); 01349 } 01350 01351 /** 01352 * @brief Configure the FIFO . 01353 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n 01354 * FCR DMDIS LL_DMA_ConfigFifo 01355 * @param DMAx DMAx Instance 01356 * @param Stream This parameter can be one of the following values: 01357 * @arg @ref LL_DMA_STREAM_0 01358 * @arg @ref LL_DMA_STREAM_1 01359 * @arg @ref LL_DMA_STREAM_2 01360 * @arg @ref LL_DMA_STREAM_3 01361 * @arg @ref LL_DMA_STREAM_4 01362 * @arg @ref LL_DMA_STREAM_5 01363 * @arg @ref LL_DMA_STREAM_6 01364 * @arg @ref LL_DMA_STREAM_7 01365 * @param FifoMode This parameter can be one of the following values: 01366 * @arg @ref LL_DMA_FIFOMODE_ENABLE 01367 * @arg @ref LL_DMA_FIFOMODE_DISABLE 01368 * @param FifoThreshold This parameter can be one of the following values: 01369 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 01370 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 01371 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 01372 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 01373 * @retval None 01374 */ 01375 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) 01376 { 01377 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); 01378 } 01379 01380 /** 01381 * @brief Configure the Source and Destination addresses. 01382 * @note This API must not be called when the DMA stream is enabled. 01383 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n 01384 * PAR PA LL_DMA_ConfigAddresses 01385 * @param DMAx DMAx Instance 01386 * @param Stream This parameter can be one of the following values: 01387 * @arg @ref LL_DMA_STREAM_0 01388 * @arg @ref LL_DMA_STREAM_1 01389 * @arg @ref LL_DMA_STREAM_2 01390 * @arg @ref LL_DMA_STREAM_3 01391 * @arg @ref LL_DMA_STREAM_4 01392 * @arg @ref LL_DMA_STREAM_5 01393 * @arg @ref LL_DMA_STREAM_6 01394 * @arg @ref LL_DMA_STREAM_7 01395 * @param SrcAddress Between 0 to 0xFFFFFFFF 01396 * @param DstAddress Between 0 to 0xFFFFFFFF 01397 * @param Direction This parameter can be one of the following values: 01398 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 01399 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 01400 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 01401 * @retval None 01402 */ 01403 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) 01404 { 01405 /* Direction Memory to Periph */ 01406 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) 01407 { 01408 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress); 01409 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress); 01410 } 01411 /* Direction Periph to Memory and Memory to Memory */ 01412 else 01413 { 01414 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress); 01415 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress); 01416 } 01417 } 01418 01419 /** 01420 * @brief Set the Memory address. 01421 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress 01422 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01423 * @note This API must not be called when the DMA channel is enabled. 01424 * @param DMAx DMAx Instance 01425 * @param Stream This parameter can be one of the following values: 01426 * @arg @ref LL_DMA_STREAM_0 01427 * @arg @ref LL_DMA_STREAM_1 01428 * @arg @ref LL_DMA_STREAM_2 01429 * @arg @ref LL_DMA_STREAM_3 01430 * @arg @ref LL_DMA_STREAM_4 01431 * @arg @ref LL_DMA_STREAM_5 01432 * @arg @ref LL_DMA_STREAM_6 01433 * @arg @ref LL_DMA_STREAM_7 01434 * @param MemoryAddress Between 0 to 0xFFFFFFFF 01435 * @retval None 01436 */ 01437 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) 01438 { 01439 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); 01440 } 01441 01442 /** 01443 * @brief Set the Peripheral address. 01444 * @rmtoll PAR PA LL_DMA_SetPeriphAddress 01445 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01446 * @note This API must not be called when the DMA channel is enabled. 01447 * @param DMAx DMAx Instance 01448 * @param Stream This parameter can be one of the following values: 01449 * @arg @ref LL_DMA_STREAM_0 01450 * @arg @ref LL_DMA_STREAM_1 01451 * @arg @ref LL_DMA_STREAM_2 01452 * @arg @ref LL_DMA_STREAM_3 01453 * @arg @ref LL_DMA_STREAM_4 01454 * @arg @ref LL_DMA_STREAM_5 01455 * @arg @ref LL_DMA_STREAM_6 01456 * @arg @ref LL_DMA_STREAM_7 01457 * @param PeriphAddress Between 0 to 0xFFFFFFFF 01458 * @retval None 01459 */ 01460 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress) 01461 { 01462 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress); 01463 } 01464 01465 /** 01466 * @brief Get the Memory address. 01467 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress 01468 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01469 * @param DMAx DMAx Instance 01470 * @param Stream This parameter can be one of the following values: 01471 * @arg @ref LL_DMA_STREAM_0 01472 * @arg @ref LL_DMA_STREAM_1 01473 * @arg @ref LL_DMA_STREAM_2 01474 * @arg @ref LL_DMA_STREAM_3 01475 * @arg @ref LL_DMA_STREAM_4 01476 * @arg @ref LL_DMA_STREAM_5 01477 * @arg @ref LL_DMA_STREAM_6 01478 * @arg @ref LL_DMA_STREAM_7 01479 * @retval Between 0 to 0xFFFFFFFF 01480 */ 01481 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) 01482 { 01483 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); 01484 } 01485 01486 /** 01487 * @brief Get the Peripheral address. 01488 * @rmtoll PAR PA LL_DMA_GetPeriphAddress 01489 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01490 * @param DMAx DMAx Instance 01491 * @param Stream This parameter can be one of the following values: 01492 * @arg @ref LL_DMA_STREAM_0 01493 * @arg @ref LL_DMA_STREAM_1 01494 * @arg @ref LL_DMA_STREAM_2 01495 * @arg @ref LL_DMA_STREAM_3 01496 * @arg @ref LL_DMA_STREAM_4 01497 * @arg @ref LL_DMA_STREAM_5 01498 * @arg @ref LL_DMA_STREAM_6 01499 * @arg @ref LL_DMA_STREAM_7 01500 * @retval Between 0 to 0xFFFFFFFF 01501 */ 01502 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) 01503 { 01504 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); 01505 } 01506 01507 /** 01508 * @brief Set the Memory to Memory Source address. 01509 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress 01510 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01511 * @note This API must not be called when the DMA channel is enabled. 01512 * @param DMAx DMAx Instance 01513 * @param Stream This parameter can be one of the following values: 01514 * @arg @ref LL_DMA_STREAM_0 01515 * @arg @ref LL_DMA_STREAM_1 01516 * @arg @ref LL_DMA_STREAM_2 01517 * @arg @ref LL_DMA_STREAM_3 01518 * @arg @ref LL_DMA_STREAM_4 01519 * @arg @ref LL_DMA_STREAM_5 01520 * @arg @ref LL_DMA_STREAM_6 01521 * @arg @ref LL_DMA_STREAM_7 01522 * @param MemoryAddress Between 0 to 0xFFFFFFFF 01523 * @retval None 01524 */ 01525 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) 01526 { 01527 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress); 01528 } 01529 01530 /** 01531 * @brief Set the Memory to Memory Destination address. 01532 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress 01533 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01534 * @note This API must not be called when the DMA channel is enabled. 01535 * @param DMAx DMAx Instance 01536 * @param Stream This parameter can be one of the following values: 01537 * @arg @ref LL_DMA_STREAM_0 01538 * @arg @ref LL_DMA_STREAM_1 01539 * @arg @ref LL_DMA_STREAM_2 01540 * @arg @ref LL_DMA_STREAM_3 01541 * @arg @ref LL_DMA_STREAM_4 01542 * @arg @ref LL_DMA_STREAM_5 01543 * @arg @ref LL_DMA_STREAM_6 01544 * @arg @ref LL_DMA_STREAM_7 01545 * @param MemoryAddress Between 0 to 0xFFFFFFFF 01546 * @retval None 01547 */ 01548 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) 01549 { 01550 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); 01551 } 01552 01553 /** 01554 * @brief Get the Memory to Memory Source address. 01555 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress 01556 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01557 * @param DMAx DMAx Instance 01558 * @param Stream This parameter can be one of the following values: 01559 * @arg @ref LL_DMA_STREAM_0 01560 * @arg @ref LL_DMA_STREAM_1 01561 * @arg @ref LL_DMA_STREAM_2 01562 * @arg @ref LL_DMA_STREAM_3 01563 * @arg @ref LL_DMA_STREAM_4 01564 * @arg @ref LL_DMA_STREAM_5 01565 * @arg @ref LL_DMA_STREAM_6 01566 * @arg @ref LL_DMA_STREAM_7 01567 * @retval Between 0 to 0xFFFFFFFF 01568 */ 01569 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) 01570 { 01571 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); 01572 } 01573 01574 /** 01575 * @brief Get the Memory to Memory Destination address. 01576 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress 01577 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01578 * @param DMAx DMAx Instance 01579 * @param Stream This parameter can be one of the following values: 01580 * @arg @ref LL_DMA_STREAM_0 01581 * @arg @ref LL_DMA_STREAM_1 01582 * @arg @ref LL_DMA_STREAM_2 01583 * @arg @ref LL_DMA_STREAM_3 01584 * @arg @ref LL_DMA_STREAM_4 01585 * @arg @ref LL_DMA_STREAM_5 01586 * @arg @ref LL_DMA_STREAM_6 01587 * @arg @ref LL_DMA_STREAM_7 01588 * @retval Between 0 to 0xFFFFFFFF 01589 */ 01590 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) 01591 { 01592 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); 01593 } 01594 01595 /** 01596 * @brief Set Memory 1 address (used in case of Double buffer mode). 01597 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address 01598 * @param DMAx DMAx Instance 01599 * @param Stream This parameter can be one of the following values: 01600 * @arg @ref LL_DMA_STREAM_0 01601 * @arg @ref LL_DMA_STREAM_1 01602 * @arg @ref LL_DMA_STREAM_2 01603 * @arg @ref LL_DMA_STREAM_3 01604 * @arg @ref LL_DMA_STREAM_4 01605 * @arg @ref LL_DMA_STREAM_5 01606 * @arg @ref LL_DMA_STREAM_6 01607 * @arg @ref LL_DMA_STREAM_7 01608 * @param Address Between 0 to 0xFFFFFFFF 01609 * @retval None 01610 */ 01611 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) 01612 { 01613 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address); 01614 } 01615 01616 /** 01617 * @brief Get Memory 1 address (used in case of Double buffer mode). 01618 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address 01619 * @param DMAx DMAx Instance 01620 * @param Stream This parameter can be one of the following values: 01621 * @arg @ref LL_DMA_STREAM_0 01622 * @arg @ref LL_DMA_STREAM_1 01623 * @arg @ref LL_DMA_STREAM_2 01624 * @arg @ref LL_DMA_STREAM_3 01625 * @arg @ref LL_DMA_STREAM_4 01626 * @arg @ref LL_DMA_STREAM_5 01627 * @arg @ref LL_DMA_STREAM_6 01628 * @arg @ref LL_DMA_STREAM_7 01629 * @retval Between 0 to 0xFFFFFFFF 01630 */ 01631 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) 01632 { 01633 return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); 01634 } 01635 01636 /** 01637 * @} 01638 */ 01639 01640 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 01641 * @{ 01642 */ 01643 01644 /** 01645 * @brief Get Stream 0 half transfer flag. 01646 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 01647 * @param DMAx DMAx Instance 01648 * @retval State of bit (1 or 0). 01649 */ 01650 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) 01651 { 01652 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); 01653 } 01654 01655 /** 01656 * @brief Get Stream 1 half transfer flag. 01657 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 01658 * @param DMAx DMAx Instance 01659 * @retval State of bit (1 or 0). 01660 */ 01661 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) 01662 { 01663 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); 01664 } 01665 01666 /** 01667 * @brief Get Stream 2 half transfer flag. 01668 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 01669 * @param DMAx DMAx Instance 01670 * @retval State of bit (1 or 0). 01671 */ 01672 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) 01673 { 01674 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); 01675 } 01676 01677 /** 01678 * @brief Get Stream 3 half transfer flag. 01679 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 01680 * @param DMAx DMAx Instance 01681 * @retval State of bit (1 or 0). 01682 */ 01683 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) 01684 { 01685 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); 01686 } 01687 01688 /** 01689 * @brief Get Stream 4 half transfer flag. 01690 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 01691 * @param DMAx DMAx Instance 01692 * @retval State of bit (1 or 0). 01693 */ 01694 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) 01695 { 01696 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); 01697 } 01698 01699 /** 01700 * @brief Get Stream 5 half transfer flag. 01701 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 01702 * @param DMAx DMAx Instance 01703 * @retval State of bit (1 or 0). 01704 */ 01705 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) 01706 { 01707 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); 01708 } 01709 01710 /** 01711 * @brief Get Stream 6 half transfer flag. 01712 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 01713 * @param DMAx DMAx Instance 01714 * @retval State of bit (1 or 0). 01715 */ 01716 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) 01717 { 01718 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); 01719 } 01720 01721 /** 01722 * @brief Get Stream 7 half transfer flag. 01723 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 01724 * @param DMAx DMAx Instance 01725 * @retval State of bit (1 or 0). 01726 */ 01727 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) 01728 { 01729 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); 01730 } 01731 01732 /** 01733 * @brief Get Stream 0 transfer complete flag. 01734 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 01735 * @param DMAx DMAx Instance 01736 * @retval State of bit (1 or 0). 01737 */ 01738 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) 01739 { 01740 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); 01741 } 01742 01743 /** 01744 * @brief Get Stream 1 transfer complete flag. 01745 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 01746 * @param DMAx DMAx Instance 01747 * @retval State of bit (1 or 0). 01748 */ 01749 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) 01750 { 01751 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); 01752 } 01753 01754 /** 01755 * @brief Get Stream 2 transfer complete flag. 01756 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 01757 * @param DMAx DMAx Instance 01758 * @retval State of bit (1 or 0). 01759 */ 01760 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) 01761 { 01762 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); 01763 } 01764 01765 /** 01766 * @brief Get Stream 3 transfer complete flag. 01767 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 01768 * @param DMAx DMAx Instance 01769 * @retval State of bit (1 or 0). 01770 */ 01771 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) 01772 { 01773 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); 01774 } 01775 01776 /** 01777 * @brief Get Stream 4 transfer complete flag. 01778 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 01779 * @param DMAx DMAx Instance 01780 * @retval State of bit (1 or 0). 01781 */ 01782 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) 01783 { 01784 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); 01785 } 01786 01787 /** 01788 * @brief Get Stream 5 transfer complete flag. 01789 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 01790 * @param DMAx DMAx Instance 01791 * @retval State of bit (1 or 0). 01792 */ 01793 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) 01794 { 01795 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); 01796 } 01797 01798 /** 01799 * @brief Get Stream 6 transfer complete flag. 01800 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 01801 * @param DMAx DMAx Instance 01802 * @retval State of bit (1 or 0). 01803 */ 01804 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) 01805 { 01806 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); 01807 } 01808 01809 /** 01810 * @brief Get Stream 7 transfer complete flag. 01811 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 01812 * @param DMAx DMAx Instance 01813 * @retval State of bit (1 or 0). 01814 */ 01815 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) 01816 { 01817 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); 01818 } 01819 01820 /** 01821 * @brief Get Stream 0 transfer error flag. 01822 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 01823 * @param DMAx DMAx Instance 01824 * @retval State of bit (1 or 0). 01825 */ 01826 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) 01827 { 01828 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); 01829 } 01830 01831 /** 01832 * @brief Get Stream 1 transfer error flag. 01833 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 01834 * @param DMAx DMAx Instance 01835 * @retval State of bit (1 or 0). 01836 */ 01837 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) 01838 { 01839 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); 01840 } 01841 01842 /** 01843 * @brief Get Stream 2 transfer error flag. 01844 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 01845 * @param DMAx DMAx Instance 01846 * @retval State of bit (1 or 0). 01847 */ 01848 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) 01849 { 01850 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); 01851 } 01852 01853 /** 01854 * @brief Get Stream 3 transfer error flag. 01855 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 01856 * @param DMAx DMAx Instance 01857 * @retval State of bit (1 or 0). 01858 */ 01859 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) 01860 { 01861 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); 01862 } 01863 01864 /** 01865 * @brief Get Stream 4 transfer error flag. 01866 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 01867 * @param DMAx DMAx Instance 01868 * @retval State of bit (1 or 0). 01869 */ 01870 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) 01871 { 01872 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); 01873 } 01874 01875 /** 01876 * @brief Get Stream 5 transfer error flag. 01877 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 01878 * @param DMAx DMAx Instance 01879 * @retval State of bit (1 or 0). 01880 */ 01881 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) 01882 { 01883 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); 01884 } 01885 01886 /** 01887 * @brief Get Stream 6 transfer error flag. 01888 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 01889 * @param DMAx DMAx Instance 01890 * @retval State of bit (1 or 0). 01891 */ 01892 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) 01893 { 01894 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); 01895 } 01896 01897 /** 01898 * @brief Get Stream 7 transfer error flag. 01899 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 01900 * @param DMAx DMAx Instance 01901 * @retval State of bit (1 or 0). 01902 */ 01903 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) 01904 { 01905 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); 01906 } 01907 01908 /** 01909 * @brief Get Stream 0 direct mode error flag. 01910 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 01911 * @param DMAx DMAx Instance 01912 * @retval State of bit (1 or 0). 01913 */ 01914 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) 01915 { 01916 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); 01917 } 01918 01919 /** 01920 * @brief Get Stream 1 direct mode error flag. 01921 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 01922 * @param DMAx DMAx Instance 01923 * @retval State of bit (1 or 0). 01924 */ 01925 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) 01926 { 01927 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); 01928 } 01929 01930 /** 01931 * @brief Get Stream 2 direct mode error flag. 01932 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 01933 * @param DMAx DMAx Instance 01934 * @retval State of bit (1 or 0). 01935 */ 01936 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) 01937 { 01938 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); 01939 } 01940 01941 /** 01942 * @brief Get Stream 3 direct mode error flag. 01943 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 01944 * @param DMAx DMAx Instance 01945 * @retval State of bit (1 or 0). 01946 */ 01947 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) 01948 { 01949 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); 01950 } 01951 01952 /** 01953 * @brief Get Stream 4 direct mode error flag. 01954 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 01955 * @param DMAx DMAx Instance 01956 * @retval State of bit (1 or 0). 01957 */ 01958 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) 01959 { 01960 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); 01961 } 01962 01963 /** 01964 * @brief Get Stream 5 direct mode error flag. 01965 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 01966 * @param DMAx DMAx Instance 01967 * @retval State of bit (1 or 0). 01968 */ 01969 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) 01970 { 01971 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); 01972 } 01973 01974 /** 01975 * @brief Get Stream 6 direct mode error flag. 01976 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 01977 * @param DMAx DMAx Instance 01978 * @retval State of bit (1 or 0). 01979 */ 01980 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) 01981 { 01982 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); 01983 } 01984 01985 /** 01986 * @brief Get Stream 7 direct mode error flag. 01987 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 01988 * @param DMAx DMAx Instance 01989 * @retval State of bit (1 or 0). 01990 */ 01991 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) 01992 { 01993 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); 01994 } 01995 01996 /** 01997 * @brief Get Stream 0 FIFO error flag. 01998 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 01999 * @param DMAx DMAx Instance 02000 * @retval State of bit (1 or 0). 02001 */ 02002 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) 02003 { 02004 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); 02005 } 02006 02007 /** 02008 * @brief Get Stream 1 FIFO error flag. 02009 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 02010 * @param DMAx DMAx Instance 02011 * @retval State of bit (1 or 0). 02012 */ 02013 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) 02014 { 02015 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); 02016 } 02017 02018 /** 02019 * @brief Get Stream 2 FIFO error flag. 02020 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 02021 * @param DMAx DMAx Instance 02022 * @retval State of bit (1 or 0). 02023 */ 02024 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) 02025 { 02026 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); 02027 } 02028 02029 /** 02030 * @brief Get Stream 3 FIFO error flag. 02031 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 02032 * @param DMAx DMAx Instance 02033 * @retval State of bit (1 or 0). 02034 */ 02035 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) 02036 { 02037 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); 02038 } 02039 02040 /** 02041 * @brief Get Stream 4 FIFO error flag. 02042 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 02043 * @param DMAx DMAx Instance 02044 * @retval State of bit (1 or 0). 02045 */ 02046 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) 02047 { 02048 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); 02049 } 02050 02051 /** 02052 * @brief Get Stream 5 FIFO error flag. 02053 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 02054 * @param DMAx DMAx Instance 02055 * @retval State of bit (1 or 0). 02056 */ 02057 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) 02058 { 02059 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); 02060 } 02061 02062 /** 02063 * @brief Get Stream 6 FIFO error flag. 02064 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 02065 * @param DMAx DMAx Instance 02066 * @retval State of bit (1 or 0). 02067 */ 02068 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) 02069 { 02070 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); 02071 } 02072 02073 /** 02074 * @brief Get Stream 7 FIFO error flag. 02075 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 02076 * @param DMAx DMAx Instance 02077 * @retval State of bit (1 or 0). 02078 */ 02079 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) 02080 { 02081 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); 02082 } 02083 02084 /** 02085 * @brief Clear Stream 0 half transfer flag. 02086 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 02087 * @param DMAx DMAx Instance 02088 * @retval None 02089 */ 02090 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) 02091 { 02092 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); 02093 } 02094 02095 /** 02096 * @brief Clear Stream 1 half transfer flag. 02097 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 02098 * @param DMAx DMAx Instance 02099 * @retval None 02100 */ 02101 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) 02102 { 02103 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); 02104 } 02105 02106 /** 02107 * @brief Clear Stream 2 half transfer flag. 02108 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 02109 * @param DMAx DMAx Instance 02110 * @retval None 02111 */ 02112 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) 02113 { 02114 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); 02115 } 02116 02117 /** 02118 * @brief Clear Stream 3 half transfer flag. 02119 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 02120 * @param DMAx DMAx Instance 02121 * @retval None 02122 */ 02123 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) 02124 { 02125 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); 02126 } 02127 02128 /** 02129 * @brief Clear Stream 4 half transfer flag. 02130 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 02131 * @param DMAx DMAx Instance 02132 * @retval None 02133 */ 02134 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) 02135 { 02136 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); 02137 } 02138 02139 /** 02140 * @brief Clear Stream 5 half transfer flag. 02141 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 02142 * @param DMAx DMAx Instance 02143 * @retval None 02144 */ 02145 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) 02146 { 02147 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); 02148 } 02149 02150 /** 02151 * @brief Clear Stream 6 half transfer flag. 02152 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 02153 * @param DMAx DMAx Instance 02154 * @retval None 02155 */ 02156 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) 02157 { 02158 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); 02159 } 02160 02161 /** 02162 * @brief Clear Stream 7 half transfer flag. 02163 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 02164 * @param DMAx DMAx Instance 02165 * @retval None 02166 */ 02167 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) 02168 { 02169 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); 02170 } 02171 02172 /** 02173 * @brief Clear Stream 0 transfer complete flag. 02174 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 02175 * @param DMAx DMAx Instance 02176 * @retval None 02177 */ 02178 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) 02179 { 02180 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); 02181 } 02182 02183 /** 02184 * @brief Clear Stream 1 transfer complete flag. 02185 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 02186 * @param DMAx DMAx Instance 02187 * @retval None 02188 */ 02189 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) 02190 { 02191 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); 02192 } 02193 02194 /** 02195 * @brief Clear Stream 2 transfer complete flag. 02196 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 02197 * @param DMAx DMAx Instance 02198 * @retval None 02199 */ 02200 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) 02201 { 02202 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); 02203 } 02204 02205 /** 02206 * @brief Clear Stream 3 transfer complete flag. 02207 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 02208 * @param DMAx DMAx Instance 02209 * @retval None 02210 */ 02211 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) 02212 { 02213 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); 02214 } 02215 02216 /** 02217 * @brief Clear Stream 4 transfer complete flag. 02218 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 02219 * @param DMAx DMAx Instance 02220 * @retval None 02221 */ 02222 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) 02223 { 02224 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); 02225 } 02226 02227 /** 02228 * @brief Clear Stream 5 transfer complete flag. 02229 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 02230 * @param DMAx DMAx Instance 02231 * @retval None 02232 */ 02233 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) 02234 { 02235 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); 02236 } 02237 02238 /** 02239 * @brief Clear Stream 6 transfer complete flag. 02240 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 02241 * @param DMAx DMAx Instance 02242 * @retval None 02243 */ 02244 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) 02245 { 02246 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); 02247 } 02248 02249 /** 02250 * @brief Clear Stream 7 transfer complete flag. 02251 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 02252 * @param DMAx DMAx Instance 02253 * @retval None 02254 */ 02255 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) 02256 { 02257 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); 02258 } 02259 02260 /** 02261 * @brief Clear Stream 0 transfer error flag. 02262 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 02263 * @param DMAx DMAx Instance 02264 * @retval None 02265 */ 02266 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) 02267 { 02268 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); 02269 } 02270 02271 /** 02272 * @brief Clear Stream 1 transfer error flag. 02273 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 02274 * @param DMAx DMAx Instance 02275 * @retval None 02276 */ 02277 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) 02278 { 02279 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); 02280 } 02281 02282 /** 02283 * @brief Clear Stream 2 transfer error flag. 02284 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 02285 * @param DMAx DMAx Instance 02286 * @retval None 02287 */ 02288 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) 02289 { 02290 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); 02291 } 02292 02293 /** 02294 * @brief Clear Stream 3 transfer error flag. 02295 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 02296 * @param DMAx DMAx Instance 02297 * @retval None 02298 */ 02299 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) 02300 { 02301 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); 02302 } 02303 02304 /** 02305 * @brief Clear Stream 4 transfer error flag. 02306 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 02307 * @param DMAx DMAx Instance 02308 * @retval None 02309 */ 02310 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) 02311 { 02312 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); 02313 } 02314 02315 /** 02316 * @brief Clear Stream 5 transfer error flag. 02317 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 02318 * @param DMAx DMAx Instance 02319 * @retval None 02320 */ 02321 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) 02322 { 02323 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); 02324 } 02325 02326 /** 02327 * @brief Clear Stream 6 transfer error flag. 02328 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 02329 * @param DMAx DMAx Instance 02330 * @retval None 02331 */ 02332 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) 02333 { 02334 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); 02335 } 02336 02337 /** 02338 * @brief Clear Stream 7 transfer error flag. 02339 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 02340 * @param DMAx DMAx Instance 02341 * @retval None 02342 */ 02343 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) 02344 { 02345 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); 02346 } 02347 02348 /** 02349 * @brief Clear Stream 0 direct mode error flag. 02350 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 02351 * @param DMAx DMAx Instance 02352 * @retval None 02353 */ 02354 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) 02355 { 02356 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); 02357 } 02358 02359 /** 02360 * @brief Clear Stream 1 direct mode error flag. 02361 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 02362 * @param DMAx DMAx Instance 02363 * @retval None 02364 */ 02365 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) 02366 { 02367 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); 02368 } 02369 02370 /** 02371 * @brief Clear Stream 2 direct mode error flag. 02372 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 02373 * @param DMAx DMAx Instance 02374 * @retval None 02375 */ 02376 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) 02377 { 02378 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); 02379 } 02380 02381 /** 02382 * @brief Clear Stream 3 direct mode error flag. 02383 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 02384 * @param DMAx DMAx Instance 02385 * @retval None 02386 */ 02387 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) 02388 { 02389 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); 02390 } 02391 02392 /** 02393 * @brief Clear Stream 4 direct mode error flag. 02394 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 02395 * @param DMAx DMAx Instance 02396 * @retval None 02397 */ 02398 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) 02399 { 02400 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); 02401 } 02402 02403 /** 02404 * @brief Clear Stream 5 direct mode error flag. 02405 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 02406 * @param DMAx DMAx Instance 02407 * @retval None 02408 */ 02409 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) 02410 { 02411 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); 02412 } 02413 02414 /** 02415 * @brief Clear Stream 6 direct mode error flag. 02416 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 02417 * @param DMAx DMAx Instance 02418 * @retval None 02419 */ 02420 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) 02421 { 02422 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); 02423 } 02424 02425 /** 02426 * @brief Clear Stream 7 direct mode error flag. 02427 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 02428 * @param DMAx DMAx Instance 02429 * @retval None 02430 */ 02431 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) 02432 { 02433 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); 02434 } 02435 02436 /** 02437 * @brief Clear Stream 0 FIFO error flag. 02438 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 02439 * @param DMAx DMAx Instance 02440 * @retval None 02441 */ 02442 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) 02443 { 02444 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); 02445 } 02446 02447 /** 02448 * @brief Clear Stream 1 FIFO error flag. 02449 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 02450 * @param DMAx DMAx Instance 02451 * @retval None 02452 */ 02453 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) 02454 { 02455 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); 02456 } 02457 02458 /** 02459 * @brief Clear Stream 2 FIFO error flag. 02460 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 02461 * @param DMAx DMAx Instance 02462 * @retval None 02463 */ 02464 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) 02465 { 02466 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); 02467 } 02468 02469 /** 02470 * @brief Clear Stream 3 FIFO error flag. 02471 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 02472 * @param DMAx DMAx Instance 02473 * @retval None 02474 */ 02475 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) 02476 { 02477 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); 02478 } 02479 02480 /** 02481 * @brief Clear Stream 4 FIFO error flag. 02482 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 02483 * @param DMAx DMAx Instance 02484 * @retval None 02485 */ 02486 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) 02487 { 02488 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); 02489 } 02490 02491 /** 02492 * @brief Clear Stream 5 FIFO error flag. 02493 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 02494 * @param DMAx DMAx Instance 02495 * @retval None 02496 */ 02497 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) 02498 { 02499 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); 02500 } 02501 02502 /** 02503 * @brief Clear Stream 6 FIFO error flag. 02504 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 02505 * @param DMAx DMAx Instance 02506 * @retval None 02507 */ 02508 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) 02509 { 02510 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); 02511 } 02512 02513 /** 02514 * @brief Clear Stream 7 FIFO error flag. 02515 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 02516 * @param DMAx DMAx Instance 02517 * @retval None 02518 */ 02519 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) 02520 { 02521 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); 02522 } 02523 02524 /** 02525 * @} 02526 */ 02527 02528 /** @defgroup DMA_LL_EF_IT_Management IT_Management 02529 * @{ 02530 */ 02531 02532 /** 02533 * @brief Enable Half transfer interrupt. 02534 * @rmtoll CR HTIE LL_DMA_EnableIT_HT 02535 * @param DMAx DMAx Instance 02536 * @param Stream This parameter can be one of the following values: 02537 * @arg @ref LL_DMA_STREAM_0 02538 * @arg @ref LL_DMA_STREAM_1 02539 * @arg @ref LL_DMA_STREAM_2 02540 * @arg @ref LL_DMA_STREAM_3 02541 * @arg @ref LL_DMA_STREAM_4 02542 * @arg @ref LL_DMA_STREAM_5 02543 * @arg @ref LL_DMA_STREAM_6 02544 * @arg @ref LL_DMA_STREAM_7 02545 * @retval None 02546 */ 02547 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 02548 { 02549 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); 02550 } 02551 02552 /** 02553 * @brief Enable Transfer error interrupt. 02554 * @rmtoll CR TEIE LL_DMA_EnableIT_TE 02555 * @param DMAx DMAx Instance 02556 * @param Stream This parameter can be one of the following values: 02557 * @arg @ref LL_DMA_STREAM_0 02558 * @arg @ref LL_DMA_STREAM_1 02559 * @arg @ref LL_DMA_STREAM_2 02560 * @arg @ref LL_DMA_STREAM_3 02561 * @arg @ref LL_DMA_STREAM_4 02562 * @arg @ref LL_DMA_STREAM_5 02563 * @arg @ref LL_DMA_STREAM_6 02564 * @arg @ref LL_DMA_STREAM_7 02565 * @retval None 02566 */ 02567 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 02568 { 02569 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); 02570 } 02571 02572 /** 02573 * @brief Enable Transfer complete interrupt. 02574 * @rmtoll CR TCIE LL_DMA_EnableIT_TC 02575 * @param DMAx DMAx Instance 02576 * @param Stream This parameter can be one of the following values: 02577 * @arg @ref LL_DMA_STREAM_0 02578 * @arg @ref LL_DMA_STREAM_1 02579 * @arg @ref LL_DMA_STREAM_2 02580 * @arg @ref LL_DMA_STREAM_3 02581 * @arg @ref LL_DMA_STREAM_4 02582 * @arg @ref LL_DMA_STREAM_5 02583 * @arg @ref LL_DMA_STREAM_6 02584 * @arg @ref LL_DMA_STREAM_7 02585 * @retval None 02586 */ 02587 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 02588 { 02589 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); 02590 } 02591 02592 /** 02593 * @brief Enable Direct mode error interrupt. 02594 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME 02595 * @param DMAx DMAx Instance 02596 * @param Stream This parameter can be one of the following values: 02597 * @arg @ref LL_DMA_STREAM_0 02598 * @arg @ref LL_DMA_STREAM_1 02599 * @arg @ref LL_DMA_STREAM_2 02600 * @arg @ref LL_DMA_STREAM_3 02601 * @arg @ref LL_DMA_STREAM_4 02602 * @arg @ref LL_DMA_STREAM_5 02603 * @arg @ref LL_DMA_STREAM_6 02604 * @arg @ref LL_DMA_STREAM_7 02605 * @retval None 02606 */ 02607 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) 02608 { 02609 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); 02610 } 02611 02612 /** 02613 * @brief Enable FIFO error interrupt. 02614 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE 02615 * @param DMAx DMAx Instance 02616 * @param Stream This parameter can be one of the following values: 02617 * @arg @ref LL_DMA_STREAM_0 02618 * @arg @ref LL_DMA_STREAM_1 02619 * @arg @ref LL_DMA_STREAM_2 02620 * @arg @ref LL_DMA_STREAM_3 02621 * @arg @ref LL_DMA_STREAM_4 02622 * @arg @ref LL_DMA_STREAM_5 02623 * @arg @ref LL_DMA_STREAM_6 02624 * @arg @ref LL_DMA_STREAM_7 02625 * @retval None 02626 */ 02627 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) 02628 { 02629 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); 02630 } 02631 02632 /** 02633 * @brief Disable Half transfer interrupt. 02634 * @rmtoll CR HTIE LL_DMA_DisableIT_HT 02635 * @param DMAx DMAx Instance 02636 * @param Stream This parameter can be one of the following values: 02637 * @arg @ref LL_DMA_STREAM_0 02638 * @arg @ref LL_DMA_STREAM_1 02639 * @arg @ref LL_DMA_STREAM_2 02640 * @arg @ref LL_DMA_STREAM_3 02641 * @arg @ref LL_DMA_STREAM_4 02642 * @arg @ref LL_DMA_STREAM_5 02643 * @arg @ref LL_DMA_STREAM_6 02644 * @arg @ref LL_DMA_STREAM_7 02645 * @retval None 02646 */ 02647 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 02648 { 02649 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); 02650 } 02651 02652 /** 02653 * @brief Disable Transfer error interrupt. 02654 * @rmtoll CR TEIE LL_DMA_DisableIT_TE 02655 * @param DMAx DMAx Instance 02656 * @param Stream This parameter can be one of the following values: 02657 * @arg @ref LL_DMA_STREAM_0 02658 * @arg @ref LL_DMA_STREAM_1 02659 * @arg @ref LL_DMA_STREAM_2 02660 * @arg @ref LL_DMA_STREAM_3 02661 * @arg @ref LL_DMA_STREAM_4 02662 * @arg @ref LL_DMA_STREAM_5 02663 * @arg @ref LL_DMA_STREAM_6 02664 * @arg @ref LL_DMA_STREAM_7 02665 * @retval None 02666 */ 02667 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 02668 { 02669 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); 02670 } 02671 02672 /** 02673 * @brief Disable Transfer complete interrupt. 02674 * @rmtoll CR TCIE LL_DMA_DisableIT_TC 02675 * @param DMAx DMAx Instance 02676 * @param Stream This parameter can be one of the following values: 02677 * @arg @ref LL_DMA_STREAM_0 02678 * @arg @ref LL_DMA_STREAM_1 02679 * @arg @ref LL_DMA_STREAM_2 02680 * @arg @ref LL_DMA_STREAM_3 02681 * @arg @ref LL_DMA_STREAM_4 02682 * @arg @ref LL_DMA_STREAM_5 02683 * @arg @ref LL_DMA_STREAM_6 02684 * @arg @ref LL_DMA_STREAM_7 02685 * @retval None 02686 */ 02687 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 02688 { 02689 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); 02690 } 02691 02692 /** 02693 * @brief Disable Direct mode error interrupt. 02694 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME 02695 * @param DMAx DMAx Instance 02696 * @param Stream This parameter can be one of the following values: 02697 * @arg @ref LL_DMA_STREAM_0 02698 * @arg @ref LL_DMA_STREAM_1 02699 * @arg @ref LL_DMA_STREAM_2 02700 * @arg @ref LL_DMA_STREAM_3 02701 * @arg @ref LL_DMA_STREAM_4 02702 * @arg @ref LL_DMA_STREAM_5 02703 * @arg @ref LL_DMA_STREAM_6 02704 * @arg @ref LL_DMA_STREAM_7 02705 * @retval None 02706 */ 02707 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) 02708 { 02709 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); 02710 } 02711 02712 /** 02713 * @brief Disable FIFO error interrupt. 02714 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE 02715 * @param DMAx DMAx Instance 02716 * @param Stream This parameter can be one of the following values: 02717 * @arg @ref LL_DMA_STREAM_0 02718 * @arg @ref LL_DMA_STREAM_1 02719 * @arg @ref LL_DMA_STREAM_2 02720 * @arg @ref LL_DMA_STREAM_3 02721 * @arg @ref LL_DMA_STREAM_4 02722 * @arg @ref LL_DMA_STREAM_5 02723 * @arg @ref LL_DMA_STREAM_6 02724 * @arg @ref LL_DMA_STREAM_7 02725 * @retval None 02726 */ 02727 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) 02728 { 02729 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); 02730 } 02731 02732 /** 02733 * @brief Check if Half transfer interrup is enabled. 02734 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT 02735 * @param DMAx DMAx Instance 02736 * @param Stream This parameter can be one of the following values: 02737 * @arg @ref LL_DMA_STREAM_0 02738 * @arg @ref LL_DMA_STREAM_1 02739 * @arg @ref LL_DMA_STREAM_2 02740 * @arg @ref LL_DMA_STREAM_3 02741 * @arg @ref LL_DMA_STREAM_4 02742 * @arg @ref LL_DMA_STREAM_5 02743 * @arg @ref LL_DMA_STREAM_6 02744 * @arg @ref LL_DMA_STREAM_7 02745 * @retval State of bit (1 or 0). 02746 */ 02747 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 02748 { 02749 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); 02750 } 02751 02752 /** 02753 * @brief Check if Transfer error nterrup is enabled. 02754 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE 02755 * @param DMAx DMAx Instance 02756 * @param Stream This parameter can be one of the following values: 02757 * @arg @ref LL_DMA_STREAM_0 02758 * @arg @ref LL_DMA_STREAM_1 02759 * @arg @ref LL_DMA_STREAM_2 02760 * @arg @ref LL_DMA_STREAM_3 02761 * @arg @ref LL_DMA_STREAM_4 02762 * @arg @ref LL_DMA_STREAM_5 02763 * @arg @ref LL_DMA_STREAM_6 02764 * @arg @ref LL_DMA_STREAM_7 02765 * @retval State of bit (1 or 0). 02766 */ 02767 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 02768 { 02769 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE); 02770 } 02771 02772 /** 02773 * @brief Check if Transfer complete interrup is enabled. 02774 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC 02775 * @param DMAx DMAx Instance 02776 * @param Stream This parameter can be one of the following values: 02777 * @arg @ref LL_DMA_STREAM_0 02778 * @arg @ref LL_DMA_STREAM_1 02779 * @arg @ref LL_DMA_STREAM_2 02780 * @arg @ref LL_DMA_STREAM_3 02781 * @arg @ref LL_DMA_STREAM_4 02782 * @arg @ref LL_DMA_STREAM_5 02783 * @arg @ref LL_DMA_STREAM_6 02784 * @arg @ref LL_DMA_STREAM_7 02785 * @retval State of bit (1 or 0). 02786 */ 02787 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 02788 { 02789 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); 02790 } 02791 02792 /** 02793 * @brief Check if Direct mode error interrupt is enabled. 02794 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME 02795 * @param DMAx DMAx Instance 02796 * @param Stream This parameter can be one of the following values: 02797 * @arg @ref LL_DMA_STREAM_0 02798 * @arg @ref LL_DMA_STREAM_1 02799 * @arg @ref LL_DMA_STREAM_2 02800 * @arg @ref LL_DMA_STREAM_3 02801 * @arg @ref LL_DMA_STREAM_4 02802 * @arg @ref LL_DMA_STREAM_5 02803 * @arg @ref LL_DMA_STREAM_6 02804 * @arg @ref LL_DMA_STREAM_7 02805 * @retval State of bit (1 or 0). 02806 */ 02807 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) 02808 { 02809 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE); 02810 } 02811 02812 /** 02813 * @brief Check if FIFO error interrup is enabled. 02814 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE 02815 * @param DMAx DMAx Instance 02816 * @param Stream This parameter can be one of the following values: 02817 * @arg @ref LL_DMA_STREAM_0 02818 * @arg @ref LL_DMA_STREAM_1 02819 * @arg @ref LL_DMA_STREAM_2 02820 * @arg @ref LL_DMA_STREAM_3 02821 * @arg @ref LL_DMA_STREAM_4 02822 * @arg @ref LL_DMA_STREAM_5 02823 * @arg @ref LL_DMA_STREAM_6 02824 * @arg @ref LL_DMA_STREAM_7 02825 * @retval State of bit (1 or 0). 02826 */ 02827 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) 02828 { 02829 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE); 02830 } 02831 02832 /** 02833 * @} 02834 */ 02835 02836 #if defined(USE_FULL_LL_DRIVER) 02837 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions 02838 * @{ 02839 */ 02840 02841 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); 02842 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); 02843 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); 02844 02845 /** 02846 * @} 02847 */ 02848 #endif /* USE_FULL_LL_DRIVER */ 02849 02850 /** 02851 * @} 02852 */ 02853 02854 /** 02855 * @} 02856 */ 02857 02858 #endif /* DMA1 || DMA2 */ 02859 02860 /** 02861 * @} 02862 */ 02863 02864 #ifdef __cplusplus 02865 } 02866 #endif 02867 02868 #endif /* __STM32F4xx_LL_DMA_H */ 02869 02870 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1