ADC group regular - Sampling mode

Defines
#define	LL_ADC_REG_SAMPLING_MODE_NORMAL   (0x00000000UL)
#define	LL_ADC_REG_SAMPLING_MODE_BULB   (ADC3_CFGR2_BULB)
#define	LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED   (ADC3_CFGR2_SMPTRIG)

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Define Documentation

#define LL_ADC_REG_SAMPLING_MODE_BULB   (ADC3_CFGR2_BULB)

ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. Note: First conversion is using minimal sampling time (see Channel - Sampling time). On devices STM32H72xx and STM32H73xx

Definition at line 1009 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SAMPLING_MODE_NORMAL   (0x00000000UL)

ADC conversions sampling phase duration is defined using Channel - Sampling time. On devices STM32H72xx and STM32H73xx

Definition at line 1008 of file stm32h7xx_ll_adc.h.

#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED   (ADC3_CFGR2_SMPTRIG)

ADC conversions sampling phase is controlled by trigger events: Trigger rising edge = start sampling Trigger falling edge = stop sampling and start conversion. On devices STM32H72xx and STM32H73xx

Definition at line 1011 of file stm32h7xx_ll_adc.h.