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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_adc.h 00004 * @author MCD Application Team 00005 * @brief Header file of ADC HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_ADC_H 00021 #define STM32H7xx_HAL_ADC_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx_hal_def.h" 00029 00030 /* Include low level driver */ 00031 #include "stm32h7xx_ll_adc.h" 00032 00033 /** @addtogroup STM32H7xx_HAL_Driver 00034 * @{ 00035 */ 00036 00037 /** @addtogroup ADC 00038 * @{ 00039 */ 00040 00041 /* Exported types ------------------------------------------------------------*/ 00042 /** @defgroup ADC_Exported_Types ADC Exported Types 00043 * @{ 00044 */ 00045 00046 /** 00047 * @brief ADC group regular oversampling structure definition 00048 */ 00049 typedef struct 00050 { 00051 uint32_t Ratio; /*!< Configures the oversampling ratio. */ 00052 #if defined(ADC_VER_V5_V90) 00053 /* On devices STM32H72xx and STM32H73xx, this parameter can be a value from 1 to 1023 for ADC1/2 or a value of @ref ADC_HAL_EC_OVS_RATIO for ADC3*/ 00054 #else 00055 /*This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 00056 #endif 00057 00058 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 00059 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 00060 00061 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 00062 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 00063 00064 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 00065 The oversampling is either temporary stopped or reset upon an injected 00066 sequence interruption. 00067 If oversampling is enabled on both regular and injected groups, this parameter 00068 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 00069 (the oversampling buffer is zeroed during injection sequence). 00070 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 00071 00072 } ADC_OversamplingTypeDef; 00073 00074 /** 00075 * @brief Structure definition of ADC instance and ADC group regular. 00076 * @note Parameters of this structure are shared within 2 scopes: 00077 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 00078 * ScanConvMode, EOCSelection, LowPowerAutoWait. 00079 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 00080 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 00081 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 00082 * ADC state can be either: 00083 * - For all parameters: ADC disabled 00084 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. 00085 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. 00086 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00087 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 00088 * (which fulfills the ADC state condition) on the fly). 00089 */ 00090 typedef struct 00091 { 00092 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. 00093 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 00094 Note: The ADC clock configuration is common to all ADC instances. 00095 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 00096 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 00097 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 00098 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 00099 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 00100 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. 00101 Note: This parameter can be modified only if all ADC instances are disabled. */ 00102 00103 uint32_t Resolution; /*!< Configure the ADC resolution. 00104 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 00105 00106 #if defined(ADC_VER_V5_V90) 00107 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 00108 Refer to reference manual for alignments formats versus resolutions. 00109 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN 00110 This parameter is reserved for ADC3 on devices STM32H72xx and STM32H73xx*/ 00111 #endif 00112 00113 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 00114 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 00115 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 00116 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 00117 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). 00118 Scan direction is upward: from rank 1 to rank 'n'. 00119 This parameter can be a value of @ref ADC_Scan_mode */ 00120 00121 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 00122 This parameter can be a value of @ref ADC_EOCSelection. */ 00123 00124 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 00125 conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, 00126 using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 00127 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 00128 for low frequency applications. 00129 This parameter can be set to ENABLE or DISABLE. 00130 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). 00131 Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). 00132 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 00133 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, 00134 use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ 00135 00136 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 00137 after the first ADC conversion start trigger occurred (software start or external trigger). 00138 This parameter can be set to ENABLE or DISABLE. */ 00139 00140 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. 00141 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 00142 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 00143 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 00144 continuous mode or external trigger that could launch a conversion). */ 00145 00146 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 00147 (main sequence subdivided in successive parts). 00148 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 00149 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 00150 This parameter can be set to ENABLE or DISABLE. */ 00151 00152 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. 00153 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 00154 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 00155 00156 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 00157 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 00158 This parameter can be a value of @ref ADC_regular_external_trigger_source. 00159 Caution: external trigger source is common to all ADC instances. */ 00160 00161 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 00162 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 00163 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 00164 00165 uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transferred to DFSDM register. 00166 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 00167 This parameter can be a value of @ref ADC_ConversionDataManagement. 00168 Note: This parameter must be modified when no conversion is on going on both regular and injected groups 00169 (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).*/ 00170 #if defined(ADC_VER_V5_V90) 00171 /*Note: On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */ 00172 00173 uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. 00174 This parameter can be a value of @ref ADC_regular_sampling_mode. 00175 Note: 00176 - On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */ 00177 00178 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) 00179 or in continuous mode (DMA transfer unlimited, whatever number of conversions). 00180 This parameter can be set to ENABLE or DISABLE. 00181 Notes: 00182 - In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 00183 - Specific to ADC3 only on devices STM32H72xx and STM32H73xx */ 00184 #endif 00185 00186 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 00187 This parameter applies to ADC group regular only. 00188 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 00189 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 00190 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 00191 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 00192 Note: Error reporting with respect to the conversion mode: 00193 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 00194 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 00195 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 00196 00197 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling. 00198 This parameter can be a value of @ref ADCEx_Left_Bit_Shift */ 00199 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 00200 This parameter can be set to ENABLE or DISABLE. 00201 Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ 00202 00203 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 00204 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 00205 00206 } ADC_InitTypeDef; 00207 00208 /** 00209 * @brief Structure definition of ADC channel for regular group 00210 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 00211 * ADC state can be either: 00212 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 00213 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. 00214 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. 00215 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00216 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) 00217 * on the fly). 00218 */ 00219 typedef struct 00220 { 00221 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 00222 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 00223 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 00224 00225 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 00226 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 00227 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 00228 the new channel setting (or parameter number of conversions adjusted) */ 00229 00230 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 00231 Unit: ADC clock cycles 00232 Conversion time is the addition of sampling time and processing time 00233 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 00234 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 00235 Caution: This parameter applies to a channel that can be used into regular and/or injected group. 00236 It overwrites the last setting. 00237 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 00238 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 00239 Refer to device datasheet for timings values. */ 00240 00241 uint32_t SingleDiff; /*!< Select single-ended or differential input. 00242 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 00243 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 00244 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 00245 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00246 It overwrites the last setting. 00247 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 00248 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 00249 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 00250 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 00251 of another parameter update on the fly) */ 00252 00253 uint32_t OffsetNumber; /*!< Select the offset number 00254 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 00255 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 00256 00257 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. 00258 Offset value must be a positive number. 00259 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF, 00260 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. 00261 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 00262 without continuous mode or external trigger that could launch a conversion). */ 00263 00264 FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction. 00265 This parameter is applied only for 16-bit or 8-bit resolution. 00266 This parameter can be set to ENABLE or DISABLE.*/ 00267 #if defined(ADC_VER_V5_V90) 00268 uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. 00269 This parameter can be a value of @ref ADCEx_OffsetSign. 00270 Note: 00271 - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 00272 without continuous mode or external trigger that could launch a conversion). 00273 - Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00274 FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 00275 This parameter value can be ENABLE or DISABLE. 00276 Note: 00277 - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 00278 without continuous mode or external trigger that could launch a conversion). 00279 - Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00280 #endif 00281 FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not. 00282 This parameter is applied only for 16-bit or 8-bit resolution. 00283 This parameter can be set to ENABLE or DISABLE. */ 00284 00285 } ADC_ChannelConfTypeDef; 00286 00287 /** 00288 * @brief Structure definition of ADC analog watchdog 00289 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 00290 * ADC state can be either: 00291 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. 00292 */ 00293 typedef struct 00294 { 00295 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 00296 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 00297 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 00298 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 00299 00300 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 00301 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. 00302 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. 00303 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 00304 00305 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 00306 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). 00307 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). 00308 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 00309 00310 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 00311 This parameter can be set to ENABLE or DISABLE */ 00312 00313 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 00314 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number 00315 between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. 00316 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 00317 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 00318 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 00319 impacted: the comparison of analog watchdog thresholds is done 00320 on oversampling intermediate computation (after ratio, before shift 00321 application): intermediate register bitfield [32:7] (26 most significant bits). */ 00322 00323 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 00324 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number 00325 between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. 00326 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 00327 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 00328 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 00329 impacted: the comparison of analog watchdog thresholds is done 00330 on oversampling intermediate computation (after ratio, before shift 00331 application): intermediate register bitfield [32:7] (26 most significant bits). */ 00332 #if defined(ADC_VER_V5_V90) 00333 uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. 00334 Before setting flag or raising interrupt, analog watchdog can wait to have several 00335 consecutive out-of-window samples. This parameter allows to configure this number. 00336 This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE. 00337 This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. Applicable for ADC3 on devices STM32H72xx and STM32H73xx. */ 00338 #endif 00339 } ADC_AnalogWDGConfTypeDef; 00340 00341 /** 00342 * @brief ADC group injected contexts queue configuration 00343 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 00344 */ 00345 typedef struct 00346 { 00347 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 00348 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 00349 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 00350 00351 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 00352 } ADC_InjectionConfigTypeDef; 00353 00354 /** @defgroup ADC_States ADC States 00355 * @{ 00356 */ 00357 00358 /** 00359 * @brief HAL ADC state machine: ADC states definition (bitfields) 00360 * @note ADC state machine is managed by bitfields, state must be compared 00361 * with bit by bit. 00362 * For example: 00363 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 00364 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 00365 */ 00366 /* States of ADC global scope */ 00367 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 00368 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 00369 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ 00370 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 00371 00372 /* States of ADC errors */ 00373 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 00374 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 00375 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 00376 00377 /* States of ADC group regular */ 00378 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 00379 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 00380 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 00381 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 00382 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ 00383 00384 /* States of ADC group injected */ 00385 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, 00386 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 00387 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 00388 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 00389 00390 /* States of ADC analog watchdogs */ 00391 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 00392 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 00393 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 00394 00395 /* States of ADC multi-mode */ 00396 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ 00397 00398 /** 00399 * @} 00400 */ 00401 00402 /** 00403 * @brief ADC handle Structure definition 00404 */ 00405 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00406 typedef struct __ADC_HandleTypeDef 00407 #else 00408 typedef struct 00409 #endif 00410 { 00411 ADC_TypeDef *Instance; /*!< Register base address */ 00412 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 00413 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 00414 HAL_LockTypeDef Lock; /*!< ADC locking object */ 00415 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 00416 __IO uint32_t ErrorCode; /*!< ADC Error code */ 00417 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ 00418 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00419 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 00420 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 00421 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 00422 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 00423 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 00424 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ 00425 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 00426 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 00427 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 00428 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 00429 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 00430 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00431 } ADC_HandleTypeDef; 00432 00433 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00434 /** 00435 * @brief HAL ADC Callback ID enumeration definition 00436 */ 00437 typedef enum 00438 { 00439 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 00440 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 00441 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 00442 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 00443 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 00444 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 00445 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 00446 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 00447 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 00448 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 00449 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 00450 } HAL_ADC_CallbackIDTypeDef; 00451 00452 /** 00453 * @brief HAL ADC Callback pointer definition 00454 */ 00455 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 00456 00457 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00458 00459 /** 00460 * @} 00461 */ 00462 00463 00464 /* Exported constants --------------------------------------------------------*/ 00465 00466 /** @defgroup ADC_Exported_Constants ADC Exported Constants 00467 * @{ 00468 */ 00469 00470 /** @defgroup ADC_Error_Code ADC Error Code 00471 * @{ 00472 */ 00473 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 00474 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 00475 enable/disable, erroneous state, ...) */ 00476 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 00477 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 00478 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 00479 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00480 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 00481 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00482 /** 00483 * @} 00484 */ 00485 00486 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 00487 * @{ 00488 */ 00489 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 00490 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 00491 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 00492 00493 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ 00494 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ 00495 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ 00496 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ 00497 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ 00498 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ 00499 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ 00500 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ 00501 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ 00502 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ 00503 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ 00504 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ 00505 /** 00506 * @} 00507 */ 00508 00509 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 00510 * @{ 00511 */ 00512 #define ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B) /*!< ADC resolution 16 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 00513 #define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 00514 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 00515 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 00516 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 00517 00518 #if defined (ADC_VER_V5_X) 00519 #define ADC_RESOLUTION_14B_OPT (LL_ADC_RESOLUTION_14B_OPT) /*!< ADC resolution 14 bits optimized for power consumption, available on for devices revision V only */ 00520 #define ADC_RESOLUTION_12B_OPT (LL_ADC_RESOLUTION_12B_OPT) /*!< ADC resolution 12 bits optimized for power consumption, available on for devices revision V only */ 00521 #endif 00522 00523 #if defined(ADC_VER_V5_V90) 00524 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 00525 #endif /* ADC_VER_V5_V90 */ 00526 /** 00527 * @} 00528 */ 00529 00530 #if defined(ADC_VER_V5_V90) 00531 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 00532 * @{ 00533 */ 00534 #define ADC3_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 00535 #define ADC3_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ 00536 /** 00537 * @} 00538 */ 00539 #endif 00540 00541 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 00542 * @{ 00543 */ 00544 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 00545 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 00546 /** 00547 * @} 00548 */ 00549 00550 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 00551 * @{ 00552 */ 00553 /* ADC group regular trigger sources for all ADC instances */ 00554 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ 00555 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00556 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00557 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00558 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00559 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */ 00560 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00561 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */ 00562 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */ 00563 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */ 00564 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */ 00565 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */ 00566 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */ 00567 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */ 00568 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ 00569 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ 00570 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00571 #define ADC_EXTERNALTRIG_HR1_ADCTRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */ 00572 #define ADC_EXTERNALTRIG_HR1_ADCTRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG3 event. Trigger edge set to rising edge (default setting). */ 00573 #define ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */ 00574 #define ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */ 00575 #define ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */ 00576 #if defined(TIM23) 00577 #define ADC_EXTERNALTRIG_T23_TRGO (LL_ADC_REG_TRIG_EXT_TIM23_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM23 TRGO event. Trigger edge set to rising edge (default setting). */ 00578 #endif /*TIM23*/ 00579 #if defined(TIM24) 00580 #define ADC_EXTERNALTRIG_T24_TRGO (LL_ADC_REG_TRIG_EXT_TIM24_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM24 TRGO event. Trigger edge set to rising edge (default setting). */ 00581 #endif /*TIM24*/ 00582 /** 00583 * @} 00584 */ 00585 00586 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 00587 * @{ 00588 */ 00589 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ 00590 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ 00591 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ 00592 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 00593 /** 00594 * @} 00595 */ 00596 #if defined(ADC_VER_V5_V90) 00597 /** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode 00598 * @{ 00599 */ 00600 #define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ 00601 #define ADC_SAMPLING_MODE_BULB (ADC3_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. 00602 Notes: 00603 - First conversion is using minimal sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) 00604 - Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00605 #define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC3_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events: 00606 Trigger rising edge = start sampling 00607 Trigger falling edge = stop sampling and start conversion 00608 Note: Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00609 /** 00610 * @} 00611 */ 00612 #endif 00613 00614 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 00615 * @{ 00616 */ 00617 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 00618 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 00619 /** 00620 * @} 00621 */ 00622 00623 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 00624 * @{ 00625 */ 00626 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ 00627 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ 00628 /** 00629 * @} 00630 */ 00631 00632 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 00633 * @{ 00634 */ 00635 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 00636 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 00637 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 00638 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 00639 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 00640 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 00641 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 00642 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 00643 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 00644 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 00645 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 00646 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 00647 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 00648 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 00649 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 00650 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 00651 /** 00652 * @} 00653 */ 00654 00655 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 00656 * @{ 00657 */ 00658 #define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 00659 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 00660 #define ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5) /*!< Sampling time 8.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 00661 #define ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5) /*!< Sampling time 16.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 00662 #define ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5) /*!< Sampling time 32.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 00663 #define ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5) /*!< Sampling time 64.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 00664 #define ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5) /*!< Sampling time 387.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 00665 #define ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5) /*!< Sampling time 810.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 00666 /** 00667 * @} 00668 */ 00669 #if defined(ADC_VER_V5_V90) 00670 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 00671 * @{ 00672 */ 00673 #define ADC3_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 00674 #define ADC3_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 00675 #define ADC3_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 00676 #define ADC3_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 00677 #define ADC3_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 00678 #define ADC3_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 00679 #define ADC3_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 00680 #define ADC3_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 00681 #define ADC3_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. 00682 On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 00683 /** 00684 * @} 00685 */ 00686 #endif 00687 00688 /** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode 00689 * @{ 00690 */ 00691 #define ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET) 00692 #define ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY) 00693 /** 00694 * @} 00695 */ 00696 00697 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 00698 * @{ 00699 */ 00700 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 00701 /* all ADC instances (refer to Reference Manual). */ 00702 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 00703 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 00704 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 00705 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 00706 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 00707 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 00708 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 00709 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 00710 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 00711 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 00712 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 00713 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 00714 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 00715 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 00716 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 00717 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 00718 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 00719 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 00720 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 00721 #define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */ 00722 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference, channel specific to ADC3. */ 00723 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor, channel specific to ADC3. */ 00724 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC3. */ 00725 #define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ 00726 #define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ 00727 #if defined (LL_ADC_CHANNEL_DAC2CH1_ADC2) 00728 #define ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_DAC2CH1_ADC2) /*!< ADC internal channel connected to DAC2 channel 1, channel specific to ADC2 */ 00729 #endif 00730 /** 00731 * @} 00732 */ 00733 00734 /** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management 00735 * @{ 00736 */ 00737 #define ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000) /*!< Regular Conversion data stored in DR register only */ 00738 #define ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */ 00739 #define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */ 00740 #define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)) /*!< DMA circular mode selected */ 00741 /** 00742 * @} 00743 */ 00744 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 00745 * @{ 00746 */ 00747 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 00748 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 00749 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 00750 /** 00751 * @} 00752 */ 00753 00754 #if defined(ADC_VER_V5_V90) 00755 /** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration 00756 * @{ 00757 */ 00758 #define ADC3_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00759 #define ADC3_AWD_FILTERING_2SAMPLES ((ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00760 #define ADC3_AWD_FILTERING_3SAMPLES ((ADC3_TR1_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00761 #define ADC3_AWD_FILTERING_4SAMPLES ((ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00762 #define ADC3_AWD_FILTERING_5SAMPLES ((ADC3_TR1_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00763 #define ADC3_AWD_FILTERING_6SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00764 #define ADC3_AWD_FILTERING_7SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00765 #define ADC3_AWD_FILTERING_8SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00766 /** 00767 * @} 00768 */ 00769 #endif 00770 00771 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 00772 * @{ 00773 */ 00774 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ 00775 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ 00776 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ 00777 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ 00778 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 00779 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ 00780 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ 00781 /** 00782 * @} 00783 */ 00784 #if defined(ADC_VER_V5_V90) 00785 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 00786 * @{ 00787 */ 00788 #define ADC3_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00789 #define ADC3_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00790 #define ADC3_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00791 #define ADC3_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00792 #define ADC3_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00793 #define ADC3_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00794 #define ADC3_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00795 #define ADC3_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00796 #define ADC3_OVERSAMPLING_RATIO_512 (LL_ADC_OVS_RATIO_512) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00797 #define ADC3_OVERSAMPLING_RATIO_1024 (LL_ADC_OVS_RATIO_1024) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 00798 /** 00799 * @} 00800 */ 00801 #endif 00802 00803 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 00804 * @{ 00805 */ 00806 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 00807 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 00808 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 00809 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 00810 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 00811 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 00812 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 00813 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 00814 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 00815 #define ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */ 00816 #define ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */ 00817 #define ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11)/*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */ 00818 /** 00819 * @} 00820 */ 00821 00822 /** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift 00823 * @{ 00824 */ 00825 #define ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE) /*!< ADC No bit shift */ 00826 #define ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1) /*!< ADC 1 bit shift */ 00827 #define ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2) /*!< ADC 2 bits shift */ 00828 #define ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3) /*!< ADC 3 bits shift */ 00829 #define ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4) /*!< ADC 4 bits shift */ 00830 #define ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5) /*!< ADC 5 bits shift */ 00831 #define ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6) /*!< ADC 6 bits shift */ 00832 #define ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7) /*!< ADC 7 bits shift */ 00833 #define ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8) /*!< ADC 8 bits shift */ 00834 #define ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9) /*!< ADC 9 bits shift */ 00835 #define ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10) /*!< ADC 10 bits shift */ 00836 #define ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11) /*!< ADC 11 bits shift */ 00837 #define ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12) /*!< ADC 12 bits shift */ 00838 #define ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13) /*!< ADC 13 bits shift */ 00839 #define ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14) /*!< ADC 14 bits shift */ 00840 #define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15) /*!< ADC 15 bits shift */ 00841 /** 00842 * @} 00843 */ 00844 00845 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 00846 * @{ 00847 */ 00848 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 00849 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 00850 /** 00851 * @} 00852 */ 00853 00854 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 00855 * @{ 00856 */ 00857 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ 00858 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ 00859 /** 00860 * @} 00861 */ 00862 00863 00864 /** @defgroup ADC_Event_type ADC Event type 00865 * @{ 00866 */ 00867 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 00868 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ 00869 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ 00870 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ 00871 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 00872 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 00873 /** 00874 * @} 00875 */ 00876 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 00877 00878 /** @defgroup ADC_interrupts_definition ADC interrupts definition 00879 * @{ 00880 */ 00881 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 00882 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 00883 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 00884 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 00885 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 00886 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 00887 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 00888 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 00889 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 00890 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 00891 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 00892 00893 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ 00894 00895 /** 00896 * @} 00897 */ 00898 00899 /** @defgroup ADC_flags_definition ADC flags definition 00900 * @{ 00901 */ 00902 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 00903 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 00904 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 00905 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 00906 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 00907 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 00908 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 00909 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 00910 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 00911 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 00912 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 00913 00914 /** 00915 * @} 00916 */ 00917 00918 /** 00919 * @} 00920 */ 00921 00922 /* Private macro -------------------------------------------------------------*/ 00923 00924 /** @defgroup ADC_Private_Macros ADC Private Macros 00925 * @{ 00926 */ 00927 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 00928 /* code of final user. */ 00929 00930 /** 00931 * @brief Verify the ADC data conversion setting. 00932 * @param DATA : programmed DATA conversion mode. 00933 * @retval SET (DATA is a valid value) or RESET (DATA is invalid) 00934 */ 00935 #define IS_ADC_CONVERSIONDATAMGT(DATA) \ 00936 ((((DATA) == ADC_CONVERSIONDATA_DR)) || \ 00937 (((DATA) == ADC_CONVERSIONDATA_DFSDM)) || \ 00938 (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \ 00939 (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR))) 00940 00941 /** 00942 * @brief Return resolution bits in CFGR register RES[1:0] field. 00943 * @param __HANDLE__ ADC handle 00944 * @retval Value of bitfield RES in CFGR register. 00945 */ 00946 #define ADC_GET_RESOLUTION(__HANDLE__) \ 00947 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 00948 00949 /** 00950 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 00951 * @param __HANDLE__ ADC handle 00952 * @retval None 00953 */ 00954 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 00955 00956 /** 00957 * @brief Verification of ADC state: enabled or disabled. 00958 * @param __HANDLE__ ADC handle 00959 * @retval SET (ADC enabled) or RESET (ADC disabled) 00960 */ 00961 #define ADC_IS_ENABLE(__HANDLE__) \ 00962 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 00963 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 00964 ) ? SET : RESET) 00965 00966 /** 00967 * @brief Check if conversion is on going on regular group. 00968 * @param __HANDLE__ ADC handle 00969 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 00970 */ 00971 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 00972 (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) 00973 00974 /** 00975 * @brief Check if ADC clock mode is synchronous 00976 * @param __HANDLE__: ADC handle 00977 * @retval SET (clock mode is synchronous) or RESET (clock mode is asynchronous) 00978 */ 00979 #if defined (ADC3) 00980 #define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) \ 00981 (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2))? \ 00982 ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL) \ 00983 :((((ADC3_COMMON)->CCR) & ADC_CCR_CKMODE) != 0UL)) 00984 #else 00985 #define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL) 00986 00987 #endif 00988 00989 /** 00990 * @brief Simultaneously clear and set specific bits of the handle State. 00991 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 00992 * the first parameter is the ADC handle State, the second parameter is the 00993 * bit field to clear, the third and last parameter is the bit field to set. 00994 * @retval None 00995 */ 00996 #define ADC_STATE_CLR_SET MODIFY_REG 00997 00998 /** 00999 * @brief Verify that a given value is aligned with the ADC resolution range. 01000 * @param __RESOLUTION__ ADC resolution (16, 14, 12, 10 or 8 bits). 01001 * @param __ADC_VALUE__ value checked against the resolution. 01002 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 01003 */ 01004 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 01005 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 01006 01007 #if defined(ADC_VER_V5_V90) 01008 /** 01009 * @brief Verify that a given value is aligned with the ADC resolution range. Applicable for ADC3 on devices STM32H72xx and STM32H73xx. 01010 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 01011 * @param __ADC_VALUE__ value checked against the resolution. 01012 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 01013 */ 01014 #define IS_ADC3_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 01015 ((__ADC_VALUE__) <= __LL_ADC3_DIGITAL_SCALE(__RESOLUTION__)) 01016 #endif 01017 /** 01018 * @brief Verify the length of the scheduled regular conversions group. 01019 * @param __LENGTH__ number of programmed conversions. 01020 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) 01021 */ 01022 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 01023 01024 01025 /** 01026 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 01027 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 01028 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) 01029 */ 01030 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 01031 01032 01033 /** 01034 * @brief Verify the ADC clock setting. 01035 * @param __ADC_CLOCK__ programmed ADC clock. 01036 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 01037 */ 01038 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 01039 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 01040 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 01041 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 01042 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 01043 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 01044 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 01045 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 01046 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 01047 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 01048 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 01049 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 01050 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 01051 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 01052 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 01053 01054 /** 01055 * @brief Verify the ADC resolution setting. 01056 * @param __RESOLUTION__ programmed ADC resolution. 01057 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 01058 */ 01059 #if defined(ADC_VER_V5_V90) 01060 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \ 01061 ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \ 01062 ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 01063 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 01064 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 01065 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 01066 #elif defined (ADC_VER_V5_X) 01067 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \ 01068 ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \ 01069 ((__RESOLUTION__) == ADC_RESOLUTION_14B_OPT) || \ 01070 ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 01071 ((__RESOLUTION__) == ADC_RESOLUTION_12B_OPT) || \ 01072 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 01073 ((__RESOLUTION__) == ADC_RESOLUTION_8B) ) 01074 #else /* ADC_VER_V5_3 */ 01075 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \ 01076 ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \ 01077 ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 01078 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 01079 ((__RESOLUTION__) == ADC_RESOLUTION_8B) ) 01080 #endif /* ADC_VER_V5_V90*/ 01081 01082 /** 01083 * @brief Verify the ADC resolution setting when limited to 8 bits. 01084 * @param __RESOLUTION__ programmed ADC resolution when limited to 8 bits. 01085 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 01086 */ 01087 #define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B)) 01088 01089 #if defined(ADC_VER_V5_V90) 01090 /** 01091 * @brief Verify the ADC converted data alignment. Applicable for ADC3 on devices STM32H72xx and STM32H73xx. 01092 * @param __ALIGN__ programmed ADC converted data alignment. 01093 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 01094 */ 01095 #define IS_ADC3_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC3_DATAALIGN_RIGHT) || \ 01096 ((__ALIGN__) == ADC3_DATAALIGN_LEFT) ) 01097 01098 /** 01099 * @brief Verify the ADC regular conversions external trigger. 01100 * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger. 01101 * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid) 01102 */ 01103 #define IS_ADC3_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \ 01104 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \ 01105 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) ) 01106 01107 #endif 01108 01109 /** 01110 * @brief Verify the ADC scan mode. 01111 * @param __SCAN_MODE__ programmed ADC scan mode. 01112 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 01113 */ 01114 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 01115 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 01116 01117 /** 01118 * @brief Verify the ADC edge trigger setting for regular group. 01119 * @param __EDGE__ programmed ADC edge trigger setting. 01120 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 01121 */ 01122 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 01123 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 01124 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 01125 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 01126 01127 /** 01128 * @brief Verify the ADC regular conversions external trigger. 01129 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 01130 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 01131 */ 01132 #if defined(ADC_VER_V5_V90) 01133 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 01134 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 01135 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 01136 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 01137 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 01138 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 01139 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 01140 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 01141 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 01142 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 01143 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 01144 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 01145 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 01146 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 01147 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 01148 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 01149 ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1) || \ 01150 ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3) || \ 01151 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \ 01152 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \ 01153 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \ 01154 ((__REGTRIG__) == ADC_EXTERNALTRIG_T23_TRGO) || \ 01155 ((__REGTRIG__) == ADC_EXTERNALTRIG_T24_TRGO) || \ 01156 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 01157 #else 01158 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 01159 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 01160 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 01161 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 01162 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 01163 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 01164 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 01165 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 01166 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 01167 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 01168 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 01169 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 01170 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 01171 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 01172 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 01173 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 01174 ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1) || \ 01175 ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3) || \ 01176 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \ 01177 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \ 01178 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \ 01179 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 01180 #endif /* ADC_VER_V5_V90*/ 01181 01182 01183 /** 01184 * @brief Verify the ADC regular conversions check for converted data availability. 01185 * @param __EOC_SELECTION__ converted data availability check. 01186 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 01187 */ 01188 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 01189 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 01190 01191 /** 01192 * @brief Verify the ADC regular conversions overrun handling. 01193 * @param __OVR__ ADC regular conversions overrun handling. 01194 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 01195 */ 01196 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 01197 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 01198 01199 /** 01200 * @brief Verify the ADC conversions sampling time. 01201 * @param __TIME__ ADC conversions sampling time. 01202 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 01203 */ 01204 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \ 01205 ((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 01206 ((__TIME__) == ADC_SAMPLETIME_8CYCLES_5) || \ 01207 ((__TIME__) == ADC_SAMPLETIME_16CYCLES_5) || \ 01208 ((__TIME__) == ADC_SAMPLETIME_32CYCLES_5) || \ 01209 ((__TIME__) == ADC_SAMPLETIME_64CYCLES_5) || \ 01210 ((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \ 01211 ((__TIME__) == ADC_SAMPLETIME_810CYCLES_5) ) 01212 01213 /** 01214 * @brief Verify the ADC regular channel setting. 01215 * @param __CHANNEL__ programmed ADC regular channel. 01216 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 01217 */ 01218 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 01219 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 01220 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 01221 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 01222 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 01223 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 01224 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 01225 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 01226 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 01227 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 01228 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 01229 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 01230 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 01231 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 01232 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 01233 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 01234 01235 /** 01236 * @} 01237 */ 01238 01239 01240 /* Private constants ---------------------------------------------------------*/ 01241 01242 /** @defgroup ADC_Private_Constants ADC Private Constants 01243 * @{ 01244 */ 01245 01246 /* Fixed timeout values for ADC conversion (including sampling time) */ 01247 /* Maximum sampling time is 810.5 ADC clock cycle */ 01248 /* Maximum conversion time is 16.5 + Maximum sampling time */ 01249 /* or 16.5 + 810.5 = 827 ADC clock cycles */ 01250 /* Minimum ADC Clock frequency is 0.35 MHz */ 01251 /* Maximum conversion time is */ 01252 /* 827 / 0.35 MHz = 2.36 ms */ 01253 01254 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 01255 01256 /* Delay for temperature sensor stabilization time. */ 01257 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 01258 /* Unit: us */ 01259 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 01260 01261 /* Delay for ADC voltage regulator startup time */ 01262 /* Maximum delay is 10 microseconds */ 01263 /* (refer device RM, parameter Tadcvreg_stup). */ 01264 #define ADC_STAB_DELAY_US (10UL) /*!< ADC voltage regulator startup time */ 01265 01266 /** 01267 * @} 01268 */ 01269 01270 /* Exported macro ------------------------------------------------------------*/ 01271 01272 /** @defgroup ADC_Exported_Macros ADC Exported Macros 01273 * @{ 01274 */ 01275 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 01276 /* final user. */ 01277 01278 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 01279 * @{ 01280 */ 01281 01282 /** @brief Reset ADC handle state. 01283 * @param __HANDLE__ ADC handle 01284 * @retval None 01285 */ 01286 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 01287 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 01288 do{ \ 01289 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 01290 (__HANDLE__)->MspInitCallback = NULL; \ 01291 (__HANDLE__)->MspDeInitCallback = NULL; \ 01292 } while(0) 01293 #else 01294 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 01295 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 01296 #endif 01297 01298 /** 01299 * @brief Enable ADC interrupt. 01300 * @param __HANDLE__ ADC handle 01301 * @param __INTERRUPT__ ADC Interrupt 01302 * This parameter can be one of the following values: 01303 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 01304 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 01305 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 01306 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 01307 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 01308 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 01309 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 01310 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 01311 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 01312 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 01313 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 01314 * @retval None 01315 */ 01316 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 01317 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 01318 01319 /** 01320 * @brief Disable ADC interrupt. 01321 * @param __HANDLE__ ADC handle 01322 * @param __INTERRUPT__ ADC Interrupt 01323 * This parameter can be one of the following values: 01324 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 01325 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 01326 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 01327 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 01328 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 01329 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 01330 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 01331 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 01332 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 01333 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 01334 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 01335 * @retval None 01336 */ 01337 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 01338 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 01339 01340 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 01341 * @param __HANDLE__ ADC handle 01342 * @param __INTERRUPT__ ADC interrupt source to check 01343 * This parameter can be one of the following values: 01344 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 01345 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 01346 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 01347 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 01348 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 01349 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 01350 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 01351 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 01352 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 01353 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 01354 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 01355 * @retval State of interruption (SET or RESET) 01356 */ 01357 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 01358 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 01359 01360 /** 01361 * @brief Check whether the specified ADC flag is set or not. 01362 * @param __HANDLE__ ADC handle 01363 * @param __FLAG__ ADC flag 01364 * This parameter can be one of the following values: 01365 * @arg @ref ADC_FLAG_RDY ADC Ready flag 01366 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 01367 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 01368 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 01369 * @arg @ref ADC_FLAG_OVR ADC overrun flag 01370 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 01371 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 01372 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 01373 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 01374 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 01375 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 01376 * @retval State of flag (TRUE or FALSE). 01377 */ 01378 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 01379 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 01380 01381 /** 01382 * @brief Clear the specified ADC flag. 01383 * @param __HANDLE__ ADC handle 01384 * @param __FLAG__ ADC flag 01385 * This parameter can be one of the following values: 01386 * @arg @ref ADC_FLAG_RDY ADC Ready flag 01387 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 01388 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 01389 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 01390 * @arg @ref ADC_FLAG_OVR ADC overrun flag 01391 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 01392 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 01393 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 01394 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 01395 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 01396 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 01397 * @retval None 01398 */ 01399 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 01400 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 01401 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 01402 01403 /** 01404 * @} 01405 */ 01406 01407 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 01408 * @{ 01409 */ 01410 01411 /** 01412 * @brief Helper macro to get ADC channel number in decimal format 01413 * from literals ADC_CHANNEL_x. 01414 * @note Example: 01415 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 01416 * will return decimal number "4". 01417 * @note The input can be a value from functions where a channel 01418 * number is returned, either defined with number 01419 * or with bitfield (only one bit must be set). 01420 * @param __CHANNEL__ This parameter can be one of the following values: 01421 * @arg @ref ADC_CHANNEL_0 (3) 01422 * @arg @ref ADC_CHANNEL_1 (3) 01423 * @arg @ref ADC_CHANNEL_2 (3) 01424 * @arg @ref ADC_CHANNEL_3 (3) 01425 * @arg @ref ADC_CHANNEL_4 (3) 01426 * @arg @ref ADC_CHANNEL_5 (3) 01427 * @arg @ref ADC_CHANNEL_6 01428 * @arg @ref ADC_CHANNEL_7 01429 * @arg @ref ADC_CHANNEL_8 01430 * @arg @ref ADC_CHANNEL_9 01431 * @arg @ref ADC_CHANNEL_10 01432 * @arg @ref ADC_CHANNEL_11 01433 * @arg @ref ADC_CHANNEL_12 01434 * @arg @ref ADC_CHANNEL_13 01435 * @arg @ref ADC_CHANNEL_14 01436 * @arg @ref ADC_CHANNEL_15 01437 * @arg @ref ADC_CHANNEL_16 01438 * @arg @ref ADC_CHANNEL_17 01439 * @arg @ref ADC_CHANNEL_18 01440 * @arg @ref ADC_CHANNEL_VREFINT (1) 01441 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 01442 * @arg @ref ADC_CHANNEL_VBAT (1) 01443 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2) 01444 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2) 01445 * 01446 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n 01447 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n 01448 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 01449 * Other channels are slow channels (conversion rate: refer to reference manual). 01450 * @retval Value between Min_Data=0 and Max_Data=18 01451 */ 01452 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 01453 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 01454 01455 /** 01456 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 01457 * from number in decimal format. 01458 * @note Example: 01459 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 01460 * will return a data equivalent to "ADC_CHANNEL_4". 01461 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 01462 * @retval Returned value can be one of the following values: 01463 * @arg @ref ADC_CHANNEL_0 (3) 01464 * @arg @ref ADC_CHANNEL_1 (3) 01465 * @arg @ref ADC_CHANNEL_2 (3) 01466 * @arg @ref ADC_CHANNEL_3 (3) 01467 * @arg @ref ADC_CHANNEL_4 (3) 01468 * @arg @ref ADC_CHANNEL_5 (3) 01469 * @arg @ref ADC_CHANNEL_6 01470 * @arg @ref ADC_CHANNEL_7 01471 * @arg @ref ADC_CHANNEL_8 01472 * @arg @ref ADC_CHANNEL_9 01473 * @arg @ref ADC_CHANNEL_10 01474 * @arg @ref ADC_CHANNEL_11 01475 * @arg @ref ADC_CHANNEL_12 01476 * @arg @ref ADC_CHANNEL_13 01477 * @arg @ref ADC_CHANNEL_14 01478 * @arg @ref ADC_CHANNEL_15 01479 * @arg @ref ADC_CHANNEL_16 01480 * @arg @ref ADC_CHANNEL_17 01481 * @arg @ref ADC_CHANNEL_18 01482 * @arg @ref ADC_CHANNEL_VREFINT (1) 01483 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 01484 * @arg @ref ADC_CHANNEL_VBAT (1) 01485 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2) 01486 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2) 01487 * 01488 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n 01489 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n 01490 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 01491 * Other channels are slow channels (conversion rate: refer to reference manual).\n 01492 * (1, 2) For ADC channel read back from ADC register, 01493 * comparison with internal channel parameter to be done 01494 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01495 */ 01496 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 01497 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 01498 01499 /** 01500 * @brief Helper macro to determine whether the selected channel 01501 * corresponds to literal definitions of driver. 01502 * @note The different literal definitions of ADC channels are: 01503 * - ADC internal channel: 01504 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 01505 * - ADC external channel (channel connected to a GPIO pin): 01506 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 01507 * @note The channel parameter must be a value defined from literal 01508 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 01509 * ADC_CHANNEL_TEMPSENSOR, ...), 01510 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 01511 * must not be a value from functions where a channel number is 01512 * returned from ADC registers, 01513 * because internal and external channels share the same channel 01514 * number in ADC registers. The differentiation is made only with 01515 * parameters definitions of driver. 01516 * @param __CHANNEL__ This parameter can be one of the following values: 01517 * @arg @ref ADC_CHANNEL_0 (3) 01518 * @arg @ref ADC_CHANNEL_1 (3) 01519 * @arg @ref ADC_CHANNEL_2 (3) 01520 * @arg @ref ADC_CHANNEL_3 (3) 01521 * @arg @ref ADC_CHANNEL_4 (3) 01522 * @arg @ref ADC_CHANNEL_5 (3) 01523 * @arg @ref ADC_CHANNEL_6 01524 * @arg @ref ADC_CHANNEL_7 01525 * @arg @ref ADC_CHANNEL_8 01526 * @arg @ref ADC_CHANNEL_9 01527 * @arg @ref ADC_CHANNEL_10 01528 * @arg @ref ADC_CHANNEL_11 01529 * @arg @ref ADC_CHANNEL_12 01530 * @arg @ref ADC_CHANNEL_13 01531 * @arg @ref ADC_CHANNEL_14 01532 * @arg @ref ADC_CHANNEL_15 01533 * @arg @ref ADC_CHANNEL_16 01534 * @arg @ref ADC_CHANNEL_17 01535 * @arg @ref ADC_CHANNEL_18 01536 * @arg @ref ADC_CHANNEL_VREFINT (1) 01537 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 01538 * @arg @ref ADC_CHANNEL_VBAT (1) 01539 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2) 01540 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2) 01541 * 01542 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n 01543 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n 01544 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 01545 * Other channels are slow channels (conversion rate: refer to reference manual). 01546 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 01547 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 01548 */ 01549 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 01550 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 01551 01552 /** 01553 * @brief Helper macro to convert a channel defined from parameter 01554 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 01555 * ADC_CHANNEL_TEMPSENSOR, ...), 01556 * to its equivalent parameter definition of a ADC external channel 01557 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 01558 * @note The channel parameter can be, additionally to a value 01559 * defined from parameter definition of a ADC internal channel 01560 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 01561 * a value defined from parameter definition of 01562 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 01563 * or a value from functions where a channel number is returned 01564 * from ADC registers. 01565 * @param __CHANNEL__ This parameter can be one of the following values: 01566 * @arg @ref ADC_CHANNEL_0 (3) 01567 * @arg @ref ADC_CHANNEL_1 (3) 01568 * @arg @ref ADC_CHANNEL_2 (3) 01569 * @arg @ref ADC_CHANNEL_3 (3) 01570 * @arg @ref ADC_CHANNEL_4 (3) 01571 * @arg @ref ADC_CHANNEL_5 (3) 01572 * @arg @ref ADC_CHANNEL_6 01573 * @arg @ref ADC_CHANNEL_7 01574 * @arg @ref ADC_CHANNEL_8 01575 * @arg @ref ADC_CHANNEL_9 01576 * @arg @ref ADC_CHANNEL_10 01577 * @arg @ref ADC_CHANNEL_11 01578 * @arg @ref ADC_CHANNEL_12 01579 * @arg @ref ADC_CHANNEL_13 01580 * @arg @ref ADC_CHANNEL_14 01581 * @arg @ref ADC_CHANNEL_15 01582 * @arg @ref ADC_CHANNEL_16 01583 * @arg @ref ADC_CHANNEL_17 01584 * @arg @ref ADC_CHANNEL_18 01585 * @arg @ref ADC_CHANNEL_VREFINT (1) 01586 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 01587 * @arg @ref ADC_CHANNEL_VBAT (1) 01588 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2) 01589 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2) 01590 * 01591 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n 01592 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n 01593 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 01594 * Other channels are slow channels (conversion rate: refer to reference manual). 01595 * @retval Returned value can be one of the following values: 01596 * @arg @ref ADC_CHANNEL_0 01597 * @arg @ref ADC_CHANNEL_1 01598 * @arg @ref ADC_CHANNEL_2 01599 * @arg @ref ADC_CHANNEL_3 01600 * @arg @ref ADC_CHANNEL_4 01601 * @arg @ref ADC_CHANNEL_5 01602 * @arg @ref ADC_CHANNEL_6 01603 * @arg @ref ADC_CHANNEL_7 01604 * @arg @ref ADC_CHANNEL_8 01605 * @arg @ref ADC_CHANNEL_9 01606 * @arg @ref ADC_CHANNEL_10 01607 * @arg @ref ADC_CHANNEL_11 01608 * @arg @ref ADC_CHANNEL_12 01609 * @arg @ref ADC_CHANNEL_13 01610 * @arg @ref ADC_CHANNEL_14 01611 * @arg @ref ADC_CHANNEL_15 01612 * @arg @ref ADC_CHANNEL_16 01613 * @arg @ref ADC_CHANNEL_17 01614 * @arg @ref ADC_CHANNEL_18 01615 */ 01616 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 01617 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 01618 01619 /** 01620 * @brief Helper macro to determine whether the internal channel 01621 * selected is available on the ADC instance selected. 01622 * @note The channel parameter must be a value defined from parameter 01623 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 01624 * ADC_CHANNEL_TEMPSENSOR, ...), 01625 * must not be a value defined from parameter definition of 01626 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 01627 * or a value from functions where a channel number is 01628 * returned from ADC registers, 01629 * because internal and external channels share the same channel 01630 * number in ADC registers. The differentiation is made only with 01631 * parameters definitions of driver. 01632 * @param __ADC_INSTANCE__ ADC instance 01633 * @param __CHANNEL__ This parameter can be one of the following values: 01634 * @arg @ref ADC_CHANNEL_VREFINT (1) 01635 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 01636 * @arg @ref ADC_CHANNEL_VBAT (1) 01637 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2) 01638 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2) 01639 * 01640 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n 01641 * (2) On STM32H7, parameter available only on ADC instance: ADC2. 01642 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 01643 * Value "1" if the internal channel selected is available on the ADC instance selected. 01644 */ 01645 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 01646 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 01647 01648 /** 01649 * @brief Helper macro to get the ADC multimode conversion data of ADC master 01650 * or ADC slave from raw value with both ADC conversion data concatenated. 01651 * @note This macro is intended to be used when multimode transfer by DMA 01652 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 01653 * In this case the transferred data need to processed with this macro 01654 * to separate the conversion data of ADC master and ADC slave. 01655 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 01656 * @arg @ref LL_ADC_MULTI_MASTER 01657 * @arg @ref LL_ADC_MULTI_SLAVE 01658 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 01659 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01660 */ 01661 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 01662 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 01663 01664 /** 01665 * @brief Helper macro to select the ADC common instance 01666 * to which is belonging the selected ADC instance. 01667 * @note ADC common register instance can be used for: 01668 * - Set parameters common to several ADC instances 01669 * - Multimode (for devices with several ADC instances) 01670 * Refer to functions having argument "ADCxy_COMMON" as parameter. 01671 * @param __ADCx__ ADC instance 01672 * @retval ADC common register instance 01673 */ 01674 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 01675 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 01676 01677 /** 01678 * @brief Helper macro to check if all ADC instances sharing the same 01679 * ADC common instance are disabled. 01680 * @note This check is required by functions with setting conditioned to 01681 * ADC state: 01682 * All ADC instances of the ADC common group must be disabled. 01683 * Refer to functions having argument "ADCxy_COMMON" as parameter. 01684 * @note On devices with only 1 ADC common instance, parameter of this macro 01685 * is useless and can be ignored (parameter kept for compatibility 01686 * with devices featuring several ADC common instances). 01687 * @param __ADCXY_COMMON__ ADC common instance 01688 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01689 * @retval Value "0" if all ADC instances sharing the same ADC common instance 01690 * are disabled. 01691 * Value "1" if at least one ADC instance sharing the same ADC common instance 01692 * is enabled. 01693 */ 01694 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 01695 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 01696 01697 /** 01698 * @brief Helper macro to define the ADC conversion data full-scale digital 01699 * value corresponding to the selected ADC resolution. 01700 * @note ADC conversion data full-scale corresponds to voltage range 01701 * determined by analog voltage references Vref+ and Vref- 01702 * (refer to reference manual). 01703 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01704 * @arg @ref ADC_RESOLUTION_16B 01705 * @arg @ref ADC_RESOLUTION_14B 01706 * @arg @ref ADC_RESOLUTION_12B 01707 * @arg @ref ADC_RESOLUTION_10B 01708 * @arg @ref ADC_RESOLUTION_8B 01709 * @retval ADC conversion data full-scale digital value 01710 */ 01711 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 01712 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 01713 01714 /** 01715 * @brief Helper macro to convert the ADC conversion data from 01716 * a resolution to another resolution. 01717 * @param __DATA__ ADC conversion data to be converted 01718 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 01719 * This parameter can be one of the following values: 01720 * @arg @ref ADC_RESOLUTION_16B 01721 * @arg @ref ADC_RESOLUTION_14B 01722 * @arg @ref ADC_RESOLUTION_12B 01723 * @arg @ref ADC_RESOLUTION_10B 01724 * @arg @ref ADC_RESOLUTION_8B 01725 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 01726 * This parameter can be one of the following values: 01727 * @arg @ref ADC_RESOLUTION_16B 01728 * @arg @ref ADC_RESOLUTION_14B 01729 * @arg @ref ADC_RESOLUTION_12B 01730 * @arg @ref ADC_RESOLUTION_10B 01731 * @arg @ref ADC_RESOLUTION_8B 01732 * @retval ADC conversion data to the requested resolution 01733 */ 01734 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 01735 __ADC_RESOLUTION_CURRENT__,\ 01736 __ADC_RESOLUTION_TARGET__) \ 01737 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 01738 (__ADC_RESOLUTION_CURRENT__),\ 01739 (__ADC_RESOLUTION_TARGET__)) 01740 01741 /** 01742 * @brief Helper macro to calculate the voltage (unit: mVolt) 01743 * corresponding to a ADC conversion data (unit: digital value). 01744 * @note Analog reference voltage (Vref+) must be either known from 01745 * user board environment or can be calculated using ADC measurement 01746 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01747 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 01748 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 01749 * (unit: digital value). 01750 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01751 * @arg @ref ADC_RESOLUTION_16B 01752 * @arg @ref ADC_RESOLUTION_14B 01753 * @arg @ref ADC_RESOLUTION_12B 01754 * @arg @ref ADC_RESOLUTION_10B 01755 * @arg @ref ADC_RESOLUTION_8B 01756 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 01757 */ 01758 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 01759 __ADC_DATA__,\ 01760 __ADC_RESOLUTION__) \ 01761 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 01762 (__ADC_DATA__),\ 01763 (__ADC_RESOLUTION__)) 01764 01765 /** 01766 * @brief Helper macro to calculate analog reference voltage (Vref+) 01767 * (unit: mVolt) from ADC conversion data of internal voltage 01768 * reference VrefInt. 01769 * @note Computation is using VrefInt calibration value 01770 * stored in system memory for each device during production. 01771 * @note This voltage depends on user board environment: voltage level 01772 * connected to pin Vref+. 01773 * On devices with small package, the pin Vref+ is not present 01774 * and internally bonded to pin Vdda. 01775 * @note On this STM32 series, calibration data of internal voltage reference 01776 * VrefInt corresponds to a resolution of 12 bits, 01777 * this is the recommended ADC resolution to convert voltage of 01778 * internal voltage reference VrefInt. 01779 * Otherwise, this macro performs the processing to scale 01780 * ADC conversion data to 12 bits. 01781 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 01782 * of internal voltage reference VrefInt (unit: digital value). 01783 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01784 * @arg @ref ADC_RESOLUTION_16B 01785 * @arg @ref ADC_RESOLUTION_14B 01786 * @arg @ref ADC_RESOLUTION_12B 01787 * @arg @ref ADC_RESOLUTION_10B 01788 * @arg @ref ADC_RESOLUTION_8B 01789 * @retval Analog reference voltage (unit: mV) 01790 */ 01791 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 01792 __ADC_RESOLUTION__) \ 01793 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 01794 (__ADC_RESOLUTION__)) 01795 01796 /** 01797 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 01798 * from ADC conversion data of internal temperature sensor. 01799 * @note Computation is using temperature sensor calibration values 01800 * stored in system memory for each device during production. 01801 * @note Calculation formula: 01802 * Temperature = ((TS_ADC_DATA - TS_CAL1) 01803 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 01804 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 01805 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 01806 * Avg_Slope = (TS_CAL2 - TS_CAL1) 01807 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 01808 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 01809 * TEMP_DEGC_CAL1 (calibrated in factory) 01810 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 01811 * TEMP_DEGC_CAL2 (calibrated in factory) 01812 * Caution: Calculation relevancy under reserve that calibration 01813 * parameters are correct (address and data). 01814 * To calculate temperature using temperature sensor 01815 * datasheet typical values (generic values less, therefore 01816 * less accurate than calibrated values), 01817 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 01818 * @note As calculation input, the analog reference voltage (Vref+) must be 01819 * defined as it impacts the ADC LSB equivalent voltage. 01820 * @note Analog reference voltage (Vref+) must be either known from 01821 * user board environment or can be calculated using ADC measurement 01822 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01823 * @note On this STM32 series, calibration data of temperature sensor 01824 * corresponds to a resolution of 12 bits, 01825 * this is the recommended ADC resolution to convert voltage of 01826 * temperature sensor. 01827 * Otherwise, this macro performs the processing to scale 01828 * ADC conversion data to 12 bits. 01829 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 01830 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 01831 * temperature sensor (unit: digital value). 01832 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 01833 * sensor voltage has been measured. 01834 * This parameter can be one of the following values: 01835 * @arg @ref ADC_RESOLUTION_16B 01836 * @arg @ref ADC_RESOLUTION_14B 01837 * @arg @ref ADC_RESOLUTION_12B 01838 * @arg @ref ADC_RESOLUTION_10B 01839 * @arg @ref ADC_RESOLUTION_8B 01840 * @retval Temperature (unit: degree Celsius) 01841 */ 01842 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 01843 __TEMPSENSOR_ADC_DATA__,\ 01844 __ADC_RESOLUTION__) \ 01845 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 01846 (__TEMPSENSOR_ADC_DATA__),\ 01847 (__ADC_RESOLUTION__)) 01848 01849 /** 01850 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 01851 * from ADC conversion data of internal temperature sensor. 01852 * @note Computation is using temperature sensor typical values 01853 * (refer to device datasheet). 01854 * @note Calculation formula: 01855 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 01856 * / Avg_Slope + CALx_TEMP 01857 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 01858 * (unit: digital value) 01859 * Avg_Slope = temperature sensor slope 01860 * (unit: uV/Degree Celsius) 01861 * TS_TYP_CALx_VOLT = temperature sensor digital value at 01862 * temperature CALx_TEMP (unit: mV) 01863 * Caution: Calculation relevancy under reserve the temperature sensor 01864 * of the current device has characteristics in line with 01865 * datasheet typical values. 01866 * If temperature sensor calibration values are available on 01867 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 01868 * temperature calculation will be more accurate using 01869 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 01870 * @note As calculation input, the analog reference voltage (Vref+) must be 01871 * defined as it impacts the ADC LSB equivalent voltage. 01872 * @note Analog reference voltage (Vref+) must be either known from 01873 * user board environment or can be calculated using ADC measurement 01874 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01875 * @note ADC measurement data must correspond to a resolution of 12bits 01876 * (full scale digital value 4095). If not the case, the data must be 01877 * preliminarily rescaled to an equivalent resolution of 12 bits. 01878 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 01879 * On STM32H7, refer to device datasheet parameter "Avg_Slope". 01880 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 01881 * On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 01882 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 01883 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 01884 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 01885 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 01886 * This parameter can be one of the following values: 01887 * @arg @ref ADC_RESOLUTION_16B 01888 * @arg @ref ADC_RESOLUTION_14B 01889 * @arg @ref ADC_RESOLUTION_12B 01890 * @arg @ref ADC_RESOLUTION_10B 01891 * @arg @ref ADC_RESOLUTION_8B 01892 * @retval Temperature (unit: degree Celsius) 01893 */ 01894 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 01895 __TEMPSENSOR_TYP_CALX_V__,\ 01896 __TEMPSENSOR_CALX_TEMP__,\ 01897 __VREFANALOG_VOLTAGE__,\ 01898 __TEMPSENSOR_ADC_DATA__,\ 01899 __ADC_RESOLUTION__) \ 01900 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 01901 (__TEMPSENSOR_TYP_CALX_V__),\ 01902 (__TEMPSENSOR_CALX_TEMP__),\ 01903 (__VREFANALOG_VOLTAGE__),\ 01904 (__TEMPSENSOR_ADC_DATA__),\ 01905 (__ADC_RESOLUTION__)) 01906 01907 /** 01908 * @} 01909 */ 01910 01911 /** 01912 * @} 01913 */ 01914 01915 /* Include ADC HAL Extended module */ 01916 #include "stm32h7xx_hal_adc_ex.h" 01917 01918 /* Exported functions --------------------------------------------------------*/ 01919 /** @addtogroup ADC_Exported_Functions 01920 * @{ 01921 */ 01922 01923 /** @addtogroup ADC_Exported_Functions_Group1 01924 * @brief Initialization and Configuration functions 01925 * @{ 01926 */ 01927 /* Initialization and de-initialization functions ****************************/ 01928 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 01929 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 01930 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 01931 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 01932 01933 01934 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 01935 /* Callbacks Register/UnRegister functions ***********************************/ 01936 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); 01937 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 01938 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 01939 /** 01940 * @} 01941 */ 01942 01943 /** @addtogroup ADC_Exported_Functions_Group2 01944 * @brief IO operation functions 01945 * @{ 01946 */ 01947 /* IO operation functions *****************************************************/ 01948 01949 /* Blocking mode: Polling */ 01950 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 01951 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 01952 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 01953 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 01954 01955 /* Non-blocking mode: Interruption */ 01956 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 01957 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 01958 01959 /* Non-blocking mode: DMA */ 01960 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 01961 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 01962 01963 /* ADC retrieve conversion value intended to be used with polling or interruption */ 01964 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); 01965 01966 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 01967 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 01968 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 01969 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 01970 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 01971 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 01972 /** 01973 * @} 01974 */ 01975 01976 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 01977 * @brief Peripheral Control functions 01978 * @{ 01979 */ 01980 /* Peripheral Control functions ***********************************************/ 01981 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); 01982 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); 01983 01984 /** 01985 * @} 01986 */ 01987 01988 /* Peripheral State functions *************************************************/ 01989 /** @addtogroup ADC_Exported_Functions_Group4 01990 * @{ 01991 */ 01992 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); 01993 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 01994 01995 /** 01996 * @} 01997 */ 01998 01999 /** 02000 * @} 02001 */ 02002 02003 /* Private functions -----------------------------------------------------------*/ 02004 /** @addtogroup ADC_Private_Functions ADC Private Functions 02005 * @{ 02006 */ 02007 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 02008 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 02009 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 02010 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 02011 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 02012 void ADC_DMAError(DMA_HandleTypeDef *hdma); 02013 void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc); 02014 02015 /** 02016 * @} 02017 */ 02018 02019 /** 02020 * @} 02021 */ 02022 02023 /** 02024 * @} 02025 */ 02026 02027 #ifdef __cplusplus 02028 } 02029 #endif 02030 02031 02032 #endif /* STM32H7xx_HAL_ADC_H */ 02033
1.7.6.1