ADC group regular sampling mode

Defines
#define	ADC_SAMPLING_MODE_NORMAL   (0x00000000UL)
#define	ADC_SAMPLING_MODE_BULB   (ADC3_CFGR2_BULB)
#define	ADC_SAMPLING_MODE_TRIGGER_CONTROLED   (ADC3_CFGR2_SMPTRIG)

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Define Documentation

#define ADC_SAMPLING_MODE_BULB   (ADC3_CFGR2_BULB)

ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. Notes:

• First conversion is using minimal sampling time (see Channel - Sampling time)
• Applicable for ADC3 on devices STM32H72xx and STM32H73xx

Definition at line 601 of file stm32h7xx_hal_adc.h.

#define ADC_SAMPLING_MODE_NORMAL   (0x00000000UL)

ADC conversions sampling phase duration is defined using Channel - Sampling time

Definition at line 600 of file stm32h7xx_hal_adc.h.

#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED   (ADC3_CFGR2_SMPTRIG)

ADC conversions sampling phase is controlled by trigger events: Trigger rising edge = start sampling Trigger falling edge = stop sampling and start conversion Note: Applicable for ADC3 on devices STM32H72xx and STM32H73xx

Definition at line 605 of file stm32h7xx_hal_adc.h.