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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_fdcan.h 00004 * @author MCD Application Team 00005 * @brief Header file of FDCAN HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_FDCAN_H 00021 #define STM32H7xx_HAL_FDCAN_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx_hal_def.h" 00029 00030 #if defined(FDCAN1) 00031 00032 /** @addtogroup STM32H7xx_HAL_Driver 00033 * @{ 00034 */ 00035 00036 /** @addtogroup FDCAN 00037 * @{ 00038 */ 00039 00040 /* Exported types ------------------------------------------------------------*/ 00041 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types 00042 * @{ 00043 */ 00044 00045 /** 00046 * @brief HAL State structures definition 00047 */ 00048 typedef enum 00049 { 00050 HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */ 00051 HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */ 00052 HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */ 00053 HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */ 00054 } HAL_FDCAN_StateTypeDef; 00055 00056 /** 00057 * @brief FDCAN Init structure definition 00058 */ 00059 typedef struct 00060 { 00061 uint32_t FrameFormat; /*!< Specifies the FDCAN frame format. 00062 This parameter can be a value of @ref FDCAN_frame_format */ 00063 00064 uint32_t Mode; /*!< Specifies the FDCAN mode. 00065 This parameter can be a value of @ref FDCAN_operating_mode */ 00066 00067 FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode. 00068 This parameter can be set to ENABLE or DISABLE */ 00069 00070 FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature. 00071 This parameter can be set to ENABLE or DISABLE */ 00072 00073 FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling. 00074 This parameter can be set to ENABLE or DISABLE */ 00075 00076 uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is 00077 divided for generating the nominal bit time quanta. 00078 This parameter must be a number between 1 and 512 */ 00079 00080 uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 00081 hardware is allowed to lengthen or shorten a bit to perform 00082 resynchronization. 00083 This parameter must be a number between 1 and 128 */ 00084 00085 uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. 00086 This parameter must be a number between 2 and 256 */ 00087 00088 uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. 00089 This parameter must be a number between 2 and 128 */ 00090 00091 uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is 00092 divided for generating the data bit time quanta. 00093 This parameter must be a number between 1 and 32 */ 00094 00095 uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 00096 hardware is allowed to lengthen or shorten a data bit to 00097 perform resynchronization. 00098 This parameter must be a number between 1 and 16 */ 00099 00100 uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. 00101 This parameter must be a number between 1 and 32 */ 00102 00103 uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. 00104 This parameter must be a number between 1 and 16 */ 00105 00106 uint32_t MessageRAMOffset; /*!< Specifies the message RAM start address. 00107 This parameter must be a number between 0 and 2560 */ 00108 00109 uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters. 00110 This parameter must be a number between 0 and 128 */ 00111 00112 uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters. 00113 This parameter must be a number between 0 and 64 */ 00114 00115 uint32_t RxFifo0ElmtsNbr; /*!< Specifies the number of Rx FIFO0 Elements. 00116 This parameter must be a number between 0 and 64 */ 00117 00118 uint32_t RxFifo0ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 0 element. 00119 This parameter can be a value of @ref FDCAN_data_field_size */ 00120 00121 uint32_t RxFifo1ElmtsNbr; /*!< Specifies the number of Rx FIFO 1 Elements. 00122 This parameter must be a number between 0 and 64 */ 00123 00124 uint32_t RxFifo1ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 1 element. 00125 This parameter can be a value of @ref FDCAN_data_field_size */ 00126 00127 uint32_t RxBuffersNbr; /*!< Specifies the number of Dedicated Rx Buffer elements. 00128 This parameter must be a number between 0 and 64 */ 00129 00130 uint32_t RxBufferSize; /*!< Specifies the Data Field Size in an Rx Buffer element. 00131 This parameter can be a value of @ref FDCAN_data_field_size */ 00132 00133 uint32_t TxEventsNbr; /*!< Specifies the number of Tx Event FIFO elements. 00134 This parameter must be a number between 0 and 32 */ 00135 00136 uint32_t TxBuffersNbr; /*!< Specifies the number of Dedicated Tx Buffers. 00137 This parameter must be a number between 0 and 32 */ 00138 00139 uint32_t TxFifoQueueElmtsNbr; /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue. 00140 This parameter must be a number between 0 and 32 */ 00141 00142 uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection. 00143 This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */ 00144 00145 uint32_t TxElmtSize; /*!< Specifies the Data Field Size in a Tx Element. 00146 This parameter can be a value of @ref FDCAN_data_field_size */ 00147 00148 } FDCAN_InitTypeDef; 00149 00150 /** 00151 * @brief FDCAN clock calibration unit structure definition 00152 */ 00153 typedef struct 00154 { 00155 uint32_t ClockCalibration; /*!< Enable or disable the clock calibration. 00156 This parameter can be a value of @ref FDCAN_clock_calibration. */ 00157 00158 uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider when the clock calibration 00159 is bypassed. 00160 This parameter can be a value of @ref FDCAN_clock_divider */ 00161 00162 uint32_t MinOscClkPeriods; /*!< Configures the minimum number of periods in two CAN bit times. The 00163 actual configured number of periods is MinOscClkPeriods x 32. 00164 This parameter must be a number between 0x00 and 0xFF */ 00165 00166 uint32_t CalFieldLength; /*!< Specifies the calibration field length. 00167 This parameter can be a value of @ref FDCAN_calibration_field_length */ 00168 00169 uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time. 00170 This parameter must be a number between 4 and 25 */ 00171 00172 uint32_t WatchdogStartValue; /*!< Start value of the Calibration Watchdog Counter. 00173 If set to zero the counter is disabled. 00174 This parameter must be a number between 0x0000 and 0xFFFF */ 00175 00176 } FDCAN_ClkCalUnitTypeDef; 00177 00178 /** 00179 * @brief FDCAN filter structure definition 00180 */ 00181 typedef struct 00182 { 00183 uint32_t IdType; /*!< Specifies the identifier type. 00184 This parameter can be a value of @ref FDCAN_id_type */ 00185 00186 uint32_t FilterIndex; /*!< Specifies the filter which will be initialized. 00187 This parameter must be a number between: 00188 - 0 and 127, if IdType is FDCAN_STANDARD_ID 00189 - 0 and 63, if IdType is FDCAN_EXTENDED_ID */ 00190 00191 uint32_t FilterType; /*!< Specifies the filter type. 00192 This parameter can be a value of @ref FDCAN_filter_type. 00193 The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted 00194 only when IdType is FDCAN_EXTENDED_ID. 00195 This parameter is ignored if FilterConfig is set to 00196 FDCAN_FILTER_TO_RXBUFFER */ 00197 00198 uint32_t FilterConfig; /*!< Specifies the filter configuration. 00199 This parameter can be a value of @ref FDCAN_filter_config */ 00200 00201 uint32_t FilterID1; /*!< Specifies the filter identification 1. 00202 This parameter must be a number between: 00203 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 00204 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 00205 00206 uint32_t FilterID2; /*!< Specifies the filter identification 2. 00207 This parameter is ignored if FilterConfig is set to 00208 FDCAN_FILTER_TO_RXBUFFER. 00209 This parameter must be a number between: 00210 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 00211 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 00212 00213 uint32_t RxBufferIndex; /*!< Contains the index of the Rx buffer in which the 00214 matching message will be stored. 00215 This parameter must be a number between 0 and 63. 00216 This parameter is ignored if FilterConfig is different 00217 from FDCAN_FILTER_TO_RXBUFFER */ 00218 00219 uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for 00220 calibration messages. 00221 This parameter is ignored if FilterConfig is different 00222 from FDCAN_FILTER_TO_RXBUFFER. 00223 This parameter can be: 00224 - 0 : ordinary message 00225 - 1 : calibration message */ 00226 00227 } FDCAN_FilterTypeDef; 00228 00229 /** 00230 * @brief FDCAN Tx header structure definition 00231 */ 00232 typedef struct 00233 { 00234 uint32_t Identifier; /*!< Specifies the identifier. 00235 This parameter must be a number between: 00236 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 00237 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 00238 00239 uint32_t IdType; /*!< Specifies the identifier type for the message that will be 00240 transmitted. 00241 This parameter can be a value of @ref FDCAN_id_type */ 00242 00243 uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted. 00244 This parameter can be a value of @ref FDCAN_frame_type */ 00245 00246 uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted. 00247 This parameter can be a value of @ref FDCAN_data_length_code */ 00248 00249 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 00250 This parameter can be a value of @ref FDCAN_error_state_indicator */ 00251 00252 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without 00253 bit rate switching. 00254 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 00255 00256 uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or 00257 FD format. 00258 This parameter can be a value of @ref FDCAN_format */ 00259 00260 uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control. 00261 This parameter can be a value of @ref FDCAN_EFC */ 00262 00263 uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO 00264 element for identification of Tx message status. 00265 This parameter must be a number between 0 and 0xFF */ 00266 00267 } FDCAN_TxHeaderTypeDef; 00268 00269 /** 00270 * @brief FDCAN Rx header structure definition 00271 */ 00272 typedef struct 00273 { 00274 uint32_t Identifier; /*!< Specifies the identifier. 00275 This parameter must be a number between: 00276 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 00277 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 00278 00279 uint32_t IdType; /*!< Specifies the identifier type of the received message. 00280 This parameter can be a value of @ref FDCAN_id_type */ 00281 00282 uint32_t RxFrameType; /*!< Specifies the the received message frame type. 00283 This parameter can be a value of @ref FDCAN_frame_type */ 00284 00285 uint32_t DataLength; /*!< Specifies the received frame length. 00286 This parameter can be a value of @ref FDCAN_data_length_code */ 00287 00288 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 00289 This parameter can be a value of @ref FDCAN_error_state_indicator */ 00290 00291 uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit 00292 rate switching. 00293 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 00294 00295 uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD 00296 format. 00297 This parameter can be a value of @ref FDCAN_format */ 00298 00299 uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 00300 reception. 00301 This parameter must be a number between 0 and 0xFFFF */ 00302 00303 uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. 00304 This parameter must be a number between: 00305 - 0 and 127, if IdType is FDCAN_STANDARD_ID 00306 - 0 and 63, if IdType is FDCAN_EXTENDED_ID */ 00307 00308 uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. 00309 Acceptance of non-matching frames may be enabled via 00310 HAL_FDCAN_ConfigGlobalFilter(). 00311 This parameter can be 0 or 1 */ 00312 00313 } FDCAN_RxHeaderTypeDef; 00314 00315 /** 00316 * @brief FDCAN Tx event FIFO structure definition 00317 */ 00318 typedef struct 00319 { 00320 uint32_t Identifier; /*!< Specifies the identifier. 00321 This parameter must be a number between: 00322 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 00323 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 00324 00325 uint32_t IdType; /*!< Specifies the identifier type for the transmitted message. 00326 This parameter can be a value of @ref FDCAN_id_type */ 00327 00328 uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message. 00329 This parameter can be a value of @ref FDCAN_frame_type */ 00330 00331 uint32_t DataLength; /*!< Specifies the length of the transmitted frame. 00332 This parameter can be a value of @ref FDCAN_data_length_code */ 00333 00334 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 00335 This parameter can be a value of @ref FDCAN_error_state_indicator */ 00336 00337 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit 00338 rate switching. 00339 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 00340 00341 uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD 00342 format. 00343 This parameter can be a value of @ref FDCAN_format */ 00344 00345 uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 00346 transmission. 00347 This parameter must be a number between 0 and 0xFFFF */ 00348 00349 uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element 00350 for identification of Tx message status. 00351 This parameter must be a number between 0 and 0xFF */ 00352 00353 uint32_t EventType; /*!< Specifies the event type. 00354 This parameter can be a value of @ref FDCAN_event_type */ 00355 00356 } FDCAN_TxEventFifoTypeDef; 00357 00358 /** 00359 * @brief FDCAN High Priority Message Status structure definition 00360 */ 00361 typedef struct 00362 { 00363 uint32_t FilterList; /*!< Specifies the filter list of the matching filter element. 00364 This parameter can be: 00365 - 0 : Standard Filter List 00366 - 1 : Extended Filter List */ 00367 00368 uint32_t FilterIndex; /*!< Specifies the index of matching filter element. 00369 This parameter can be a number between: 00370 - 0 and 127, if FilterList is 0 (Standard) 00371 - 0 and 63, if FilterList is 1 (Extended) */ 00372 00373 uint32_t MessageStorage; /*!< Specifies the HP Message Storage. 00374 This parameter can be a value of @ref FDCAN_hp_msg_storage */ 00375 00376 uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the 00377 message was stored. 00378 This parameter is valid only when MessageStorage is: 00379 FDCAN_HP_STORAGE_RXFIFO0 00380 or 00381 FDCAN_HP_STORAGE_RXFIFO1 */ 00382 00383 } FDCAN_HpMsgStatusTypeDef; 00384 00385 /** 00386 * @brief FDCAN Protocol Status structure definition 00387 */ 00388 typedef struct 00389 { 00390 uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. 00391 This parameter can be a value of @ref FDCAN_protocol_error_code */ 00392 00393 uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format 00394 frame with its BRS flag set. 00395 This parameter can be a value of @ref FDCAN_protocol_error_code */ 00396 00397 uint32_t Activity; /*!< Specifies the FDCAN module communication state. 00398 This parameter can be a value of @ref FDCAN_communication_state */ 00399 00400 uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. 00401 This parameter can be: 00402 - 0 : The FDCAN is in Error_Active state 00403 - 1 : The FDCAN is in Error_Passive state */ 00404 00405 uint32_t Warning; /*!< Specifies the FDCAN module warning status. 00406 This parameter can be: 00407 - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96 00408 - 1 : at least one of error counters has reached the Error_Warning limit of 96 */ 00409 00410 uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. 00411 This parameter can be: 00412 - 0 : The FDCAN is not in Bus_Off state 00413 - 1 : The FDCAN is in Bus_Off state */ 00414 00415 uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. 00416 This parameter can be: 00417 - 0 : Last received CAN FD message did not have its ESI flag set 00418 - 1 : Last received CAN FD message had its ESI flag set */ 00419 00420 uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. 00421 This parameter can be: 00422 - 0 : Last received CAN FD message did not have its BRS flag set 00423 - 1 : Last received CAN FD message had its BRS flag set */ 00424 00425 uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status. 00426 This parameter can be: 00427 - 0 : no CAN FD message received 00428 - 1 : CAN FD message received */ 00429 00430 uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. 00431 This parameter can be: 00432 - 0 : No protocol exception event occurred since last read access 00433 - 1 : Protocol exception event occurred */ 00434 00435 uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. 00436 This parameter can be a number between 0 and 127 */ 00437 00438 } FDCAN_ProtocolStatusTypeDef; 00439 00440 /** 00441 * @brief FDCAN Error Counters structure definition 00442 */ 00443 typedef struct 00444 { 00445 uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. 00446 This parameter can be a number between 0 and 255 */ 00447 00448 uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. 00449 This parameter can be a number between 0 and 127 */ 00450 00451 uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. 00452 This parameter can be: 00453 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128 00454 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */ 00455 00456 uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. 00457 This parameter can be a number between 0 and 255. 00458 This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt 00459 or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of 00460 TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ 00461 00462 } FDCAN_ErrorCountersTypeDef; 00463 00464 /** 00465 * @brief FDCAN TT Init structure definition 00466 */ 00467 typedef struct 00468 { 00469 uint32_t OperationMode; /*!< Specifies the FDCAN Operation Mode. 00470 This parameter can be a value of @ref FDCAN_operation_mode */ 00471 00472 uint32_t GapEnable; /*!< Specifies the FDCAN TT Operation. 00473 This parameter can be a value of @ref FDCAN_TT_operation. 00474 This parameter is ignored if OperationMode is set to 00475 FDCAN_TT_COMMUNICATION_LEVEL0 */ 00476 00477 uint32_t TimeMaster; /*!< Specifies whether the instance is a slave or a potential master. 00478 This parameter can be a value of @ref FDCAN_TT_time_master */ 00479 00480 uint32_t SyncDevLimit; /*!< Specifies the Synchronization Deviation Limit SDL of the TUR 00481 numerator : TUR = (Numerator +/- SDL) / Denominator. 00482 With : SDL = 2^(SyncDevLimit+5). 00483 This parameter must be a number between 0 and 7 */ 00484 00485 uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset. 00486 This parameter must be a number between 0 and 127 */ 00487 00488 uint32_t ExternalClkSync; /*!< Enable or disable External Clock Synchronization. 00489 This parameter can be a value of @ref FDCAN_TT_external_clk_sync. 00490 This parameter is ignored if OperationMode is set to 00491 FDCAN_TT_COMMUNICATION_LEVEL1 */ 00492 00493 uint32_t AppWdgLimit; /*!< Specifies the Application Watchdog Limit : maximum time after 00494 which the application has to serve the application watchdog. 00495 The application watchdog is incremented once each 256 NTUs. 00496 The application watchdog can be disabled by setting AppWdgLimit to 0. 00497 This parameter must be a number between 0 and 255. 00498 This parameter is ignored if OperationMode is set to 00499 FDCAN_TT_COMMUNICATION_LEVEL0 */ 00500 00501 uint32_t GlobalTimeFilter; /*!< Enable or disable Global Time Filtering. 00502 This parameter can be a value of @ref FDCAN_TT_global_time_filtering. 00503 This parameter is ignored if OperationMode is set to 00504 FDCAN_TT_COMMUNICATION_LEVEL1 */ 00505 00506 uint32_t ClockCalibration; /*!< Enable or disable Automatic Clock Calibration. 00507 This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration. 00508 This parameter is ignored if OperationMode is set to 00509 FDCAN_TT_COMMUNICATION_LEVEL1 */ 00510 00511 uint32_t EvtTrigPolarity; /*!< Specifies the Event Trigger Polarity. 00512 This parameter can be a value of @ref FDCAN_TT_event_trig_polarity. 00513 This parameter is ignored if OperationMode is set to 00514 FDCAN_TT_COMMUNICATION_LEVEL0 */ 00515 00516 uint32_t BasicCyclesNbr; /*!< Specifies the nubmer of basic cycles in the system matrix. 00517 This parameter can be a value of @ref FDCAN_TT_basic_cycle_number */ 00518 00519 uint32_t CycleStartSync; /*!< Enable or disable synchronization pulse output at pin fdcan1_soc. 00520 This parameter can be a value of @ref FDCAN_TT_cycle_start_sync */ 00521 00522 uint32_t TxEnableWindow; /*!< Specifies the length of Tx enable window in NTUs. 00523 This parameter must be a number between 1 and 16 */ 00524 00525 uint32_t ExpTxTrigNbr; /*!< Specifies the number of expected Tx_Triggers in the system matrix. 00526 This is the sum of Tx_Triggers for exclusive, single arbitrating and 00527 merged arbitrating windows. 00528 This parameter must be a number between 0 and 4095 */ 00529 00530 uint32_t TURNumerator; /*!< Specifies the TUR (Time Unit Ratio) numerator. 00531 It is adviced to set this parameter to the largest applicable value. 00532 This parameter must be a number between 0x10000 and 0x1FFFF */ 00533 00534 uint32_t TURDenominator; /*!< Specifies the TUR (Time Unit Ratio) denominator. 00535 This parameter must be a number between 0x0001 and 0x3FFF */ 00536 00537 uint32_t TriggerMemoryNbr; /*!< Specifies the number of trigger memory elements. 00538 This parameter must be a number between 0 and 64 */ 00539 00540 uint32_t StopWatchTrigSel; /*!< Specifies the input to be used as stop watch trigger. 00541 This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */ 00542 00543 uint32_t EventTrigSel; /*!< Specifies the input to be used as event trigger. 00544 This parameter can be a value of @ref FDCAN_TT_event_trig_selection */ 00545 00546 } FDCAN_TT_ConfigTypeDef; 00547 00548 /** 00549 * @brief FDCAN Trigger structure definition 00550 */ 00551 typedef struct 00552 { 00553 uint32_t TriggerIndex; /*!< Specifies the trigger which will be configured. 00554 This parameter must be a number between 0 and 63 */ 00555 00556 uint32_t TimeMark; /*!< Specifies the cycle time for which the trigger becomes active. 00557 This parameter must be a number between 0 and 0xFFFF */ 00558 00559 uint32_t RepeatFactor; /*!< Specifies the trigger repeat factor. 00560 This parameter can be a value of @ref FDCAN_TT_Repeat_Factor */ 00561 00562 uint32_t StartCycle; /*!< Specifies the index of the first cycle in which the trigger becomes active. 00563 This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. 00564 This parameter must be a number between 0 and RepeatFactor */ 00565 00566 uint32_t TmEventInt; /*!< Enable or disable the internal time mark event. 00567 If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element 00568 becomes active. 00569 This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal */ 00570 00571 uint32_t TmEventExt; /*!< Enable or disable the external time mark event. 00572 If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when 00573 trigger memory element becomes active. 00574 This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External */ 00575 00576 uint32_t TriggerType; /*!< Specifies the trigger type. 00577 This parameter can be a value of @ref FDCAN_TT_Trigger_Type */ 00578 00579 uint32_t FilterType; /*!< Specifies the filter identifier type. 00580 This parameter can be a value of @ref FDCAN_id_type */ 00581 00582 uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid. 00583 This parameter can be a value of @ref FDCAN_Tx_location. 00584 This parameter is taken in consideration only if the trigger is configured for 00585 transmission. */ 00586 00587 uint32_t FilterIndex; /*!< Specifies the filter for which the trigger is valid. 00588 This parameter is taken in consideration only if the trigger is configured for 00589 reception. 00590 This parameter must be a number between: 00591 - 0 and 127, if FilterType is FDCAN_STANDARD_ID 00592 - 0 and 63, if FilterType is FDCAN_EXTENDED_ID */ 00593 00594 } FDCAN_TriggerTypeDef; 00595 00596 /** 00597 * @brief FDCAN TT Operation Status structure definition 00598 */ 00599 typedef struct 00600 { 00601 uint32_t ErrorLevel; /*!< Specifies the type of the TT operation error level. 00602 This parameter can be a value of @ref FDCAN_TT_error_level */ 00603 00604 uint32_t MasterState; /*!< Specifies the type of the TT master state. 00605 This parameter can be a value of @ref FDCAN_TT_master_state */ 00606 00607 uint32_t SyncState; /*!< Specifies the type of the TT synchronization state. 00608 This parameter can be a value of @ref FDCAN_TT_sync_state */ 00609 00610 uint32_t GTimeQuality; /*!< Specifies the Quality of Global Time Phase. 00611 This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0. 00612 This parameter can be: 00613 - 0 : Global time not valid 00614 - 1 : Global time in phase with Time Master */ 00615 00616 uint32_t ClockQuality; /*!< Specifies the Quality of Clock Speed. 00617 This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1. 00618 This parameter can be: 00619 - 0 : Local clock speed not synchronized to Time Master clock speed 00620 - 1 : Synchronization Deviation = SDL */ 00621 00622 uint32_t RefTrigOffset; /*!< Specifies the Actual Reference Trigger Offset Value. 00623 This parameter can be a number between 0 and 0xFF */ 00624 00625 uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State. 00626 This parameter can be: 00627 - 0 : No global time preset pending 00628 - 1 : Node waits for the global time preset to take effect */ 00629 00630 uint32_t GapFinished; /*!< Specifies whether a Gap is finished. 00631 This parameter can be: 00632 - 0 : Reset at the end of each reference message 00633 - 1 : Gap finished */ 00634 00635 uint32_t MasterPriority; /*!< Specifies the Priority of actual Time Master. 00636 This parameter can be a number between 0 and 0x7 */ 00637 00638 uint32_t GapStarted; /*!< Specifies whether a Gap is started. 00639 This parameter can be: 00640 - 0 : No Gap in schedule 00641 - 1 : Gap time after Basic Cycle has started */ 00642 00643 uint32_t WaitForEvt; /*!< Specifies whether a Gap is annouced. 00644 This parameter can be: 00645 - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0 00646 - 1 : Reference message with Next_is_Gap = 1 received */ 00647 00648 uint32_t AppWdgEvt; /*!< Specifies the Application Watchdog State. 00649 This parameter can be: 00650 - 0 : Application Watchdog served in time 00651 - 1 : Failed to serve Application Watchdog in time */ 00652 00653 uint32_t ECSPending; /*!< Specifies the External Clock Synchronization State. 00654 This parameter can be: 00655 - 0 : No external clock synchronization pending 00656 - 1 : Node waits for external clock synchronization to take effect */ 00657 00658 uint32_t PhaseLock; /*!< Specifies the Phase Lock State. 00659 This parameter can be: 00660 - 0 : Phase outside range 00661 - 1 : Phase inside range */ 00662 00663 } FDCAN_TTOperationStatusTypeDef; 00664 00665 /** 00666 * @brief FDCAN Message RAM blocks 00667 */ 00668 typedef struct 00669 { 00670 uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address. 00671 This parameter must be a 32-bit word address */ 00672 00673 uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address. 00674 This parameter must be a 32-bit word address */ 00675 00676 uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address. 00677 This parameter must be a 32-bit word address */ 00678 00679 uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address. 00680 This parameter must be a 32-bit word address */ 00681 00682 uint32_t RxBufferSA; /*!< Specifies the Rx Buffer Start Address. 00683 This parameter must be a 32-bit word address */ 00684 00685 uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address. 00686 This parameter must be a 32-bit word address */ 00687 00688 uint32_t TxBufferSA; /*!< Specifies the Tx Buffers Start Address. 00689 This parameter must be a 32-bit word address */ 00690 00691 uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address. 00692 This parameter must be a 32-bit word address */ 00693 00694 uint32_t TTMemorySA; /*!< Specifies the Trigger Memory Start Address. 00695 This parameter must be a 32-bit word address */ 00696 00697 uint32_t EndAddress; /*!< Specifies the End Address of the allocated RAM. 00698 This parameter must be a 32-bit word address */ 00699 00700 } FDCAN_MsgRamAddressTypeDef; 00701 00702 /** 00703 * @brief FDCAN handle structure definition 00704 */ 00705 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 00706 typedef struct __FDCAN_HandleTypeDef 00707 #else 00708 typedef struct 00709 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 00710 { 00711 FDCAN_GlobalTypeDef *Instance; /*!< Register base address */ 00712 00713 TTCAN_TypeDef *ttcan; /*!< TT register base address */ 00714 00715 FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */ 00716 00717 FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */ 00718 00719 uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index 00720 of latest Tx FIFO/Queue request */ 00721 00722 __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */ 00723 00724 HAL_LockTypeDef Lock; /*!< FDCAN locking object */ 00725 00726 __IO uint32_t ErrorCode; /*!< FDCAN Error code */ 00727 00728 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 00729 void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); /*!< FDCAN Clock Calibration callback */ 00730 void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */ 00731 void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */ 00732 void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */ 00733 void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */ 00734 void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */ 00735 void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */ 00736 void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Rx Buffer New Message callback */ 00737 void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */ 00738 void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */ 00739 void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */ 00740 void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */ 00741 void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */ 00742 void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); /*!< FDCAN T Schedule Synchronization callback */ 00743 void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); /*!< FDCAN TT Time Mark callback */ 00744 void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback */ 00745 void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); /*!< FDCAN TT Global Time callback */ 00746 00747 void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */ 00748 void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */ 00749 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 00750 00751 } FDCAN_HandleTypeDef; 00752 00753 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 00754 /** 00755 * @brief HAL FDCAN common Callback ID enumeration definition 00756 */ 00757 typedef enum 00758 { 00759 HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */ 00760 HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, /*!< FDCAN Rx buffer new message callback ID */ 00761 HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, /*!< FDCAN High priority message callback ID */ 00762 HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID */ 00763 HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, /*!< FDCAN Timeout occurred callback ID */ 00764 HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, /*!< FDCAN Error callback ID */ 00765 00766 HAL_FDCAN_MSPINIT_CB_ID = 0x06U, /*!< FDCAN MspInit callback ID */ 00767 HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U, /*!< FDCAN MspDeInit callback ID */ 00768 00769 } HAL_FDCAN_CallbackIDTypeDef; 00770 00771 /** 00772 * @brief HAL FDCAN Callback pointer definition 00773 */ 00774 typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */ 00775 typedef void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); /*!< pointer to Clock Calibration FDCAN callback function */ 00776 typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */ 00777 typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */ 00778 typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */ 00779 typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */ 00780 typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */ 00781 typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */ 00782 typedef void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); /*!< pointer to TT Schedule Synchronization FDCAN callback function */ 00783 typedef void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); /*!< pointer to TT Time Mark FDCAN callback function */ 00784 typedef void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function */ 00785 typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); /*!< pointer to TT Global Time FDCAN callback function */ 00786 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 00787 00788 /** 00789 * @} 00790 */ 00791 00792 /* Exported constants --------------------------------------------------------*/ 00793 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants 00794 * @{ 00795 */ 00796 00797 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code 00798 * @{ 00799 */ 00800 #define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 00801 #define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 00802 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */ 00803 #define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */ 00804 #define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */ 00805 #define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */ 00806 #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ 00807 #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ 00808 #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ 00809 #define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ 00810 #define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ 00811 #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ 00812 #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ 00813 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ 00814 #define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */ 00815 #define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */ 00816 #define HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE /*!< Global Time Error : Synchronization deviation exceeded limit */ 00817 #define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */ 00818 #define HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle */ 00819 #define HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1 /*!< Scheduling error 1 */ 00820 #define HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2 /*!< Scheduling error 2 */ 00821 #define HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT /*!< No system startup due to missing reference message */ 00822 #define HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT /*!< Missing reference message */ 00823 #define HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW /*!< Application watchdog not served in time */ 00824 #define HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER /*!< Error found in trigger list */ 00825 00826 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 00827 #define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */ 00828 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 00829 /** 00830 * @} 00831 */ 00832 00833 /** @defgroup FDCAN_frame_format FDCAN Frame Format 00834 * @{ 00835 */ 00836 #define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ 00837 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */ 00838 #define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */ 00839 /** 00840 * @} 00841 */ 00842 00843 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode 00844 * @{ 00845 */ 00846 #define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ 00847 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */ 00848 #define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */ 00849 #define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */ 00850 #define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */ 00851 /** 00852 * @} 00853 */ 00854 00855 /** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration 00856 * @{ 00857 */ 00858 #define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */ 00859 #define FDCAN_CLOCK_CALIBRATION_ENABLE ((uint32_t)0x00000001U) /*!< Enable Clock Calibration */ 00860 /** 00861 * @} 00862 */ 00863 00864 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider 00865 * @{ 00866 */ 00867 #define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */ 00868 #define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2 */ 00869 #define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4 */ 00870 #define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6 */ 00871 #define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8 */ 00872 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */ 00873 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */ 00874 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */ 00875 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */ 00876 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */ 00877 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */ 00878 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */ 00879 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */ 00880 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */ 00881 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */ 00882 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */ 00883 /** 00884 * @} 00885 */ 00886 00887 /** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length 00888 * @{ 00889 */ 00890 #define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U) /*!< Calibration field length is 32 bits */ 00891 #define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */ 00892 /** 00893 * @} 00894 */ 00895 00896 /** @defgroup FDCAN_calibration_state FDCAN Calibration State 00897 * @{ 00898 */ 00899 #define FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U) /*!< Clock not calibrated */ 00900 #define FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U) /*!< Clock basic calibrated */ 00901 #define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */ 00902 /** 00903 * @} 00904 */ 00905 00906 /** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter 00907 * @{ 00908 */ 00909 #define FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U) /*!< Time Quanta Counter */ 00910 #define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */ 00911 #define FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter */ 00912 /** 00913 * @} 00914 */ 00915 00916 /** @defgroup FDCAN_data_field_size FDCAN Data Field Size 00917 * @{ 00918 */ 00919 #define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */ 00920 #define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */ 00921 #define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */ 00922 #define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */ 00923 #define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */ 00924 #define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */ 00925 #define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ 00926 #define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */ 00927 /** 00928 * @} 00929 */ 00930 00931 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode 00932 * @{ 00933 */ 00934 #define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */ 00935 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */ 00936 /** 00937 * @} 00938 */ 00939 00940 /** @defgroup FDCAN_id_type FDCAN ID Type 00941 * @{ 00942 */ 00943 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */ 00944 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */ 00945 /** 00946 * @} 00947 */ 00948 00949 /** @defgroup FDCAN_frame_type FDCAN Frame Type 00950 * @{ 00951 */ 00952 #define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ 00953 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */ 00954 /** 00955 * @} 00956 */ 00957 00958 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code 00959 * @{ 00960 */ 00961 #define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ 00962 #define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */ 00963 #define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */ 00964 #define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */ 00965 #define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */ 00966 #define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */ 00967 #define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */ 00968 #define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */ 00969 #define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */ 00970 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */ 00971 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */ 00972 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */ 00973 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */ 00974 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */ 00975 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */ 00976 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */ 00977 /** 00978 * @} 00979 */ 00980 00981 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator 00982 * @{ 00983 */ 00984 #define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */ 00985 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */ 00986 /** 00987 * @} 00988 */ 00989 00990 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching 00991 * @{ 00992 */ 00993 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */ 00994 #define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */ 00995 /** 00996 * @} 00997 */ 00998 00999 /** @defgroup FDCAN_format FDCAN format 01000 * @{ 01001 */ 01002 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */ 01003 #define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */ 01004 /** 01005 * @} 01006 */ 01007 01008 /** @defgroup FDCAN_EFC FDCAN Event FIFO control 01009 * @{ 01010 */ 01011 #define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */ 01012 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */ 01013 /** 01014 * @} 01015 */ 01016 01017 /** @defgroup FDCAN_filter_type FDCAN Filter Type 01018 * @{ 01019 */ 01020 #define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */ 01021 #define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */ 01022 #define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */ 01023 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */ 01024 /** 01025 * @} 01026 */ 01027 01028 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration 01029 * @{ 01030 */ 01031 #define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */ 01032 #define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */ 01033 #define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */ 01034 #define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */ 01035 #define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */ 01036 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */ 01037 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */ 01038 #define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */ 01039 /** 01040 * @} 01041 */ 01042 01043 /** @defgroup FDCAN_Tx_location FDCAN Tx Location 01044 * @{ 01045 */ 01046 #define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */ 01047 #define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */ 01048 #define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */ 01049 #define FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3 */ 01050 #define FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4 */ 01051 #define FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5 */ 01052 #define FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6 */ 01053 #define FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7 */ 01054 #define FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8 */ 01055 #define FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9 */ 01056 #define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */ 01057 #define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */ 01058 #define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */ 01059 #define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */ 01060 #define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */ 01061 #define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */ 01062 #define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */ 01063 #define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */ 01064 #define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */ 01065 #define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */ 01066 #define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */ 01067 #define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */ 01068 #define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */ 01069 #define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */ 01070 #define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */ 01071 #define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */ 01072 #define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */ 01073 #define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */ 01074 #define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */ 01075 #define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */ 01076 #define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */ 01077 #define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */ 01078 /** 01079 * @} 01080 */ 01081 01082 /** @defgroup FDCAN_Rx_location FDCAN Rx Location 01083 * @{ 01084 */ 01085 #define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */ 01086 #define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */ 01087 #define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0 */ 01088 #define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1 */ 01089 #define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2 */ 01090 #define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3 */ 01091 #define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4 */ 01092 #define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5 */ 01093 #define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6 */ 01094 #define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7 */ 01095 #define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8 */ 01096 #define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9 */ 01097 #define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */ 01098 #define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */ 01099 #define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */ 01100 #define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */ 01101 #define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */ 01102 #define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */ 01103 #define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */ 01104 #define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */ 01105 #define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */ 01106 #define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */ 01107 #define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */ 01108 #define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */ 01109 #define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */ 01110 #define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */ 01111 #define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */ 01112 #define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */ 01113 #define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */ 01114 #define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */ 01115 #define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */ 01116 #define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */ 01117 #define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */ 01118 #define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */ 01119 #define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */ 01120 #define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */ 01121 #define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */ 01122 #define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */ 01123 #define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */ 01124 #define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */ 01125 #define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */ 01126 #define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */ 01127 #define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */ 01128 #define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */ 01129 #define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */ 01130 #define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */ 01131 #define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */ 01132 #define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */ 01133 #define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */ 01134 #define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */ 01135 #define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */ 01136 #define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */ 01137 #define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */ 01138 #define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */ 01139 #define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */ 01140 #define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */ 01141 #define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */ 01142 #define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */ 01143 #define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */ 01144 #define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */ 01145 #define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */ 01146 #define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */ 01147 #define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */ 01148 #define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */ 01149 #define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */ 01150 #define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */ 01151 /** 01152 * @} 01153 */ 01154 01155 /** @defgroup FDCAN_event_type FDCAN Event Type 01156 * @{ 01157 */ 01158 #define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */ 01159 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */ 01160 /** 01161 * @} 01162 */ 01163 01164 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage 01165 * @{ 01166 */ 01167 #define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */ 01168 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */ 01169 #define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */ 01170 #define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */ 01171 /** 01172 * @} 01173 */ 01174 01175 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code 01176 * @{ 01177 */ 01178 #define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */ 01179 #define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */ 01180 #define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */ 01181 #define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */ 01182 #define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */ 01183 #define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */ 01184 #define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */ 01185 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */ 01186 /** 01187 * @} 01188 */ 01189 01190 /** @defgroup FDCAN_communication_state FDCAN communication state 01191 * @{ 01192 */ 01193 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */ 01194 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */ 01195 #define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */ 01196 #define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */ 01197 /** 01198 * @} 01199 */ 01200 01201 /** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark 01202 * @{ 01203 */ 01204 #define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */ 01205 #define FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U) /*!< Rx FIFO0 */ 01206 #define FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U) /*!< Rx FIFO1 */ 01207 /** 01208 * @} 01209 */ 01210 01211 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode 01212 * @{ 01213 */ 01214 #define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */ 01215 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */ 01216 /** 01217 * @} 01218 */ 01219 01220 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames 01221 * @{ 01222 */ 01223 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */ 01224 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */ 01225 #define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */ 01226 /** 01227 * @} 01228 */ 01229 01230 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames 01231 * @{ 01232 */ 01233 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */ 01234 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */ 01235 /** 01236 * @} 01237 */ 01238 01239 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line 01240 * @{ 01241 */ 01242 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */ 01243 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */ 01244 /** 01245 * @} 01246 */ 01247 01248 /** @defgroup FDCAN_Timestamp FDCAN timestamp 01249 * @{ 01250 */ 01251 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */ 01252 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */ 01253 /** 01254 * @} 01255 */ 01256 01257 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler 01258 * @{ 01259 */ 01260 #define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ 01261 #define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2 */ 01262 #define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3 */ 01263 #define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4 */ 01264 #define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5 */ 01265 #define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6 */ 01266 #define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7 */ 01267 #define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8 */ 01268 #define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9 */ 01269 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */ 01270 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */ 01271 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */ 01272 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */ 01273 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */ 01274 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */ 01275 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */ 01276 /** 01277 * @} 01278 */ 01279 01280 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation 01281 * @{ 01282 */ 01283 #define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */ 01284 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */ 01285 #define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */ 01286 #define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */ 01287 /** 01288 * @} 01289 */ 01290 01291 /** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload 01292 * @{ 01293 */ 01294 #define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U) /*!< Reference message has no additional payload */ 01295 #define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */ 01296 /** 01297 * @} 01298 */ 01299 01300 /** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor 01301 * @{ 01302 */ 01303 #define FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles */ 01304 #define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle */ 01305 #define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle */ 01306 #define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle */ 01307 #define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */ 01308 #define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */ 01309 #define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */ 01310 /** 01311 * @} 01312 */ 01313 01314 /** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type 01315 * @{ 01316 */ 01317 #define FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation */ 01318 #define FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation */ 01319 #define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window */ 01320 #define FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window */ 01321 #define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window */ 01322 #define FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U) /*!< Start a merged arbitration window */ 01323 #define FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation */ 01324 #define FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation */ 01325 #define FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows */ 01326 #define FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration */ 01327 #define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */ 01328 /** 01329 * @} 01330 */ 01331 01332 /** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal 01333 * @{ 01334 */ 01335 #define FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */ 01336 #define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */ 01337 /** 01338 * @} 01339 */ 01340 01341 /** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external 01342 * @{ 01343 */ 01344 #define FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */ 01345 #define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */ 01346 /** 01347 * @} 01348 */ 01349 01350 /** @defgroup FDCAN_operation_mode FDCAN Operation Mode 01351 * @{ 01352 */ 01353 #define FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */ 01354 #define FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */ 01355 #define FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */ 01356 /** 01357 * @} 01358 */ 01359 01360 /** @defgroup FDCAN_TT_operation FDCAN TT Operation 01361 * @{ 01362 */ 01363 #define FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U) /*!< Strictly time-triggered operation */ 01364 #define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */ 01365 /** 01366 * @} 01367 */ 01368 01369 /** @defgroup FDCAN_TT_time_master FDCAN TT Time Master 01370 * @{ 01371 */ 01372 #define FDCAN_TT_SLAVE ((uint32_t)0x00000000U) /*!< Time slave */ 01373 #define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */ 01374 /** 01375 * @} 01376 */ 01377 01378 /** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization 01379 * @{ 01380 */ 01381 #define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U) /*!< External clock synchronization in Level 0,2 disabled */ 01382 #define FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled */ 01383 /** 01384 * @} 01385 */ 01386 01387 /** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering 01388 * @{ 01389 */ 01390 #define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U) /*!< Global time filtering in Level 0,2 disabled */ 01391 #define FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled */ 01392 /** 01393 * @} 01394 */ 01395 01396 /** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration 01397 * @{ 01398 */ 01399 #define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U) /*!< Automatic clock calibration in Level 0,2 disabled */ 01400 #define FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled */ 01401 /** 01402 * @} 01403 */ 01404 01405 /** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity 01406 * @{ 01407 */ 01408 #define FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U) /*!< Rising edge trigger */ 01409 #define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */ 01410 /** 01411 * @} 01412 */ 01413 01414 /** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number 01415 * @{ 01416 */ 01417 #define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix */ 01418 #define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix */ 01419 #define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix */ 01420 #define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix */ 01421 #define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */ 01422 #define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */ 01423 #define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */ 01424 /** 01425 * @} 01426 */ 01427 01428 /** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync 01429 * @{ 01430 */ 01431 #define FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U) /*!< No sync pulse */ 01432 #define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */ 01433 #define FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix */ 01434 /** 01435 * @} 01436 */ 01437 01438 /** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection 01439 * @{ 01440 */ 01441 #define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger */ 01442 #define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger */ 01443 #define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger */ 01444 #define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */ 01445 /** 01446 * @} 01447 */ 01448 01449 /** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection 01450 * @{ 01451 */ 01452 #define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger */ 01453 #define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger */ 01454 #define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger */ 01455 #define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */ 01456 /** 01457 * @} 01458 */ 01459 01460 /** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source 01461 * @{ 01462 */ 01463 #define FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U) /*!< Stop Watch disabled */ 01464 #define FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV) */ 01465 #define FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV) */ 01466 #define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */ 01467 /** 01468 * @} 01469 */ 01470 01471 /** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity 01472 * @{ 01473 */ 01474 #define FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt */ 01475 #define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */ 01476 /** 01477 * @} 01478 */ 01479 01480 /** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source 01481 * @{ 01482 */ 01483 #define FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated */ 01484 #define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time */ 01485 #define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time */ 01486 #define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */ 01487 /** 01488 * @} 01489 */ 01490 01491 /** @defgroup FDCAN_TT_error_level FDCAN TT Error Level 01492 * @{ 01493 */ 01494 #define FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U) /*!< Severity 0 - No Error */ 01495 #define FDCAN_TT_WARNING ((uint32_t)0x00000001U) /*!< Severity 1 - Warning */ 01496 #define FDCAN_TT_ERROR ((uint32_t)0x00000002U) /*!< Severity 2 - Error */ 01497 #define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */ 01498 /** 01499 * @} 01500 */ 01501 01502 /** @defgroup FDCAN_TT_master_state FDCAN TT Master State 01503 * @{ 01504 */ 01505 #define FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */ 01506 #define FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U) /*!< Operating as Time Slave */ 01507 #define FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master */ 01508 #define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master */ 01509 /** 01510 * @} 01511 */ 01512 01513 /** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State 01514 * @{ 01515 */ 01516 #define FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U) /*!< Out of Synchronization */ 01517 #define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */ 01518 #define FDCAN_TT_IN_GAP ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap */ 01519 #define FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U) /*!< Synchronized to schedule */ 01520 /** 01521 * @} 01522 */ 01523 01524 /** @defgroup Interrupt_Masks Interrupt masks 01525 * @{ 01526 */ 01527 #define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */ 01528 #define CCU_IR_MASK ((uint32_t)0xC0000000U) /*!< CCU interrupts mask */ 01529 /** 01530 * @} 01531 */ 01532 01533 /** @defgroup FDCAN_flags FDCAN Flags 01534 * @{ 01535 */ 01536 #define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */ 01537 #define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */ 01538 #define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */ 01539 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */ 01540 #define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX /*!< At least one received message stored into a Rx Buffer */ 01541 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */ 01542 #define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */ 01543 #define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW /*!< Tx Event FIFO fill level reached watermark */ 01544 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */ 01545 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */ 01546 #define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */ 01547 #define FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W /*!< Rx FIFO 0 fill level reached watermark */ 01548 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */ 01549 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */ 01550 #define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */ 01551 #define FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W /*!< Rx FIFO 1 fill level reached watermark */ 01552 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */ 01553 #define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */ 01554 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */ 01555 #define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */ 01556 #define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */ 01557 #define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */ 01558 #define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */ 01559 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */ 01560 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */ 01561 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */ 01562 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */ 01563 #define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */ 01564 #define FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed */ 01565 #define FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred */ 01566 /** 01567 * @} 01568 */ 01569 01570 /** @defgroup FDCAN_Interrupts FDCAN Interrupts 01571 * @{ 01572 */ 01573 01574 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts 01575 * @{ 01576 */ 01577 #define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */ 01578 #define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */ 01579 #define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */ 01580 /** 01581 * @} 01582 */ 01583 01584 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts 01585 * @{ 01586 */ 01587 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */ 01588 #define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE /*!< At least one received message stored into a Rx Buffer */ 01589 /** 01590 * @} 01591 */ 01592 01593 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts 01594 * @{ 01595 */ 01596 #define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */ 01597 #define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */ 01598 /** 01599 * @} 01600 */ 01601 01602 /** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts 01603 * @{ 01604 */ 01605 #define FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed */ 01606 #define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */ 01607 /** 01608 * @} 01609 */ 01610 01611 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts 01612 * @{ 01613 */ 01614 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */ 01615 #define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */ 01616 #define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */ 01617 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */ 01618 /** 01619 * @} 01620 */ 01621 01622 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts 01623 * @{ 01624 */ 01625 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */ 01626 #define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */ 01627 #define FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */ 01628 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */ 01629 /** 01630 * @} 01631 */ 01632 01633 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts 01634 * @{ 01635 */ 01636 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */ 01637 #define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */ 01638 #define FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */ 01639 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */ 01640 /** 01641 * @} 01642 */ 01643 01644 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts 01645 * @{ 01646 */ 01647 #define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */ 01648 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */ 01649 #define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */ 01650 #define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */ 01651 #define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */ 01652 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */ 01653 /** 01654 * @} 01655 */ 01656 01657 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts 01658 * @{ 01659 */ 01660 #define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */ 01661 #define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */ 01662 #define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */ 01663 /** 01664 * @} 01665 */ 01666 01667 /** 01668 * @} 01669 */ 01670 01671 /** @defgroup FDCAN_TTflags FDCAN TT Flags 01672 * @{ 01673 */ 01674 #define FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC /*!< Start of Basic Cycle */ 01675 #define FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC /*!< Start of Matrix Cycle */ 01676 #define FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM /*!< Change of Synchronization Mode */ 01677 #define FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG /*!< Start of Gap */ 01678 #define FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt */ 01679 #define FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */ 01680 #define FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE /*!< Stop Watch Event */ 01681 #define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW /*!< Global Time Wrap */ 01682 #define FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD /*!< Global Time Discontinuity */ 01683 #define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE /*!< Global Time Error */ 01684 #define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow */ 01685 #define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow */ 01686 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1 /*!< Scheduling Error 1 */ 01687 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2 /*!< Scheduling Error 2 */ 01688 #define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC /*!< Error Level Changed */ 01689 #define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT /*!< Initialization Watch Trigger */ 01690 #define FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT /*!< Watch Trigger */ 01691 #define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW /*!< Application Watchdog */ 01692 #define FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER /*!< Configuration Error */ 01693 /** 01694 * @} 01695 */ 01696 01697 /** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts 01698 * @{ 01699 */ 01700 01701 /** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts 01702 * @{ 01703 */ 01704 #define FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE /*!< Start of Basic Cycle */ 01705 #define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle */ 01706 #define FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */ 01707 #define FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE /*!< Start of Gap */ 01708 /** 01709 * @} 01710 */ 01711 01712 /** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts 01713 * @{ 01714 */ 01715 #define FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt */ 01716 #define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */ 01717 /** 01718 * @} 01719 */ 01720 01721 /** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt 01722 * @{ 01723 */ 01724 #define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */ 01725 /** 01726 * @} 01727 */ 01728 01729 /** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts 01730 * @{ 01731 */ 01732 #define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE /*!< Global Time Wrap */ 01733 #define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE /*!< Global Time Discontinuity */ 01734 /** 01735 * @} 01736 */ 01737 01738 /** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts 01739 * @{ 01740 */ 01741 #define FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE /*!< Global Time Error */ 01742 #define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow */ 01743 #define FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE /*!< Tx Count Overflow */ 01744 #define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1 */ 01745 #define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2 */ 01746 #define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */ 01747 /** 01748 * @} 01749 */ 01750 01751 /** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts 01752 * @{ 01753 */ 01754 #define FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */ 01755 #define FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE /*!< Watch Trigger */ 01756 #define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE /*!< Application Watchdog */ 01757 #define FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE /*!< Configuration Error */ 01758 /** 01759 * @} 01760 */ 01761 01762 /** 01763 * @} 01764 */ 01765 01766 /** 01767 * @} 01768 */ 01769 01770 /* Exported macro ------------------------------------------------------------*/ 01771 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros 01772 * @{ 01773 */ 01774 01775 /** @brief Reset FDCAN handle state. 01776 * @param __HANDLE__ FDCAN handle. 01777 * @retval None 01778 */ 01779 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 01780 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ 01781 (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ 01782 (__HANDLE__)->MspInitCallback = NULL; \ 01783 (__HANDLE__)->MspDeInitCallback = NULL; \ 01784 } while(0) 01785 #else 01786 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) 01787 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 01788 01789 /** 01790 * @brief Enable the specified FDCAN interrupts. 01791 * @param __HANDLE__ FDCAN handle. 01792 * @param __INTERRUPT__ FDCAN interrupt. 01793 * This parameter can be any combination of @arg FDCAN_Interrupts 01794 * @retval None 01795 */ 01796 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 01797 do{ \ 01798 (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \ 01799 FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ 01800 }while(0) 01801 01802 01803 /** 01804 * @brief Disable the specified FDCAN interrupts. 01805 * @param __HANDLE__ FDCAN handle. 01806 * @param __INTERRUPT__ FDCAN interrupt. 01807 * This parameter can be any combination of @arg FDCAN_Interrupts 01808 * @retval None 01809 */ 01810 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 01811 do{ \ 01812 ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \ 01813 FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ 01814 }while(0) 01815 01816 /** 01817 * @brief Check whether the specified FDCAN interrupt is set or not. 01818 * @param __HANDLE__ FDCAN handle. 01819 * @param __INTERRUPT__ FDCAN interrupt. 01820 * This parameter can be one of @arg FDCAN_Interrupts 01821 * @retval ITStatus 01822 */ 01823 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__))) 01824 01825 /** 01826 * @brief Clear the specified FDCAN interrupts. 01827 * @param __HANDLE__ FDCAN handle. 01828 * @param __INTERRUPT__ specifies the interrupts to clear. 01829 * This parameter can be any combination of @arg FDCAN_Interrupts 01830 * @retval None 01831 */ 01832 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \ 01833 do{ \ 01834 ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \ 01835 FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ 01836 }while(0) 01837 01838 /** 01839 * @brief Check whether the specified FDCAN flag is set or not. 01840 * @param __HANDLE__ FDCAN handle. 01841 * @param __FLAG__ FDCAN flag. 01842 * This parameter can be one of @arg FDCAN_flags 01843 * @retval FlagStatus 01844 */ 01845 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__))) 01846 01847 /** 01848 * @brief Clear the specified FDCAN flags. 01849 * @param __HANDLE__ FDCAN handle. 01850 * @param __FLAG__ specifies the flags to clear. 01851 * This parameter can be any combination of @arg FDCAN_flags 01852 * @retval None 01853 */ 01854 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 01855 do{ \ 01856 ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \ 01857 FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30); \ 01858 }while(0) 01859 01860 /** @brief Check if the specified FDCAN interrupt source is enabled or disabled. 01861 * @param __HANDLE__ FDCAN handle. 01862 * @param __INTERRUPT__ specifies the FDCAN interrupt source to check. 01863 * This parameter can be a value of @arg FDCAN_Interrupts 01864 * @retval ITStatus 01865 */ 01866 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__))) 01867 01868 /** 01869 * @brief Enable the specified FDCAN TT interrupts. 01870 * @param __HANDLE__ FDCAN handle. 01871 * @param __INTERRUPT__ FDCAN TT interrupt. 01872 * This parameter can be any combination of @arg FDCAN_TTInterrupts 01873 * @retval None 01874 */ 01875 #define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__)) 01876 01877 /** 01878 * @brief Disable the specified FDCAN TT interrupts. 01879 * @param __HANDLE__ FDCAN handle. 01880 * @param __INTERRUPT__ FDCAN TT interrupt. 01881 * This parameter can be any combination of @arg FDCAN_TTInterrupts 01882 * @retval None 01883 */ 01884 #define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__)) 01885 01886 /** 01887 * @brief Check whether the specified FDCAN TT interrupt is set or not. 01888 * @param __HANDLE__ FDCAN handle. 01889 * @param __INTERRUPT__ FDCAN TT interrupt. 01890 * This parameter can be one of @arg FDCAN_TTInterrupts 01891 * @retval ITStatus 01892 */ 01893 #define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__)) 01894 01895 /** 01896 * @brief Clear the specified FDCAN TT interrupts. 01897 * @param __HANDLE__ FDCAN handle. 01898 * @param __INTERRUPT__ specifies the TT interrupts to clear. 01899 * This parameter can be any combination of @arg FDCAN_TTInterrupts 01900 * @retval None 01901 */ 01902 #define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__)) 01903 01904 /** 01905 * @brief Check whether the specified FDCAN TT flag is set or not. 01906 * @param __HANDLE__ FDCAN handle. 01907 * @param __FLAG__ FDCAN TT flag. 01908 * This parameter can be one of @arg FDCAN_TTflags 01909 * @retval FlagStatus 01910 */ 01911 #define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__)) 01912 01913 /** 01914 * @brief Clear the specified FDCAN TT flags. 01915 * @param __HANDLE__ FDCAN handle. 01916 * @param __FLAG__ specifies the TT flags to clear. 01917 * This parameter can be any combination of @arg FDCAN_TTflags 01918 * @retval None 01919 */ 01920 #define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__)) 01921 01922 /** @brief Check if the specified FDCAN TT interrupt source is enabled or disabled. 01923 * @param __HANDLE__ FDCAN handle. 01924 * @param __INTERRUPT__ specifies the FDCAN TT interrupt source to check. 01925 * This parameter can be a value of @arg FDCAN_TTInterrupts 01926 * @retval ITStatus 01927 */ 01928 #define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__)) 01929 01930 /** 01931 * @} 01932 */ 01933 01934 /* Exported functions --------------------------------------------------------*/ 01935 /** @addtogroup FDCAN_Exported_Functions 01936 * @{ 01937 */ 01938 01939 /** @addtogroup FDCAN_Exported_Functions_Group1 01940 * @{ 01941 */ 01942 /* Initialization and de-initialization functions *****************************/ 01943 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan); 01944 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan); 01945 void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan); 01946 void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan); 01947 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 01948 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 01949 01950 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 01951 /* Callbacks Register/UnRegister functions ***********************************/ 01952 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback); 01953 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID); 01954 HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback); 01955 HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan); 01956 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback); 01957 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan); 01958 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback); 01959 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan); 01960 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback); 01961 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan); 01962 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback); 01963 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan); 01964 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback); 01965 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan); 01966 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback); 01967 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan); 01968 HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback); 01969 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan); 01970 HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback); 01971 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan); 01972 HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback); 01973 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan); 01974 HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback); 01975 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan); 01976 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 01977 /** 01978 * @} 01979 */ 01980 01981 /** @addtogroup FDCAN_Exported_Functions_Group2 01982 * @{ 01983 */ 01984 /* Configuration functions ****************************************************/ 01985 HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig); 01986 uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan); 01987 HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan); 01988 uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter); 01989 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig); 01990 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt); 01991 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask); 01992 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode); 01993 HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark); 01994 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue); 01995 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); 01996 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); 01997 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 01998 uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 01999 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 02000 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod); 02001 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 02002 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 02003 uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 02004 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 02005 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter); 02006 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 02007 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 02008 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan); 02009 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan); 02010 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 02011 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 02012 /** 02013 * @} 02014 */ 02015 02016 /** @addtogroup FDCAN_Exported_Functions_Group3 02017 * @{ 02018 */ 02019 /* Control functions **********************************************************/ 02020 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); 02021 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); 02022 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData); 02023 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex); 02024 HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); 02025 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan); 02026 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); 02027 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); 02028 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); 02029 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus); 02030 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus); 02031 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters); 02032 uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex); 02033 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); 02034 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); 02035 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan); 02036 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 02037 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 02038 /** 02039 * @} 02040 */ 02041 02042 /** @addtogroup FDCAN_Exported_Functions_Group4 02043 * @{ 02044 */ 02045 /* TT Configuration and control functions**************************************/ 02046 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams); 02047 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload); 02048 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig); 02049 HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset); 02050 HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator); 02051 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity); 02052 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle); 02053 HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 02054 HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 02055 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 02056 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 02057 HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan); 02058 HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan); 02059 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan); 02060 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan); 02061 HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan); 02062 HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan); 02063 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase); 02064 HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); 02065 HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); 02066 HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus); 02067 /** 02068 * @} 02069 */ 02070 02071 /** @addtogroup FDCAN_Exported_Functions_Group5 02072 * @{ 02073 */ 02074 /* Interrupts management ******************************************************/ 02075 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine); 02076 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine); 02077 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes); 02078 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs); 02079 HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs); 02080 HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs); 02081 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); 02082 /** 02083 * @} 02084 */ 02085 02086 /** @addtogroup FDCAN_Exported_Functions_Group6 02087 * @{ 02088 */ 02089 /* Callback functions *********************************************************/ 02090 void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); 02091 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); 02092 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); 02093 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); 02094 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan); 02095 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 02096 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 02097 void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan); 02098 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan); 02099 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan); 02100 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan); 02101 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); 02102 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); 02103 void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); 02104 void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); 02105 void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); 02106 void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); 02107 /** 02108 * @} 02109 */ 02110 02111 /** @addtogroup FDCAN_Exported_Functions_Group7 02112 * @{ 02113 */ 02114 /* Peripheral State functions *************************************************/ 02115 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan); 02116 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); 02117 /** 02118 * @} 02119 */ 02120 02121 /** 02122 * @} 02123 */ 02124 02125 /* Private types -------------------------------------------------------------*/ 02126 /** @defgroup FDCAN_Private_Types FDCAN Private Types 02127 * @{ 02128 */ 02129 02130 /** 02131 * @} 02132 */ 02133 02134 /* Private variables ---------------------------------------------------------*/ 02135 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables 02136 * @{ 02137 */ 02138 02139 /** 02140 * @} 02141 */ 02142 02143 /* Private constants ---------------------------------------------------------*/ 02144 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants 02145 * @{ 02146 */ 02147 02148 /** 02149 * @} 02150 */ 02151 02152 /* Private macros ------------------------------------------------------------*/ 02153 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros 02154 * @{ 02155 */ 02156 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \ 02157 ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \ 02158 ((FORMAT) == FDCAN_FRAME_FD_BRS )) 02159 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \ 02160 ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \ 02161 ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \ 02162 ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \ 02163 ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK )) 02164 02165 #define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \ 02166 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE )) 02167 02168 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \ 02169 ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \ 02170 ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \ 02171 ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \ 02172 ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \ 02173 ((CKDIV) == FDCAN_CLOCK_DIV10) || \ 02174 ((CKDIV) == FDCAN_CLOCK_DIV12) || \ 02175 ((CKDIV) == FDCAN_CLOCK_DIV14) || \ 02176 ((CKDIV) == FDCAN_CLOCK_DIV16) || \ 02177 ((CKDIV) == FDCAN_CLOCK_DIV18) || \ 02178 ((CKDIV) == FDCAN_CLOCK_DIV20) || \ 02179 ((CKDIV) == FDCAN_CLOCK_DIV22) || \ 02180 ((CKDIV) == FDCAN_CLOCK_DIV24) || \ 02181 ((CKDIV) == FDCAN_CLOCK_DIV26) || \ 02182 ((CKDIV) == FDCAN_CLOCK_DIV28) || \ 02183 ((CKDIV) == FDCAN_CLOCK_DIV30)) 02184 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U)) 02185 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U)) 02186 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U)) 02187 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U)) 02188 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U)) 02189 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) 02190 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) 02191 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) 02192 #define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX)) 02193 #define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN)) 02194 #define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \ 02195 ((SIZE) == FDCAN_DATA_BYTES_12) || \ 02196 ((SIZE) == FDCAN_DATA_BYTES_16) || \ 02197 ((SIZE) == FDCAN_DATA_BYTES_20) || \ 02198 ((SIZE) == FDCAN_DATA_BYTES_24) || \ 02199 ((SIZE) == FDCAN_DATA_BYTES_32) || \ 02200 ((SIZE) == FDCAN_DATA_BYTES_48) || \ 02201 ((SIZE) == FDCAN_DATA_BYTES_64)) 02202 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \ 02203 ((MODE) == FDCAN_TX_QUEUE_OPERATION)) 02204 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ 02205 ((ID_TYPE) == FDCAN_EXTENDED_ID)) 02206 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \ 02207 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \ 02208 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \ 02209 ((CONFIG) == FDCAN_FILTER_REJECT ) || \ 02210 ((CONFIG) == FDCAN_FILTER_HP ) || \ 02211 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \ 02212 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \ 02213 ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER )) 02214 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \ 02215 ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \ 02216 ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \ 02217 ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \ 02218 ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \ 02219 ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \ 02220 ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \ 02221 ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \ 02222 ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \ 02223 ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \ 02224 ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \ 02225 ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \ 02226 ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \ 02227 ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \ 02228 ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \ 02229 ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31)) 02230 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \ 02231 ((FIFO) == FDCAN_RX_FIFO1)) 02232 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \ 02233 ((MODE) == FDCAN_RX_FIFO_OVERWRITE)) 02234 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ 02235 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 02236 ((TYPE) == FDCAN_FILTER_MASK )) 02237 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ 02238 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 02239 ((TYPE) == FDCAN_FILTER_MASK ) || \ 02240 ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM)) 02241 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ 02242 ((TYPE) == FDCAN_REMOTE_FRAME)) 02243 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \ 02244 ((DLC) == FDCAN_DLC_BYTES_1 ) || \ 02245 ((DLC) == FDCAN_DLC_BYTES_2 ) || \ 02246 ((DLC) == FDCAN_DLC_BYTES_3 ) || \ 02247 ((DLC) == FDCAN_DLC_BYTES_4 ) || \ 02248 ((DLC) == FDCAN_DLC_BYTES_5 ) || \ 02249 ((DLC) == FDCAN_DLC_BYTES_6 ) || \ 02250 ((DLC) == FDCAN_DLC_BYTES_7 ) || \ 02251 ((DLC) == FDCAN_DLC_BYTES_8 ) || \ 02252 ((DLC) == FDCAN_DLC_BYTES_12) || \ 02253 ((DLC) == FDCAN_DLC_BYTES_16) || \ 02254 ((DLC) == FDCAN_DLC_BYTES_20) || \ 02255 ((DLC) == FDCAN_DLC_BYTES_24) || \ 02256 ((DLC) == FDCAN_DLC_BYTES_32) || \ 02257 ((DLC) == FDCAN_DLC_BYTES_48) || \ 02258 ((DLC) == FDCAN_DLC_BYTES_64)) 02259 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \ 02260 ((ESI) == FDCAN_ESI_PASSIVE)) 02261 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \ 02262 ((BRS) == FDCAN_BRS_ON )) 02263 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \ 02264 ((FDF) == FDCAN_FD_CAN )) 02265 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \ 02266 ((EFC) == FDCAN_STORE_TX_EVENTS)) 02267 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U) 02268 #define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U) 02269 #define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \ 02270 ((FIFO) == FDCAN_CFG_RX_FIFO0 ) || \ 02271 ((FIFO) == FDCAN_CFG_RX_FIFO1 )) 02272 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \ 02273 ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \ 02274 ((DESTINATION) == FDCAN_REJECT )) 02275 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \ 02276 ((DESTINATION) == FDCAN_REJECT_REMOTE)) 02277 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \ 02278 ((IT_LINE) == FDCAN_INTERRUPT_LINE1)) 02279 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \ 02280 ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL)) 02281 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \ 02282 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \ 02283 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \ 02284 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \ 02285 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \ 02286 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \ 02287 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \ 02288 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \ 02289 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \ 02290 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \ 02291 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \ 02292 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \ 02293 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \ 02294 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \ 02295 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \ 02296 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16)) 02297 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \ 02298 ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ 02299 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ 02300 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) 02301 #define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \ 02302 ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64)) 02303 #define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \ 02304 ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \ 02305 ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER )) 02306 #define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \ 02307 ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD)) 02308 #define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE ) || \ 02309 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \ 02310 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \ 02311 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \ 02312 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \ 02313 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \ 02314 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE)) 02315 #define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER ) || \ 02316 ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP ) || \ 02317 ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE ) || \ 02318 ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \ 02319 ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \ 02320 ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED ) || \ 02321 ((TYPE) == FDCAN_TT_WATCH_TRIGGER ) || \ 02322 ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP ) || \ 02323 ((TYPE) == FDCAN_TT_RX_TRIGGER ) || \ 02324 ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER ) || \ 02325 ((TYPE) == FDCAN_TT_END_OF_LIST )) 02326 #define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \ 02327 ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT)) 02328 #define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \ 02329 ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT)) 02330 #define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \ 02331 ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \ 02332 ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 )) 02333 #define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION ) || \ 02334 ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION)) 02335 #define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE ) || \ 02336 ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER)) 02337 #define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \ 02338 ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE )) 02339 #define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \ 02340 ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE )) 02341 #define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \ 02342 ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE )) 02343 #define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \ 02344 ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING)) 02345 #define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \ 02346 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \ 02347 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \ 02348 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \ 02349 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \ 02350 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \ 02351 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64)) 02352 #define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE ) || \ 02353 ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \ 02354 ((SYNC) == FDCAN_TT_SYNC_MATRIX_START )) 02355 #define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U)) 02356 #define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU)) 02357 #define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU)) 02358 #define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC))) 02359 #define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC))) 02360 #define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \ 02361 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \ 02362 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \ 02363 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3)) 02364 #define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \ 02365 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \ 02366 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \ 02367 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3)) 02368 #define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U)) 02369 #define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED ) || \ 02370 ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \ 02371 ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \ 02372 ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME)) 02373 #define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \ 02374 ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING)) 02375 #define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \ 02376 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \ 02377 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \ 02378 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME)) 02379 /** 02380 * @} 02381 */ 02382 02383 /* Private functions prototypes ----------------------------------------------*/ 02384 /** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes 02385 * @{ 02386 */ 02387 02388 /** 02389 * @} 02390 */ 02391 02392 /* Private functions ---------------------------------------------------------*/ 02393 /** @defgroup FDCAN_Private_Functions FDCAN Private Functions 02394 * @{ 02395 */ 02396 02397 /** 02398 * @} 02399 */ 02400 /** 02401 * @} 02402 */ 02403 02404 /** 02405 * @} 02406 */ 02407 #endif /* FDCAN1 */ 02408 02409 #ifdef __cplusplus 02410 } 02411 #endif 02412 02413 #endif /* STM32H7xx_HAL_FDCAN_H */ 02414 02415
1.7.6.1