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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_pwr_ex.h 00004 * @author MCD Application Team 00005 * @brief Header file of PWR HAL Extension module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_PWR_EX_H 00021 #define STM32H7xx_HAL_PWR_EX_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif /* __cplusplus */ 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx_hal_def.h" 00029 00030 /** @addtogroup STM32H7xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup PWREx 00035 * @{ 00036 */ 00037 00038 /* Exported types ------------------------------------------------------------*/ 00039 /** @defgroup PWREx_Exported_Types PWREx Exported Types 00040 * @{ 00041 */ 00042 /** 00043 * @brief PWREx AVD configuration structure definition 00044 */ 00045 typedef struct 00046 { 00047 uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This 00048 parameter can be a value of @ref 00049 PWREx_AVD_detection_level 00050 */ 00051 00052 uint32_t Mode; /*!< Mode : Specifies the EXTI operating mode for the AVD 00053 event. This parameter can be a value of @ref 00054 PWREx_AVD_Mode. 00055 */ 00056 }PWREx_AVDTypeDef; 00057 00058 /** 00059 * @brief PWREx Wakeup pin configuration structure definition 00060 */ 00061 typedef struct 00062 { 00063 uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled. 00064 This parameter can be a value of @ref 00065 PWREx_WakeUp_Pins 00066 */ 00067 00068 uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity. 00069 This parameter can be a value of @ref 00070 PWREx_PIN_Polarity 00071 */ 00072 00073 uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull. This 00074 parameter can be a value of @ref 00075 PWREx_PIN_Pull 00076 */ 00077 }PWREx_WakeupPinTypeDef; 00078 00079 #if defined (PWR_CSR1_MMCVDO) 00080 /** 00081 * @brief PWR VDDMMC voltage level enum definition 00082 */ 00083 typedef enum 00084 { 00085 PWR_MMC_VOLTAGE_BELOW_1V2, /*!< VDDMMC is below 1V2 */ 00086 PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */ 00087 } PWREx_MMC_VoltageLevel; 00088 #endif /* defined (PWR_CSR1_MMCVDO) */ 00089 00090 /** 00091 * @} 00092 */ 00093 00094 /* Exported constants --------------------------------------------------------*/ 00095 00096 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants 00097 * @{ 00098 */ 00099 /** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins 00100 * @{ 00101 */ 00102 /* High level and No pull (default configuration) */ 00103 #define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 00104 #if defined (PWR_WKUPEPR_WKUPEN5) 00105 #define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 00106 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */ 00107 #define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 00108 #if defined (PWR_WKUPEPR_WKUPEN3) 00109 #define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 00110 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 00111 #define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 00112 #define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 00113 00114 /* High level and No pull */ 00115 #define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6 00116 #if defined (PWR_WKUPEPR_WKUPEN5) 00117 #define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5 00118 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */ 00119 #define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 00120 #if defined (PWR_WKUPEPR_WKUPEN3) 00121 #define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 00122 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 00123 #define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 00124 #define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 00125 00126 /* Low level and No pull */ 00127 #define PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6) 00128 #if defined (PWR_WKUPEPR_WKUPP5) 00129 #define PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5) 00130 #endif /* defined (PWR_WKUPEPR_WKUPP5) */ 00131 #define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) 00132 #if defined (PWR_WKUPEPR_WKUPP3) 00133 #define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) 00134 #endif /* defined (PWR_WKUPEPR_WKUPP3) */ 00135 #define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) 00136 #define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) 00137 /** 00138 * @} 00139 */ 00140 00141 /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration 00142 * @{ 00143 */ 00144 #define PWR_PIN_POLARITY_HIGH (0x00000000U) 00145 #define PWR_PIN_POLARITY_LOW (0x00000001U) 00146 /** 00147 * @} 00148 */ 00149 00150 /** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration 00151 * @{ 00152 */ 00153 #define PWR_PIN_NO_PULL (0x00000000U) 00154 #define PWR_PIN_PULL_UP (0x00000001U) 00155 #define PWR_PIN_PULL_DOWN (0x00000002U) 00156 /** 00157 * @} 00158 */ 00159 00160 /** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags. 00161 * @{ 00162 */ 00163 #define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ 00164 #define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ 00165 #if defined (PWR_WKUPFR_WKUPF3) 00166 #define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */ 00167 #endif /* defined (PWR_WKUPFR_WKUPF3) */ 00168 #define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */ 00169 #if defined (PWR_WKUPFR_WKUPF5) 00170 #define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */ 00171 #endif /* defined (PWR_WKUPFR_WKUPF5) */ 00172 #define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */ 00173 #if defined (PWR_WKUPFR_WKUPF3) 00174 #define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ 00175 PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\ 00176 PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6) 00177 #else 00178 #define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ 00179 PWR_WKUPFR_WKUPF4 | PWR_WKUPFR_WKUPF6) 00180 #endif /* defined (PWR_WKUPFR_WKUPF3) */ 00181 /** 00182 * @} 00183 */ 00184 00185 #if defined (DUAL_CORE) 00186 /** @defgroup PWREx_Core_Select PWREx Core definition 00187 * @{ 00188 */ 00189 #define PWR_CORE_CPU1 (0x00000000U) 00190 #define PWR_CORE_CPU2 (0x00000001U) 00191 /** 00192 * @} 00193 */ 00194 #endif /* defined (DUAL_CORE) */ 00195 00196 /** @defgroup PWREx_Domains PWREx Domains definition 00197 * @{ 00198 */ 00199 #define PWR_D1_DOMAIN (0x00000000U) 00200 #if defined (PWR_CPUCR_PDDS_D2) 00201 #define PWR_D2_DOMAIN (0x00000001U) 00202 #endif /* defined (PWR_CPUCR_PDDS_D2) */ 00203 #define PWR_D3_DOMAIN (0x00000002U) 00204 /** 00205 * @} 00206 */ 00207 00208 /** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition 00209 * @{ 00210 */ 00211 #if defined (DUAL_CORE) 00212 #define PWR_D1_DOMAIN_FLAGS (0x00000000U) 00213 #define PWR_D2_DOMAIN_FLAGS (0x00000001U) 00214 #define PWR_ALL_DOMAIN_FLAGS (0x00000002U) 00215 #else 00216 #define PWR_CPU_FLAGS (0x00000000U) 00217 #endif /* defined (DUAL_CORE) */ 00218 /** 00219 * @} 00220 */ 00221 00222 /** @defgroup PWREx_D3_State PWREx D3 Domain State 00223 * @{ 00224 */ 00225 #define PWR_D3_DOMAIN_STOP (0x00000000U) 00226 #define PWR_D3_DOMAIN_RUN (0x00000800U) 00227 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup PWREx_Supply_configuration PWREx Supply configuration 00233 * @{ 00234 */ 00235 #define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ 00236 #if defined (SMPS) 00237 #define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS only */ 00238 #define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ 00239 #define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ 00240 #define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ 00241 #define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ 00242 #define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ 00243 #define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ 00244 #endif /* defined (SMPS) */ 00245 #define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */ 00246 00247 #if defined (SMPS) 00248 #define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \ 00249 PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) 00250 #else 00251 #define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) 00252 #endif /* defined (SMPS) */ 00253 /** 00254 * @} 00255 */ 00256 00257 00258 /** @defgroup PWREx_AVD_detection_level PWREx AVD detection level 00259 * @{ 00260 */ 00261 #define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0 00262 selection : 1V7 */ 00263 #define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1 00264 selection : 2V1 */ 00265 #define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2 00266 selection : 2V5 */ 00267 #define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3 00268 selection : 2V8 */ 00269 /** 00270 * @} 00271 */ 00272 00273 /** @defgroup PWREx_AVD_Mode PWREx AVD Mode 00274 * @{ 00275 */ 00276 #define PWR_AVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ 00277 #define PWR_AVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ 00278 #define PWR_AVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ 00279 #define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 00280 #define PWR_AVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ 00281 #define PWR_AVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ 00282 #define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ 00283 /** 00284 * @} 00285 */ 00286 00287 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale 00288 * @{ 00289 */ 00290 #define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0) 00291 #define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1) 00292 #define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) 00293 /** 00294 * @} 00295 */ 00296 00297 /** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection 00298 * @{ 00299 */ 00300 #define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */ 00301 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 00302 /** 00303 * @} 00304 */ 00305 00306 /** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds 00307 * @{ 00308 */ 00309 #define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) 00310 #define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL 00311 #define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH 00312 /** 00313 * @} 00314 */ 00315 00316 /** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds 00317 * @{ 00318 */ 00319 #define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) 00320 #define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL 00321 #define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH 00322 /** 00323 * @} 00324 */ 00325 /** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16 00326 * @{ 00327 */ 00328 #define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16 00329 Connected to the AVD EXTI Line */ 00330 /** 00331 * @} 00332 */ 00333 00334 #if defined (PWR_CR1_SRDRAMSO) 00335 /** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection 00336 * @{ 00337 */ 00338 #define PWR_SRD_AHB_MEMORY_BLOCK PWR_CR1_SRDRAMSO /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode */ 00339 #define PWR_USB_FDCAN_MEMORY_BLOCK PWR_CR1_HSITFSO /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */ 00340 #define PWR_GFXMMU_JPEG_MEMORY_BLOCK PWR_CR1_GFXSO /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode */ 00341 #define PWR_TCM_ECM_MEMORY_BLOCK PWR_CR1_ITCMSO /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode */ 00342 #define PWR_RAM1_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM1SO /*!< AHB RAM1 shut-off in DStop/DStop2 mode */ 00343 #define PWR_RAM2_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM2SO /*!< AHB RAM2 shut-off in DStop/DStop2 mode */ 00344 #define PWR_RAM1_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM1SO /*!< AXI RAM1 shut-off in DStop/DStop2 mode */ 00345 #define PWR_RAM2_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM2SO /*!< AXI RAM2 shut-off in DStop/DStop2 mode */ 00346 #define PWR_RAM3_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM3SO /*!< AXI RAM3 shut-off in DStop/DStop2 mode */ 00347 #define PWR_MEMORY_BLOCK_KEEP_ON 0U /*!< Memory content is kept in DStop or DStop2 mode */ 00348 #define PWR_MEMORY_BLOCK_SHUT_OFF 1U /*!< Memory content is lost in DStop or DStop2 mode */ 00349 /** 00350 * @} 00351 */ 00352 #endif /* defined (PWR_CR1_SRDRAMSO) */ 00353 /** 00354 * @} 00355 */ 00356 00357 /* Exported macro ------------------------------------------------------------*/ 00358 00359 /** @defgroup PWREx_Exported_Macro PWREx Exported Macro 00360 * @{ 00361 */ 00362 00363 /** 00364 * @brief Enable the AVD EXTI Line 16. 00365 * @retval None. 00366 */ 00367 #define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) 00368 00369 #if defined (DUAL_CORE) 00370 /** 00371 * @brief Enable the AVD EXTI D2 Line 16. 00372 * @retval None. 00373 */ 00374 #define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) 00375 #endif /* defined (DUAL_CORE) */ 00376 00377 /** 00378 * @brief Disable the AVD EXTI Line 16 00379 * @retval None. 00380 */ 00381 #define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) 00382 00383 #if defined (DUAL_CORE) 00384 /** 00385 * @brief Disable the AVD EXTI D2 Line 16. 00386 * @retval None. 00387 */ 00388 #define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) 00389 #endif /* defined (DUAL_CORE) */ 00390 00391 /** 00392 * @brief Enable event on AVD EXTI Line 16. 00393 * @retval None. 00394 */ 00395 #define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) 00396 00397 #if defined (DUAL_CORE) 00398 /** 00399 * @brief Enable event on AVD EXTI D2 Line 16. 00400 * @retval None. 00401 */ 00402 #define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) 00403 #endif /* defined (DUAL_CORE) */ 00404 00405 /** 00406 * @brief Disable event on AVD EXTI Line 16. 00407 * @retval None. 00408 */ 00409 #define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) 00410 00411 #if defined (DUAL_CORE) 00412 /** 00413 * @brief Disable event on AVD EXTI D2 Line 16. 00414 * @retval None. 00415 */ 00416 #define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) 00417 #endif /* defined (DUAL_CORE) */ 00418 00419 /** 00420 * @brief Enable the AVD Extended Interrupt Rising Trigger. 00421 * @retval None. 00422 */ 00423 #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) 00424 00425 /** 00426 * @brief Disable the AVD Extended Interrupt Rising Trigger. 00427 * @retval None. 00428 */ 00429 #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) 00430 00431 /** 00432 * @brief Enable the AVD Extended Interrupt Falling Trigger. 00433 * @retval None. 00434 */ 00435 #define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) 00436 00437 /** 00438 * @brief Disable the AVD Extended Interrupt Falling Trigger. 00439 * @retval None. 00440 */ 00441 #define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) 00442 00443 /** 00444 * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger. 00445 * @retval None. 00446 */ 00447 #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ 00448 do { \ 00449 __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \ 00450 __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \ 00451 } while(0); 00452 00453 /** 00454 * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger. 00455 * @retval None. 00456 */ 00457 #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ 00458 do { \ 00459 __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \ 00460 __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \ 00461 } while(0); 00462 00463 /** 00464 * @brief Check whether the specified AVD EXTI interrupt flag is set or not. 00465 * @retval EXTI AVD Line Status. 00466 */ 00467 #define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) 00468 00469 #if defined (DUAL_CORE) 00470 /** 00471 * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not. 00472 * @retval EXTI D2 AVD Line Status. 00473 */ 00474 #define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) 00475 #endif /* defined (DUAL_CORE) */ 00476 00477 /** 00478 * @brief Clear the AVD EXTI flag. 00479 * @retval None. 00480 */ 00481 #define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) 00482 00483 #if defined (DUAL_CORE) 00484 /** 00485 * @brief Clear the AVD EXTI D2 flag. 00486 * @retval None. 00487 */ 00488 #define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) 00489 #endif /* defined (DUAL_CORE) */ 00490 00491 /** 00492 * @brief Generates a Software interrupt on AVD EXTI line. 00493 * @retval None. 00494 */ 00495 #define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD) 00496 /** 00497 * @} 00498 */ 00499 00500 /* Exported functions --------------------------------------------------------*/ 00501 00502 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions 00503 * @{ 00504 */ 00505 00506 /** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions 00507 * @{ 00508 */ 00509 HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource); 00510 uint32_t HAL_PWREx_GetSupplyConfig (void); 00511 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling); 00512 uint32_t HAL_PWREx_GetVoltageRange (void); 00513 HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling); 00514 uint32_t HAL_PWREx_GetStopModeVoltageRange (void); 00515 /** 00516 * @} 00517 */ 00518 00519 /** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions 00520 * @{ 00521 */ 00522 /* System low power control functions */ 00523 #if defined (PWR_CPUCR_RETDS_CD) 00524 void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry); 00525 #endif /* defined (PWR_CPUCR_RETDS_CD) */ 00526 void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain); 00527 void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain); 00528 void HAL_PWREx_ConfigD3Domain (uint32_t D3State); 00529 /* Clear Cortex-Mx pending flag */ 00530 void HAL_PWREx_ClearPendingEvent (void); 00531 #if defined (DUAL_CORE) 00532 /* Clear domain flags */ 00533 void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags); 00534 /* Core Hold/Release functions */ 00535 HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU); 00536 void HAL_PWREx_ReleaseCore (uint32_t CPU); 00537 #endif /* defined (DUAL_CORE) */ 00538 /* Flash low power control functions */ 00539 void HAL_PWREx_EnableFlashPowerDown (void); 00540 void HAL_PWREx_DisableFlashPowerDown (void); 00541 #if defined (PWR_CR1_SRDRAMSO) 00542 /* Memory shut-off functions */ 00543 void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock); 00544 void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock); 00545 #endif /* defined(PWR_CR1_SRDRAMSO) */ 00546 /* Wakeup Pins control functions */ 00547 void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams); 00548 void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin); 00549 uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag); 00550 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag); 00551 /* Power Wakeup PIN IRQ Handler */ 00552 void HAL_PWREx_WAKEUP_PIN_IRQHandler (void); 00553 void HAL_PWREx_WKUP1_Callback (void); 00554 void HAL_PWREx_WKUP2_Callback (void); 00555 #if defined (PWR_WKUPEPR_WKUPEN3) 00556 void HAL_PWREx_WKUP3_Callback (void); 00557 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 00558 void HAL_PWREx_WKUP4_Callback (void); 00559 #if defined (PWR_WKUPEPR_WKUPEN5) 00560 void HAL_PWREx_WKUP5_Callback (void); 00561 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */ 00562 void HAL_PWREx_WKUP6_Callback (void); 00563 /** 00564 * @} 00565 */ 00566 00567 /** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions 00568 * @{ 00569 */ 00570 /* Backup regulator control functions */ 00571 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void); 00572 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void); 00573 /* USB regulator control functions */ 00574 HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void); 00575 HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void); 00576 void HAL_PWREx_EnableUSBVoltageDetector (void); 00577 void HAL_PWREx_DisableUSBVoltageDetector (void); 00578 /* Battery control functions */ 00579 void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue); 00580 void HAL_PWREx_DisableBatteryCharging (void); 00581 #if defined (PWR_CR1_BOOSTE) 00582 /* Analog Booster functions */ 00583 void HAL_PWREx_EnableAnalogBooster (void); 00584 void HAL_PWREx_DisableAnalogBooster (void); 00585 #endif /* PWR_CR1_BOOSTE */ 00586 /** 00587 * @} 00588 */ 00589 00590 /** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions 00591 * @{ 00592 */ 00593 /* Power VBAT/Temperature monitoring functions */ 00594 void HAL_PWREx_EnableMonitoring (void); 00595 void HAL_PWREx_DisableMonitoring (void); 00596 uint32_t HAL_PWREx_GetTemperatureLevel (void); 00597 uint32_t HAL_PWREx_GetVBATLevel (void); 00598 #if defined (PWR_CSR1_MMCVDO) 00599 PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void); 00600 #endif /* PWR_CSR1_MMCVDO */ 00601 /* Power AVD configuration functions */ 00602 void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD); 00603 void HAL_PWREx_EnableAVD (void); 00604 void HAL_PWREx_DisableAVD (void); 00605 /* Power PVD/AVD IRQ Handler */ 00606 void HAL_PWREx_PVD_AVD_IRQHandler (void); 00607 void HAL_PWREx_AVDCallback (void); 00608 /** 00609 * @} 00610 */ 00611 00612 /** 00613 * @} 00614 */ 00615 /* Private types -------------------------------------------------------------*/ 00616 /* Private variables ---------------------------------------------------------*/ 00617 /* Private constants ---------------------------------------------------------*/ 00618 /* Private macros ------------------------------------------------------------*/ 00619 /** @defgroup PWREx_Private_Macros PWREx Private Macros 00620 * @{ 00621 */ 00622 00623 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters 00624 * @{ 00625 */ 00626 /* Check PWR regulator configuration parameter */ 00627 #if defined (SMPS) 00628 #define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ 00629 ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) ||\ 00630 ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) ||\ 00631 ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) ||\ 00632 ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\ 00633 ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\ 00634 ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) ||\ 00635 ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) ||\ 00636 ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) 00637 00638 #else 00639 #define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ 00640 ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) 00641 #endif /* defined (SMPS) */ 00642 00643 /* Check PWR regulator configuration in STOP mode parameter */ 00644 #define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) ||\ 00645 ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) ||\ 00646 ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5)) 00647 00648 /* Check PWR domain parameter */ 00649 #if defined (PWR_CPUCR_PDDS_D2) 00650 #define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ 00651 ((DOMAIN) == PWR_D2_DOMAIN) ||\ 00652 ((DOMAIN) == PWR_D3_DOMAIN)) 00653 #else 00654 #define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ 00655 ((DOMAIN) == PWR_D3_DOMAIN)) 00656 #endif /* defined (PWR_CPUCR_PDDS_D2) */ 00657 00658 /* Check D3/SRD domain state parameter */ 00659 #define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\ 00660 ((STATE) == PWR_D3_DOMAIN_RUN)) 00661 00662 /* Check wake up pin parameter */ 00663 #if defined (PWR_WKUPEPR_WKUPEN3) 00664 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ 00665 ((PIN) == PWR_WAKEUP_PIN2) ||\ 00666 ((PIN) == PWR_WAKEUP_PIN3) ||\ 00667 ((PIN) == PWR_WAKEUP_PIN4) ||\ 00668 ((PIN) == PWR_WAKEUP_PIN5) ||\ 00669 ((PIN) == PWR_WAKEUP_PIN6) ||\ 00670 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ 00671 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ 00672 ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\ 00673 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ 00674 ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\ 00675 ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ 00676 ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ 00677 ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ 00678 ((PIN) == PWR_WAKEUP_PIN3_LOW) ||\ 00679 ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ 00680 ((PIN) == PWR_WAKEUP_PIN5_LOW) ||\ 00681 ((PIN) == PWR_WAKEUP_PIN6_LOW)) 00682 #else 00683 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ 00684 ((PIN) == PWR_WAKEUP_PIN2) ||\ 00685 ((PIN) == PWR_WAKEUP_PIN4) ||\ 00686 ((PIN) == PWR_WAKEUP_PIN6) ||\ 00687 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ 00688 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ 00689 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ 00690 ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ 00691 ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ 00692 ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ 00693 ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ 00694 ((PIN) == PWR_WAKEUP_PIN6_LOW)) 00695 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 00696 00697 /* Check wake up pin polarity parameter */ 00698 #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\ 00699 ((POLARITY) == PWR_PIN_POLARITY_LOW)) 00700 00701 /* Check wake up pin pull configuration parameter */ 00702 #define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\ 00703 ((PULL) == PWR_PIN_PULL_UP) ||\ 00704 ((PULL) == PWR_PIN_PULL_DOWN)) 00705 00706 /* Check wake up flag parameter */ 00707 #if defined (PWR_WKUPEPR_WKUPEN3) 00708 #define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ 00709 ((FLAG) == PWR_WAKEUP_FLAG2) ||\ 00710 ((FLAG) == PWR_WAKEUP_FLAG3) ||\ 00711 ((FLAG) == PWR_WAKEUP_FLAG4) ||\ 00712 ((FLAG) == PWR_WAKEUP_FLAG5) ||\ 00713 ((FLAG) == PWR_WAKEUP_FLAG6) ||\ 00714 ((FLAG) == PWR_WAKEUP_FLAG_ALL)) 00715 #else 00716 #define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ 00717 ((FLAG) == PWR_WAKEUP_FLAG2) ||\ 00718 ((FLAG) == PWR_WAKEUP_FLAG4) ||\ 00719 ((FLAG) == PWR_WAKEUP_FLAG6) ||\ 00720 ((FLAG) == PWR_WAKEUP_FLAG_ALL)) 00721 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 00722 00723 /* Check wake up flag parameter */ 00724 #define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\ 00725 ((LEVEL) == PWR_AVDLEVEL_1) ||\ 00726 ((LEVEL) == PWR_AVDLEVEL_2) ||\ 00727 ((LEVEL) == PWR_AVDLEVEL_3)) 00728 00729 /* Check AVD mode parameter */ 00730 #define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\ 00731 ((MODE) == PWR_AVD_MODE_IT_FALLING) ||\ 00732 ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\ 00733 ((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\ 00734 ((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\ 00735 ((MODE) == PWR_AVD_MODE_NORMAL) ||\ 00736 ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING)) 00737 00738 /* Check resistor battery parameter */ 00739 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 00740 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 00741 /* Check D1/CD CPU ID parameter */ 00742 #define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID) 00743 00744 #if defined (DUAL_CORE) 00745 /* Check CPU parameter */ 00746 #define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2)) 00747 00748 /* Check D2 CPU ID parameter */ 00749 #define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID) 00750 00751 /* Check PWR domain flag parameter */ 00752 #define IS_PWR_DOMAIN_FLAG(FLAG) (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \ 00753 ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \ 00754 ((FLAG) == PWR_ALL_DOMAIN_FLAGS)) 00755 #endif /* defined (DUAL_CORE) */ 00756 00757 #if defined (PWR_CR1_SRDRAMSO) 00758 /* Check memory block parameter */ 00759 #define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK) || \ 00760 ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK) || \ 00761 ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \ 00762 ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK) || \ 00763 ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK) || \ 00764 ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK) || \ 00765 ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK) || \ 00766 ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK) || \ 00767 ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK)) 00768 #endif /* defined (PWR_CR1_SRDRAMSO) */ 00769 /** 00770 * @} 00771 */ 00772 /** 00773 * @} 00774 */ 00775 00776 /** 00777 * @} 00778 */ 00779 00780 /** 00781 * @} 00782 */ 00783 #ifdef __cplusplus 00784 } 00785 #endif /* __cplusplus */ 00786 00787 00788 #endif /* STM32H7xx_HAL_PWR_EX_H */ 00789
1.7.6.1