Low power control functions. More...

Functions
void	HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
	Enter a Domain to DSTOP mode.
void	HAL_PWREx_ClearPendingEvent (void)
	Clear pending event.
void	HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
	Enter a Domain to DSTANDBY mode.
void	HAL_PWREx_ConfigD3Domain (uint32_t D3State)
	Configure the D3/SRD Domain state when the System in low power mode.
void	HAL_PWREx_EnableFlashPowerDown (void)
	Enable the Flash Power Down in Stop mode.
void	HAL_PWREx_DisableFlashPowerDown (void)
	Disable the Flash Power Down in Stop mode.
void	HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
	Enable the Wake-up PINx functionality.
void	HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
	Disable the Wake-up PINx functionality.
uint32_t	HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
	Get the Wake-Up Pin pending flags.
HAL_StatusTypeDef	HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
	Clear the Wake-Up pin pending flag.
void	HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
	This function handles the PWR WAKEUP PIN interrupt request.
__weak void	HAL_PWREx_WKUP1_Callback (void)
	PWR WKUP1 interrupt callback.
__weak void	HAL_PWREx_WKUP2_Callback (void)
	PWR WKUP2 interrupt callback.
__weak void	HAL_PWREx_WKUP4_Callback (void)
	PWR WKUP4 interrupt callback.
__weak void	HAL_PWREx_WKUP6_Callback (void)
	PWR WKUP6 interrupt callback.

Detailed Description

Low power control functions.

 ===============================================================================
                     ##### Low power control functions #####
 ===============================================================================

    *** Domains Low Power modes configuration ***
    =============================================
    [..]
      This section provides the extended low power mode control APIs.
      The system presents 3 principles domains (D1, D2 and D3) that can be
      operated in low-power modes (DSTOP or DSTANDBY mode):

      (+) DSTOP mode to enters a domain to STOP mode:
       (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
            subsystem is in CSTOP mode and has allocated peripheral in the
            domain.
            In DSTOP mode the domain bus matrix clock is stopped.
       (++) The system enters STOP mode using one of the following scenarios:
        (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains
              enter DSTOP mode.
        (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains
              enter DSTOP mode.
        (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains
              enter DSTOP mode.
        (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain
              enters DSTOP mode.
        (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain
              enters DSTOP mode.
        (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain
              enters DSTOP mode.
        (+++) D1, D2 and D3 domains enter DSTOP mode.
       (++) When the system enters STOP mode, the clocks are stopped and the
            regulator is running in main or low power mode.
       (++) D3 domain can be kept in Run mode regardless of the CPU status when
            enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.

      (+) DSTANDBY mode to enters a domain to STANDBY mode:
       (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control
            register (PWR_CPUCR) for the Dn domain selects Standby mode.
       (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter
            DSTANDBY mode. Consequently the VCORE supply regulator is powered
            off.

   *** DSTOP mode ***
   ==================
    [..]
      In DStop mode the domain bus matrix clock is stopped.
      The Flash memory can enter low-power Stop mode when it is enabled through
      FLPS in PWR_CR1 register. This allows a trade-off between domain DStop
      restart time and low power consumption.
    [..]
      In DStop mode domain peripherals using the LSI or LSE clock and
      peripherals having a kernel clock request are still able to operate.
    [..]
      Before entering DSTOP mode it is recommended to call SCB_CleanDCache
      function in order to clean the D-Cache and guarantee the data integrity
      for the SRAM memories.

      (+) Entry:
         The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator,
         STOPEntry, Domain) function with:
         (++) Regulator:
          (+++) PWR_MAINREGULATOR_ON     : Main regulator ON.
          (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON.
         (++) STOPEntry:
          (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction
          (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction
         (++) Domain:
          (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTOP mode.
          (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode.
          (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTOP mode.

      (+) Exit:
        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.

   *** DSTANDBY mode ***
   =====================
    [..]
      In DStandby mode:
        (+) The domain bus matrix clock is stopped.
        (+) The domain is powered down and the domain RAM and register contents
            are lost.
    [..]
      Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache
      function in order to clean the D-Cache and guarantee the data integrity
      for the SRAM memories.

      (+) Entry:
         The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode
         (Domain) function with:
       (++) Domain:
        (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTANDBY mode.
        (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode.
        (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTANDBY mode.

      (+) Exit:
        WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
        wakeup, tamper event, time stamp event, external reset in NRST pin,
        IWDG reset.

   *** Keep D3/SRD in RUN mode ***
   ===============================
    [..]
      D3/SRD domain can be kept in Run mode regardless of the CPU status when
      entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function
      with :
       (+) D3State:
        (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system
                                  mode.
        (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless
                                 of CPU subsystem mode.

    *** FLASH Power Down configuration ****
    =======================================
    [..]
      By setting the FLPS bit in the PWR_CR1 register using the
      HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters
      power down mode when the device enters STOP mode. When the Flash memory is
      in power down mode, an additional startup delay is incurred when waking up
      from STOP mode.

    *** Wakeup Pins configuration ****
    ===================================
    [..]
      Wakeup pins allow the system to exit from Standby mode. The configuration
      of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams)
      function with:
       (+) sPinParams: structure to enable and configure a wakeup pin:
        (++) WakeUpPin: Wakeup pin to be enabled.
        (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
        (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
    [..]
      The wakeup pins are internally connected to the EXTI lines [55-60] to
      generate an interrupt if enabled. The EXTI lines configuration is done by
      the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c
      file.
    [..]
      When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is
      called and the appropriate flag is set in the PWR_WKUPFR register. Then in
      the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be
      cleared and the appropriate user callback will be called. The user can add
      his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.

Function Documentation

void HAL_PWREx_ClearPendingEvent ( void )

Clear pending event.

Note:: This API clears the pending event in order to enter a given CPU to CSLEEP or CSTOP. It should be called just before APIs performing enter low power mode using Wait For Event request.; Cortex-M7 must be in CRUN mode when calling this API by Cortex-M4.

Return values:

None.

Definition at line 939 of file stm32h7xx_hal_pwr_ex.c.

References CM7_CPUID, and HAL_GetCurrentCPUID().

HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag ( uint32_t WakeUpFlag )

Clear the Wake-Up pin pending flag.

Parameters:

WakeUpFlag,:

Specifies the Wake-Up PIN flag to clear. This parameter can be one of the following values:

PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0.
PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2.
PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8.
PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13.
PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11.
PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1.
PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from all wake up pins.

Note:: The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for devices that support GPIOI port.

Return values:

HAL status.

Definition at line 1394 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_WAKEUP_FLAG.

void HAL_PWREx_ConfigD3Domain ( uint32_t D3State )

Configure the D3/SRD Domain state when the System in low power mode.

Parameters:

D3State

: Specifies the D3/SRD state. This parameter can be one of the following values :

PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep CPU sub-system low power mode.
PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode regardless of the CPU sub-system low power mode.

Return values:

None

Definition at line 1081 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_D3_STATE.

void HAL_PWREx_DisableFlashPowerDown ( void )

Disable the Flash Power Down in Stop mode.

Note:: When Flash Power Down is disabled the Flash memory is kept on normal mode when D1/SRD domain is in DStop mode. This feature allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode.

Return values:

None.

Definition at line 1226 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_DisableWakeUpPin ( uint32_t WakeUpPin )

Disable the Wake-up PINx functionality.

Parameters:

WakeUpPin

: Specifies the Wake-Up pin to be disabled. This parameter can be one of the following values:

PWR_WAKEUP_PIN1 : Disable PA0 wake-up PIN.
PWR_WAKEUP_PIN2 : Disable PA2 wake-up PIN.
PWR_WAKEUP_PIN3 : Disable PI8 wake-up PIN.
PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN.
PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN.
PWR_WAKEUP_PIN6 : Disable PC1 wake-up PIN.

Note:: The PWR_WAKEUP_PIN3 and PWR_WAKEUP_PIN5 are available only for devices that support GPIOI port.

Return values:

None

Definition at line 1344 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWREx_EnableFlashPowerDown ( void )

Enable the Flash Power Down in Stop mode.

Note:: When Flash Power Down is enabled the Flash memory enters low-power mode when D1/SRD domain is in DStop mode. This feature allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode.

Return values:

None.

Definition at line 1212 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_EnableWakeUpPin ( PWREx_WakeupPinTypeDef * sPinParams )

Enable the Wake-up PINx functionality.

Parameters:

sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that contains the configuration information for the wake-up Pin.

Note:: For dual core devices, please ensure to configure the EXTI lines for the different Cortex-Mx. All combination are allowed: wake up only Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.

Return values:

None.

Definition at line 1302 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, IS_PWR_WAKEUP_PIN, IS_PWR_WAKEUP_PIN_POLARITY, IS_PWR_WAKEUP_PIN_PULL, PWREx_WakeupPinTypeDef::PinPolarity, PWREx_WakeupPinTypeDef::PinPull, PWR_EXTI_WAKEUP_PINS_MASK, PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET, and PWREx_WakeupPinTypeDef::WakeUpPin.

void HAL_PWREx_EnterSTANDBYMode ( uint32_t Domain )

Enter a Domain to DSTANDBY mode.

Note:: This API gives flexibility to manage independently each domain STANDBY mode. For dual core lines, this API should be executed with the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When it is executed by all available Cortex-Mx, the system enter STANDBY mode. For single core lines, calling this API with D1/SRD the selected domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0 and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1.; The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for the Dn domain select Standby mode. When the system enters Standby mode, the voltage regulator is disabled.; When D2 or D3 domain is in DStandby mode and the CPU sets the domain PDDS_Dn bit to select Stop mode, the domain remains in DStandby mode. The domain will only exit DStandby when the CPU allocates a peripheral in the domain.; The system D3/SRD domain enters Standby mode only when the D1 and D2 domain are in DStandby.; Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.

Parameters:

Domain

: Specifies the Domain to enter to STANDBY mode. This parameter can be one of the following values:

PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode.
PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode.

Return values:

None

Definition at line 986 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, CM7_CPUID, HAL_GetCurrentCPUID(), IS_PWR_DOMAIN, PWR_D1_DOMAIN, and PWR_D2_DOMAIN.

void HAL_PWREx_EnterSTOPMode	(	uint32_t	Regulator,
		uint8_t	STOPEntry,
		uint32_t	Domain
	)

Enter a Domain to DSTOP mode.

Note:: This API gives flexibility to manage independently each domain STOP mode. For dual core lines, this API should be executed with the corresponding Cortex-Mx to enter domain to DSTOP mode. When it is executed by all available Cortex-Mx, the system enter to STOP mode. For single core lines, calling this API with domain parameter set to PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the CPUCR_RUN_D3 is cleared.; In DStop mode the domain bus matrix clock is stopped.; The system D3/SRD domain enter Stop mode only when the CPU subsystem is in CStop mode, the EXTI wakeup sources are inactive and at least one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for any domain request Stop.; Before entering DSTOP mode it is recommended to call SCB_CleanDCache function in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.; In System Stop mode, the domain peripherals that use the LSI or LSE clock, and the peripherals that have a kernel clock request to select HSI or CSI as source, are still able to operate.

Parameters:

Regulator	: Specifies the regulator state in STOP mode. This parameter can be one of the following values: PWR_MAINREGULATOR_ON : STOP mode with regulator ON. PWR_LOWPOWERREGULATOR_ON : STOP mode with low power regulator ON.
STOPEntry	: Specifies if STOP mode in entered with WFI or WFE intrinsic instruction. This parameter can be one of the following values: PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
Domain	: Specifies the Domain to enter in DSTOP mode. This parameter can be one of the following values: PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode. PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode. PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode.