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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_rcc_ex.c 00004 * @author MCD Application Team 00005 * @brief Extended RCC HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities RCC extension peripheral: 00008 * + Extended Peripheral Control functions 00009 * 00010 ****************************************************************************** 00011 * @attention 00012 * 00013 * Copyright (c) 2017 STMicroelectronics. 00014 * All rights reserved. 00015 * 00016 * This software is licensed under terms that can be found in the LICENSE file in 00017 * the root directory of this software component. 00018 * If no LICENSE file comes with this software, it is provided AS-IS. 00019 ****************************************************************************** 00020 */ 00021 00022 /* Includes ------------------------------------------------------------------*/ 00023 #include "stm32h7xx_hal.h" 00024 00025 /** @addtogroup STM32H7xx_HAL_Driver 00026 * @{ 00027 */ 00028 00029 /** @defgroup RCCEx RCCEx 00030 * @brief RCC HAL module driver 00031 * @{ 00032 */ 00033 00034 #ifdef HAL_RCC_MODULE_ENABLED 00035 00036 /* Private typedef -----------------------------------------------------------*/ 00037 /* Private defines -----------------------------------------------------------*/ 00038 /** @defgroup RCCEx_Private_defines RCCEx Private Defines 00039 * @{ 00040 */ 00041 #define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ 00042 #define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ 00043 00044 #define DIVIDER_P_UPDATE 0U 00045 #define DIVIDER_Q_UPDATE 1U 00046 #define DIVIDER_R_UPDATE 2U 00047 /** 00048 * @} 00049 */ 00050 00051 /* Private macros ------------------------------------------------------------*/ 00052 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros 00053 * @{ 00054 */ 00055 /** 00056 * @} 00057 */ 00058 00059 /* Private variables ---------------------------------------------------------*/ 00060 /* Private function prototypes -----------------------------------------------*/ 00061 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider); 00062 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider); 00063 00064 /* Exported functions --------------------------------------------------------*/ 00065 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions 00066 * @{ 00067 */ 00068 00069 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions 00070 * @brief Extended Peripheral Control functions 00071 * 00072 @verbatim 00073 =============================================================================== 00074 ##### Extended Peripheral Control functions ##### 00075 =============================================================================== 00076 [..] 00077 This subsection provides a set of functions allowing to control the RCC Clocks 00078 frequencies. 00079 [..] 00080 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to 00081 select the RTC clock source; in this case the Backup domain will be reset in 00082 order to modify the RTC Clock source, as consequence RTC registers (including 00083 the backup registers) and RCC_BDCR register are set to their reset values. 00084 00085 @endverbatim 00086 * @{ 00087 */ 00088 /** 00089 * @brief Initializes the RCC extended peripherals clocks according to the specified 00090 * parameters in the RCC_PeriphCLKInitTypeDef. 00091 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 00092 * contains the configuration information for the Extended Peripherals 00093 * clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123, 00094 * USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC, 00095 * SAI4A*, SAI4B*, SPI6, RTC). 00096 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select 00097 * the RTC clock source; in this case the Backup domain will be reset in 00098 * order to modify the RTC Clock source, as consequence RTC registers (including 00099 * the backup registers) are set to their reset values. 00100 * 00101 * (*) : Available on some STM32H7 lines only. 00102 * 00103 * @retval HAL status 00104 */ 00105 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) 00106 { 00107 uint32_t tmpreg; 00108 uint32_t tickstart; 00109 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 00110 HAL_StatusTypeDef status = HAL_OK; /* Final status */ 00111 00112 /*---------------------------- SPDIFRX configuration -------------------------------*/ 00113 00114 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 00115 { 00116 00117 switch(PeriphClkInit->SpdifrxClockSelection) 00118 { 00119 case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ 00120 /* Enable PLL1Q Clock output generated form System PLL . */ 00121 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 00122 00123 /* SPDIFRX clock source configuration done later after clock selection check */ 00124 break; 00125 00126 case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ 00127 00128 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 00129 00130 /* SPDIFRX clock source configuration done later after clock selection check */ 00131 break; 00132 00133 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ 00134 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 00135 00136 /* SPDIFRX clock source configuration done later after clock selection check */ 00137 break; 00138 00139 case RCC_SPDIFRXCLKSOURCE_HSI: 00140 /* Internal OSC clock is used as source of SPDIFRX clock*/ 00141 /* SPDIFRX clock source configuration done later after clock selection check */ 00142 break; 00143 00144 default: 00145 ret = HAL_ERROR; 00146 break; 00147 } 00148 00149 if(ret == HAL_OK) 00150 { 00151 /* Set the source of SPDIFRX clock*/ 00152 __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 00153 } 00154 else 00155 { 00156 /* set overall return value */ 00157 status = ret; 00158 } 00159 } 00160 00161 /*---------------------------- SAI1 configuration -------------------------------*/ 00162 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 00163 { 00164 switch(PeriphClkInit->Sai1ClockSelection) 00165 { 00166 case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ 00167 /* Enable SAI Clock output generated form System PLL . */ 00168 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 00169 00170 /* SAI1 clock source configuration done later after clock selection check */ 00171 break; 00172 00173 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ 00174 00175 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 00176 00177 /* SAI1 clock source configuration done later after clock selection check */ 00178 break; 00179 00180 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ 00181 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 00182 00183 /* SAI1 clock source configuration done later after clock selection check */ 00184 break; 00185 00186 case RCC_SAI1CLKSOURCE_PIN: 00187 /* External clock is used as source of SAI1 clock*/ 00188 /* SAI1 clock source configuration done later after clock selection check */ 00189 break; 00190 00191 case RCC_SAI1CLKSOURCE_CLKP: 00192 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ 00193 /* SAI1 clock source configuration done later after clock selection check */ 00194 break; 00195 00196 default: 00197 ret = HAL_ERROR; 00198 break; 00199 } 00200 00201 if(ret == HAL_OK) 00202 { 00203 /* Set the source of SAI1 clock*/ 00204 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 00205 } 00206 else 00207 { 00208 /* set overall return value */ 00209 status = ret; 00210 } 00211 } 00212 00213 #if defined(SAI3) 00214 /*---------------------------- SAI2/3 configuration -------------------------------*/ 00215 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 00216 { 00217 switch(PeriphClkInit->Sai23ClockSelection) 00218 { 00219 case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ 00220 /* Enable SAI Clock output generated form System PLL . */ 00221 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 00222 00223 /* SAI2/3 clock source configuration done later after clock selection check */ 00224 break; 00225 00226 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ 00227 00228 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 00229 00230 /* SAI2/3 clock source configuration done later after clock selection check */ 00231 break; 00232 00233 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ 00234 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 00235 00236 /* SAI2/3 clock source configuration done later after clock selection check */ 00237 break; 00238 00239 case RCC_SAI23CLKSOURCE_PIN: 00240 /* External clock is used as source of SAI2/3 clock*/ 00241 /* SAI2/3 clock source configuration done later after clock selection check */ 00242 break; 00243 00244 case RCC_SAI23CLKSOURCE_CLKP: 00245 /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ 00246 /* SAI2/3 clock source configuration done later after clock selection check */ 00247 break; 00248 00249 default: 00250 ret = HAL_ERROR; 00251 break; 00252 } 00253 00254 if(ret == HAL_OK) 00255 { 00256 /* Set the source of SAI2/3 clock*/ 00257 __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 00258 } 00259 else 00260 { 00261 /* set overall return value */ 00262 status = ret; 00263 } 00264 } 00265 00266 #endif /* SAI3 */ 00267 00268 #if defined(RCC_CDCCIP1R_SAI2ASEL) 00269 /*---------------------------- SAI2A configuration -------------------------------*/ 00270 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) 00271 { 00272 switch(PeriphClkInit->Sai2AClockSelection) 00273 { 00274 case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */ 00275 /* Enable SAI2A Clock output generated form System PLL . */ 00276 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 00277 00278 /* SAI2A clock source configuration done later after clock selection check */ 00279 break; 00280 00281 case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */ 00282 00283 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 00284 00285 /* SAI2A clock source configuration done later after clock selection check */ 00286 break; 00287 00288 case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */ 00289 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 00290 00291 /* SAI2A clock source configuration done later after clock selection check */ 00292 break; 00293 00294 case RCC_SAI2ACLKSOURCE_PIN: 00295 /* External clock is used as source of SAI2A clock*/ 00296 /* SAI2A clock source configuration done later after clock selection check */ 00297 break; 00298 00299 case RCC_SAI2ACLKSOURCE_CLKP: 00300 /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */ 00301 /* SAI2A clock source configuration done later after clock selection check */ 00302 break; 00303 00304 case RCC_SAI2ACLKSOURCE_SPDIF: 00305 /* SPDIF clock is used as source of SAI2A clock */ 00306 /* SAI2A clock source configuration done later after clock selection check */ 00307 break; 00308 00309 default: 00310 ret = HAL_ERROR; 00311 break; 00312 } 00313 00314 if(ret == HAL_OK) 00315 { 00316 /* Set the source of SAI2A clock*/ 00317 __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection); 00318 } 00319 else 00320 { 00321 /* set overall return value */ 00322 status = ret; 00323 } 00324 } 00325 #endif /*SAI2A*/ 00326 00327 #if defined(RCC_CDCCIP1R_SAI2BSEL) 00328 00329 /*---------------------------- SAI2B configuration -------------------------------*/ 00330 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) 00331 { 00332 switch(PeriphClkInit->Sai2BClockSelection) 00333 { 00334 case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */ 00335 /* Enable SAI Clock output generated form System PLL . */ 00336 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 00337 00338 /* SAI2B clock source configuration done later after clock selection check */ 00339 break; 00340 00341 case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */ 00342 00343 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 00344 00345 /* SAI2B clock source configuration done later after clock selection check */ 00346 break; 00347 00348 case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */ 00349 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 00350 00351 /* SAI2B clock source configuration done later after clock selection check */ 00352 break; 00353 00354 case RCC_SAI2BCLKSOURCE_PIN: 00355 /* External clock is used as source of SAI2B clock*/ 00356 /* SAI2B clock source configuration done later after clock selection check */ 00357 break; 00358 00359 case RCC_SAI2BCLKSOURCE_CLKP: 00360 /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */ 00361 /* SAI2B clock source configuration done later after clock selection check */ 00362 break; 00363 00364 case RCC_SAI2BCLKSOURCE_SPDIF: 00365 /* SPDIF clock is used as source of SAI2B clock */ 00366 /* SAI2B clock source configuration done later after clock selection check */ 00367 break; 00368 00369 default: 00370 ret = HAL_ERROR; 00371 break; 00372 } 00373 00374 if(ret == HAL_OK) 00375 { 00376 /* Set the source of SAI2B clock*/ 00377 __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection); 00378 } 00379 else 00380 { 00381 /* set overall return value */ 00382 status = ret; 00383 } 00384 } 00385 #endif /*SAI2B*/ 00386 00387 #if defined(SAI4) 00388 /*---------------------------- SAI4A configuration -------------------------------*/ 00389 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 00390 { 00391 switch(PeriphClkInit->Sai4AClockSelection) 00392 { 00393 case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ 00394 /* Enable SAI Clock output generated form System PLL . */ 00395 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 00396 00397 /* SAI1 clock source configuration done later after clock selection check */ 00398 break; 00399 00400 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ 00401 00402 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 00403 00404 /* SAI2 clock source configuration done later after clock selection check */ 00405 break; 00406 00407 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ 00408 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 00409 00410 /* SAI1 clock source configuration done later after clock selection check */ 00411 break; 00412 00413 case RCC_SAI4ACLKSOURCE_PIN: 00414 /* External clock is used as source of SAI2 clock*/ 00415 /* SAI2 clock source configuration done later after clock selection check */ 00416 break; 00417 00418 case RCC_SAI4ACLKSOURCE_CLKP: 00419 /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ 00420 /* SAI1 clock source configuration done later after clock selection check */ 00421 break; 00422 00423 #if defined(RCC_VER_3_0) 00424 case RCC_SAI4ACLKSOURCE_SPDIF: 00425 /* SPDIF clock is used as source of SAI4A clock */ 00426 /* SAI4A clock source configuration done later after clock selection check */ 00427 break; 00428 #endif /* RCC_VER_3_0 */ 00429 00430 default: 00431 ret = HAL_ERROR; 00432 break; 00433 } 00434 00435 if(ret == HAL_OK) 00436 { 00437 /* Set the source of SAI4A clock*/ 00438 __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 00439 } 00440 else 00441 { 00442 /* set overall return value */ 00443 status = ret; 00444 } 00445 } 00446 /*---------------------------- SAI4B configuration -------------------------------*/ 00447 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 00448 { 00449 switch(PeriphClkInit->Sai4BClockSelection) 00450 { 00451 case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ 00452 /* Enable SAI Clock output generated form System PLL . */ 00453 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 00454 00455 /* SAI1 clock source configuration done later after clock selection check */ 00456 break; 00457 00458 case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ 00459 00460 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 00461 00462 /* SAI2 clock source configuration done later after clock selection check */ 00463 break; 00464 00465 case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ 00466 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 00467 00468 /* SAI1 clock source configuration done later after clock selection check */ 00469 break; 00470 00471 case RCC_SAI4BCLKSOURCE_PIN: 00472 /* External clock is used as source of SAI2 clock*/ 00473 /* SAI2 clock source configuration done later after clock selection check */ 00474 break; 00475 00476 case RCC_SAI4BCLKSOURCE_CLKP: 00477 /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ 00478 /* SAI1 clock source configuration done later after clock selection check */ 00479 break; 00480 00481 #if defined(RCC_VER_3_0) 00482 case RCC_SAI4BCLKSOURCE_SPDIF: 00483 /* SPDIF clock is used as source of SAI4B clock */ 00484 /* SAI4B clock source configuration done later after clock selection check */ 00485 break; 00486 #endif /* RCC_VER_3_0 */ 00487 00488 default: 00489 ret = HAL_ERROR; 00490 break; 00491 } 00492 00493 if(ret == HAL_OK) 00494 { 00495 /* Set the source of SAI4B clock*/ 00496 __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 00497 } 00498 else 00499 { 00500 /* set overall return value */ 00501 status = ret; 00502 } 00503 } 00504 #endif /*SAI4*/ 00505 00506 #if defined(QUADSPI) 00507 /*---------------------------- QSPI configuration -------------------------------*/ 00508 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 00509 { 00510 switch(PeriphClkInit->QspiClockSelection) 00511 { 00512 case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ 00513 /* Enable QSPI Clock output generated form System PLL . */ 00514 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 00515 00516 /* QSPI clock source configuration done later after clock selection check */ 00517 break; 00518 00519 case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ 00520 00521 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 00522 00523 /* QSPI clock source configuration done later after clock selection check */ 00524 break; 00525 00526 00527 case RCC_QSPICLKSOURCE_CLKP: 00528 /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */ 00529 /* QSPI clock source configuration done later after clock selection check */ 00530 break; 00531 00532 case RCC_QSPICLKSOURCE_D1HCLK: 00533 /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ 00534 break; 00535 00536 default: 00537 ret = HAL_ERROR; 00538 break; 00539 } 00540 00541 if(ret == HAL_OK) 00542 { 00543 /* Set the source of QSPI clock*/ 00544 __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 00545 } 00546 else 00547 { 00548 /* set overall return value */ 00549 status = ret; 00550 } 00551 } 00552 #endif /*QUADSPI*/ 00553 00554 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00555 /*---------------------------- OCTOSPI configuration -------------------------------*/ 00556 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) 00557 { 00558 switch(PeriphClkInit->OspiClockSelection) 00559 { 00560 case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ 00561 /* Enable OSPI Clock output generated form System PLL . */ 00562 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 00563 00564 /* OSPI clock source configuration done later after clock selection check */ 00565 break; 00566 00567 case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ 00568 00569 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 00570 00571 /* OSPI clock source configuration done later after clock selection check */ 00572 break; 00573 00574 00575 case RCC_OSPICLKSOURCE_CLKP: 00576 /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */ 00577 /* OSPI clock source configuration done later after clock selection check */ 00578 break; 00579 00580 case RCC_OSPICLKSOURCE_HCLK: 00581 /* HCLK clock selected as OSPI kernel peripheral clock */ 00582 break; 00583 00584 default: 00585 ret = HAL_ERROR; 00586 break; 00587 } 00588 00589 if(ret == HAL_OK) 00590 { 00591 /* Set the source of OSPI clock*/ 00592 __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); 00593 } 00594 else 00595 { 00596 /* set overall return value */ 00597 status = ret; 00598 } 00599 } 00600 #endif /*OCTOSPI*/ 00601 00602 /*---------------------------- SPI1/2/3 configuration -------------------------------*/ 00603 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 00604 { 00605 switch(PeriphClkInit->Spi123ClockSelection) 00606 { 00607 case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ 00608 /* Enable SPI Clock output generated form System PLL . */ 00609 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 00610 00611 /* SPI1/2/3 clock source configuration done later after clock selection check */ 00612 break; 00613 00614 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ 00615 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 00616 00617 /* SPI1/2/3 clock source configuration done later after clock selection check */ 00618 break; 00619 00620 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ 00621 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 00622 00623 /* SPI1/2/3 clock source configuration done later after clock selection check */ 00624 break; 00625 00626 case RCC_SPI123CLKSOURCE_PIN: 00627 /* External clock is used as source of SPI1/2/3 clock*/ 00628 /* SPI1/2/3 clock source configuration done later after clock selection check */ 00629 break; 00630 00631 case RCC_SPI123CLKSOURCE_CLKP: 00632 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ 00633 /* SPI1/2/3 clock source configuration done later after clock selection check */ 00634 break; 00635 00636 default: 00637 ret = HAL_ERROR; 00638 break; 00639 } 00640 00641 if(ret == HAL_OK) 00642 { 00643 /* Set the source of SPI1/2/3 clock*/ 00644 __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 00645 } 00646 else 00647 { 00648 /* set overall return value */ 00649 status = ret; 00650 } 00651 } 00652 00653 /*---------------------------- SPI4/5 configuration -------------------------------*/ 00654 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 00655 { 00656 switch(PeriphClkInit->Spi45ClockSelection) 00657 { 00658 case RCC_SPI45CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for SPI4/5 */ 00659 /* SPI4/5 clock source configuration done later after clock selection check */ 00660 break; 00661 00662 case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ 00663 00664 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 00665 00666 /* SPI4/5 clock source configuration done later after clock selection check */ 00667 break; 00668 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ 00669 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 00670 /* SPI4/5 clock source configuration done later after clock selection check */ 00671 break; 00672 00673 case RCC_SPI45CLKSOURCE_HSI: 00674 /* HSI oscillator clock is used as source of SPI4/5 clock*/ 00675 /* SPI4/5 clock source configuration done later after clock selection check */ 00676 break; 00677 00678 case RCC_SPI45CLKSOURCE_CSI: 00679 /* CSI oscillator clock is used as source of SPI4/5 clock */ 00680 /* SPI4/5 clock source configuration done later after clock selection check */ 00681 break; 00682 00683 case RCC_SPI45CLKSOURCE_HSE: 00684 /* HSE, oscillator is used as source of SPI4/5 clock */ 00685 /* SPI4/5 clock source configuration done later after clock selection check */ 00686 break; 00687 00688 default: 00689 ret = HAL_ERROR; 00690 break; 00691 } 00692 00693 if(ret == HAL_OK) 00694 { 00695 /* Set the source of SPI4/5 clock*/ 00696 __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 00697 } 00698 else 00699 { 00700 /* set overall return value */ 00701 status = ret; 00702 } 00703 } 00704 00705 /*---------------------------- SPI6 configuration -------------------------------*/ 00706 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 00707 { 00708 switch(PeriphClkInit->Spi6ClockSelection) 00709 { 00710 case RCC_SPI6CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/ 00711 /* SPI6 clock source configuration done later after clock selection check */ 00712 break; 00713 00714 case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ 00715 00716 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 00717 00718 /* SPI6 clock source configuration done later after clock selection check */ 00719 break; 00720 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ 00721 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 00722 /* SPI6 clock source configuration done later after clock selection check */ 00723 break; 00724 00725 case RCC_SPI6CLKSOURCE_HSI: 00726 /* HSI oscillator clock is used as source of SPI6 clock*/ 00727 /* SPI6 clock source configuration done later after clock selection check */ 00728 break; 00729 00730 case RCC_SPI6CLKSOURCE_CSI: 00731 /* CSI oscillator clock is used as source of SPI6 clock */ 00732 /* SPI6 clock source configuration done later after clock selection check */ 00733 break; 00734 00735 case RCC_SPI6CLKSOURCE_HSE: 00736 /* HSE, oscillator is used as source of SPI6 clock */ 00737 /* SPI6 clock source configuration done later after clock selection check */ 00738 break; 00739 #if defined(RCC_SPI6CLKSOURCE_PIN) 00740 case RCC_SPI6CLKSOURCE_PIN: 00741 /* 2S_CKIN is used as source of SPI6 clock */ 00742 /* SPI6 clock source configuration done later after clock selection check */ 00743 break; 00744 #endif 00745 00746 default: 00747 ret = HAL_ERROR; 00748 break; 00749 } 00750 00751 if(ret == HAL_OK) 00752 { 00753 /* Set the source of SPI6 clock*/ 00754 __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 00755 } 00756 else 00757 { 00758 /* set overall return value */ 00759 status = ret; 00760 } 00761 } 00762 00763 #if defined(DSI) 00764 /*---------------------------- DSI configuration -------------------------------*/ 00765 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) 00766 { 00767 switch(PeriphClkInit->DsiClockSelection) 00768 { 00769 00770 case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/ 00771 00772 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 00773 00774 /* DSI clock source configuration done later after clock selection check */ 00775 break; 00776 00777 case RCC_DSICLKSOURCE_PHY: 00778 /* PHY is used as clock source for DSI*/ 00779 /* DSI clock source configuration done later after clock selection check */ 00780 break; 00781 00782 default: 00783 ret = HAL_ERROR; 00784 break; 00785 } 00786 00787 if(ret == HAL_OK) 00788 { 00789 /* Set the source of DSI clock*/ 00790 __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); 00791 } 00792 else 00793 { 00794 /* set overall return value */ 00795 status = ret; 00796 } 00797 } 00798 #endif /*DSI*/ 00799 00800 #if defined(FDCAN1) || defined(FDCAN2) 00801 /*---------------------------- FDCAN configuration -------------------------------*/ 00802 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 00803 { 00804 switch(PeriphClkInit->FdcanClockSelection) 00805 { 00806 case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ 00807 /* Enable FDCAN Clock output generated form System PLL . */ 00808 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 00809 00810 /* FDCAN clock source configuration done later after clock selection check */ 00811 break; 00812 00813 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ 00814 00815 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 00816 00817 /* FDCAN clock source configuration done later after clock selection check */ 00818 break; 00819 00820 case RCC_FDCANCLKSOURCE_HSE: 00821 /* HSE is used as clock source for FDCAN*/ 00822 /* FDCAN clock source configuration done later after clock selection check */ 00823 break; 00824 00825 default: 00826 ret = HAL_ERROR; 00827 break; 00828 } 00829 00830 if(ret == HAL_OK) 00831 { 00832 /* Set the source of FDCAN clock*/ 00833 __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 00834 } 00835 else 00836 { 00837 /* set overall return value */ 00838 status = ret; 00839 } 00840 } 00841 #endif /*FDCAN1 || FDCAN2*/ 00842 00843 /*---------------------------- FMC configuration -------------------------------*/ 00844 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 00845 { 00846 switch(PeriphClkInit->FmcClockSelection) 00847 { 00848 case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ 00849 /* Enable FMC Clock output generated form System PLL . */ 00850 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 00851 00852 /* FMC clock source configuration done later after clock selection check */ 00853 break; 00854 00855 case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ 00856 00857 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 00858 00859 /* FMC clock source configuration done later after clock selection check */ 00860 break; 00861 00862 00863 case RCC_FMCCLKSOURCE_CLKP: 00864 /* HSI, HSE, or CSI oscillator is used as source of FMC clock */ 00865 /* FMC clock source configuration done later after clock selection check */ 00866 break; 00867 00868 case RCC_FMCCLKSOURCE_HCLK: 00869 /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ 00870 break; 00871 00872 default: 00873 ret = HAL_ERROR; 00874 break; 00875 } 00876 00877 if(ret == HAL_OK) 00878 { 00879 /* Set the source of FMC clock*/ 00880 __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 00881 } 00882 else 00883 { 00884 /* set overall return value */ 00885 status = ret; 00886 } 00887 } 00888 00889 /*---------------------------- RTC configuration -------------------------------*/ 00890 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 00891 { 00892 /* check for RTC Parameters used to output RTCCLK */ 00893 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); 00894 00895 /* Enable write access to Backup domain */ 00896 SET_BIT(PWR->CR1, PWR_CR1_DBP); 00897 00898 /* Wait for Backup domain Write protection disable */ 00899 tickstart = HAL_GetTick(); 00900 00901 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 00902 { 00903 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 00904 { 00905 ret = HAL_TIMEOUT; 00906 break; 00907 } 00908 } 00909 00910 if(ret == HAL_OK) 00911 { 00912 /* Reset the Backup domain only if the RTC Clock source selection is modified */ 00913 if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 00914 { 00915 /* Store the content of BDCR register before the reset of Backup Domain */ 00916 tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 00917 /* RTC Clock selection can be changed only if the Backup Domain is reset */ 00918 __HAL_RCC_BACKUPRESET_FORCE(); 00919 __HAL_RCC_BACKUPRESET_RELEASE(); 00920 /* Restore the Content of BDCR register */ 00921 RCC->BDCR = tmpreg; 00922 } 00923 00924 /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ 00925 if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 00926 { 00927 /* Get Start Tick*/ 00928 tickstart = HAL_GetTick(); 00929 00930 /* Wait till LSE is ready */ 00931 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 00932 { 00933 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 00934 { 00935 ret = HAL_TIMEOUT; 00936 break; 00937 } 00938 } 00939 } 00940 00941 if(ret == HAL_OK) 00942 { 00943 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 00944 } 00945 else 00946 { 00947 /* set overall return value */ 00948 status = ret; 00949 } 00950 } 00951 else 00952 { 00953 /* set overall return value */ 00954 status = ret; 00955 } 00956 } 00957 00958 00959 /*-------------------------- USART1/6 configuration --------------------------*/ 00960 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 00961 { 00962 switch(PeriphClkInit->Usart16ClockSelection) 00963 { 00964 case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ 00965 /* USART1/6 clock source configuration done later after clock selection check */ 00966 break; 00967 00968 case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ 00969 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 00970 /* USART1/6 clock source configuration done later after clock selection check */ 00971 break; 00972 00973 case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ 00974 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 00975 /* USART1/6 clock source configuration done later after clock selection check */ 00976 break; 00977 00978 case RCC_USART16CLKSOURCE_HSI: 00979 /* HSI oscillator clock is used as source of USART1/6 clock */ 00980 /* USART1/6 clock source configuration done later after clock selection check */ 00981 break; 00982 00983 case RCC_USART16CLKSOURCE_CSI: 00984 /* CSI oscillator clock is used as source of USART1/6 clock */ 00985 /* USART1/6 clock source configuration done later after clock selection check */ 00986 break; 00987 00988 case RCC_USART16CLKSOURCE_LSE: 00989 /* LSE, oscillator is used as source of USART1/6 clock */ 00990 /* USART1/6 clock source configuration done later after clock selection check */ 00991 break; 00992 00993 default: 00994 ret = HAL_ERROR; 00995 break; 00996 } 00997 00998 if(ret == HAL_OK) 00999 { 01000 /* Set the source of USART1/6 clock */ 01001 __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 01002 } 01003 else 01004 { 01005 /* set overall return value */ 01006 status = ret; 01007 } 01008 } 01009 01010 /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ 01011 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 01012 { 01013 switch(PeriphClkInit->Usart234578ClockSelection) 01014 { 01015 case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ 01016 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ 01017 break; 01018 01019 case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ 01020 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 01021 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ 01022 break; 01023 01024 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ 01025 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 01026 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ 01027 break; 01028 01029 case RCC_USART234578CLKSOURCE_HSI: 01030 /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ 01031 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ 01032 break; 01033 01034 case RCC_USART234578CLKSOURCE_CSI: 01035 /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ 01036 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ 01037 break; 01038 01039 case RCC_USART234578CLKSOURCE_LSE: 01040 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ 01041 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ 01042 break; 01043 01044 default: 01045 ret = HAL_ERROR; 01046 break; 01047 } 01048 01049 if(ret == HAL_OK) 01050 { 01051 /* Set the source of USART2/3/4/5/7/8 clock */ 01052 __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 01053 } 01054 else 01055 { 01056 /* set overall return value */ 01057 status = ret; 01058 } 01059 } 01060 01061 /*-------------------------- LPUART1 Configuration -------------------------*/ 01062 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 01063 { 01064 switch(PeriphClkInit->Lpuart1ClockSelection) 01065 { 01066 case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ 01067 /* LPUART1 clock source configuration done later after clock selection check */ 01068 break; 01069 01070 case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ 01071 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 01072 /* LPUART1 clock source configuration done later after clock selection check */ 01073 break; 01074 01075 case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ 01076 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 01077 /* LPUART1 clock source configuration done later after clock selection check */ 01078 break; 01079 01080 case RCC_LPUART1CLKSOURCE_HSI: 01081 /* HSI oscillator clock is used as source of LPUART1 clock */ 01082 /* LPUART1 clock source configuration done later after clock selection check */ 01083 break; 01084 01085 case RCC_LPUART1CLKSOURCE_CSI: 01086 /* CSI oscillator clock is used as source of LPUART1 clock */ 01087 /* LPUART1 clock source configuration done later after clock selection check */ 01088 break; 01089 01090 case RCC_LPUART1CLKSOURCE_LSE: 01091 /* LSE, oscillator is used as source of LPUART1 clock */ 01092 /* LPUART1 clock source configuration done later after clock selection check */ 01093 break; 01094 01095 default: 01096 ret = HAL_ERROR; 01097 break; 01098 } 01099 01100 if(ret == HAL_OK) 01101 { 01102 /* Set the source of LPUART1 clock */ 01103 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 01104 } 01105 else 01106 { 01107 /* set overall return value */ 01108 status = ret; 01109 } 01110 } 01111 01112 /*---------------------------- LPTIM1 configuration -------------------------------*/ 01113 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 01114 { 01115 switch(PeriphClkInit->Lptim1ClockSelection) 01116 { 01117 case RCC_LPTIM1CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for LPTIM1*/ 01118 /* LPTIM1 clock source configuration done later after clock selection check */ 01119 break; 01120 01121 case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ 01122 01123 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 01124 01125 /* LPTIM1 clock source configuration done later after clock selection check */ 01126 break; 01127 01128 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ 01129 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 01130 01131 /* LPTIM1 clock source configuration done later after clock selection check */ 01132 break; 01133 01134 case RCC_LPTIM1CLKSOURCE_LSE: 01135 /* External low speed OSC clock is used as source of LPTIM1 clock*/ 01136 /* LPTIM1 clock source configuration done later after clock selection check */ 01137 break; 01138 01139 case RCC_LPTIM1CLKSOURCE_LSI: 01140 /* Internal low speed OSC clock is used as source of LPTIM1 clock*/ 01141 /* LPTIM1 clock source configuration done later after clock selection check */ 01142 break; 01143 case RCC_LPTIM1CLKSOURCE_CLKP: 01144 /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ 01145 /* LPTIM1 clock source configuration done later after clock selection check */ 01146 break; 01147 01148 default: 01149 ret = HAL_ERROR; 01150 break; 01151 } 01152 01153 if(ret == HAL_OK) 01154 { 01155 /* Set the source of LPTIM1 clock*/ 01156 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 01157 } 01158 else 01159 { 01160 /* set overall return value */ 01161 status = ret; 01162 } 01163 } 01164 01165 /*---------------------------- LPTIM2 configuration -------------------------------*/ 01166 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 01167 { 01168 switch(PeriphClkInit->Lptim2ClockSelection) 01169 { 01170 case RCC_LPTIM2CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/ 01171 /* LPTIM2 clock source configuration done later after clock selection check */ 01172 break; 01173 01174 case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ 01175 01176 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 01177 01178 /* LPTIM2 clock source configuration done later after clock selection check */ 01179 break; 01180 01181 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ 01182 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 01183 01184 /* LPTIM2 clock source configuration done later after clock selection check */ 01185 break; 01186 01187 case RCC_LPTIM2CLKSOURCE_LSE: 01188 /* External low speed OSC clock is used as source of LPTIM2 clock*/ 01189 /* LPTIM2 clock source configuration done later after clock selection check */ 01190 break; 01191 01192 case RCC_LPTIM2CLKSOURCE_LSI: 01193 /* Internal low speed OSC clock is used as source of LPTIM2 clock*/ 01194 /* LPTIM2 clock source configuration done later after clock selection check */ 01195 break; 01196 case RCC_LPTIM2CLKSOURCE_CLKP: 01197 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ 01198 /* LPTIM2 clock source configuration done later after clock selection check */ 01199 break; 01200 01201 default: 01202 ret = HAL_ERROR; 01203 break; 01204 } 01205 01206 if(ret == HAL_OK) 01207 { 01208 /* Set the source of LPTIM2 clock*/ 01209 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 01210 } 01211 else 01212 { 01213 /* set overall return value */ 01214 status = ret; 01215 } 01216 } 01217 01218 /*---------------------------- LPTIM345 configuration -------------------------------*/ 01219 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 01220 { 01221 switch(PeriphClkInit->Lptim345ClockSelection) 01222 { 01223 01224 case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ 01225 /* LPTIM3/4/5 clock source configuration done later after clock selection check */ 01226 break; 01227 01228 case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ 01229 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 01230 01231 /* LPTIM3/4/5 clock source configuration done later after clock selection check */ 01232 break; 01233 01234 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ 01235 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 01236 01237 /* LPTIM3/4/5 clock source configuration done later after clock selection check */ 01238 break; 01239 01240 case RCC_LPTIM345CLKSOURCE_LSE: 01241 /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */ 01242 /* LPTIM3/4/5 clock source configuration done later after clock selection check */ 01243 break; 01244 01245 case RCC_LPTIM345CLKSOURCE_LSI: 01246 /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */ 01247 /* LPTIM3/4/5 clock source configuration done later after clock selection check */ 01248 break; 01249 case RCC_LPTIM345CLKSOURCE_CLKP: 01250 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ 01251 /* LPTIM3/4/5 clock source configuration done later after clock selection check */ 01252 break; 01253 01254 default: 01255 ret = HAL_ERROR; 01256 break; 01257 } 01258 01259 if(ret == HAL_OK) 01260 { 01261 /* Set the source of LPTIM3/4/5 clock */ 01262 __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 01263 } 01264 else 01265 { 01266 /* set overall return value */ 01267 status = ret; 01268 } 01269 } 01270 01271 /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/ 01272 #if defined(I2C5) 01273 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235) 01274 { 01275 /* Check the parameters */ 01276 assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection)); 01277 01278 if ((PeriphClkInit->I2c1235ClockSelection )== RCC_I2C1235CLKSOURCE_PLL3 ) 01279 { 01280 if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 01281 { 01282 status = HAL_ERROR; 01283 } 01284 } 01285 01286 __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); 01287 01288 } 01289 #else 01290 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 01291 { 01292 /* Check the parameters */ 01293 assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); 01294 01295 if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 ) 01296 { 01297 if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 01298 { 01299 status = HAL_ERROR; 01300 } 01301 } 01302 01303 __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 01304 01305 } 01306 #endif /* I2C5 */ 01307 01308 /*------------------------------ I2C4 Configuration ------------------------*/ 01309 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 01310 { 01311 /* Check the parameters */ 01312 assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); 01313 01314 if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 ) 01315 { 01316 if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 01317 { 01318 status = HAL_ERROR; 01319 } 01320 } 01321 01322 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 01323 01324 } 01325 01326 /*---------------------------- ADC configuration -------------------------------*/ 01327 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 01328 { 01329 switch(PeriphClkInit->AdcClockSelection) 01330 { 01331 01332 case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ 01333 01334 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 01335 01336 /* ADC clock source configuration done later after clock selection check */ 01337 break; 01338 01339 case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ 01340 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 01341 01342 /* ADC clock source configuration done later after clock selection check */ 01343 break; 01344 01345 case RCC_ADCCLKSOURCE_CLKP: 01346 /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ 01347 /* ADC clock source configuration done later after clock selection check */ 01348 break; 01349 01350 default: 01351 ret = HAL_ERROR; 01352 break; 01353 } 01354 01355 if(ret == HAL_OK) 01356 { 01357 /* Set the source of ADC clock*/ 01358 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 01359 } 01360 else 01361 { 01362 /* set overall return value */ 01363 status = ret; 01364 } 01365 } 01366 01367 /*------------------------------ USB Configuration -------------------------*/ 01368 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 01369 { 01370 01371 switch(PeriphClkInit->UsbClockSelection) 01372 { 01373 case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ 01374 /* Enable USB Clock output generated form System USB . */ 01375 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 01376 01377 /* USB clock source configuration done later after clock selection check */ 01378 break; 01379 01380 case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ 01381 01382 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 01383 01384 /* USB clock source configuration done later after clock selection check */ 01385 break; 01386 01387 case RCC_USBCLKSOURCE_HSI48: 01388 /* HSI48 oscillator is used as source of USB clock */ 01389 /* USB clock source configuration done later after clock selection check */ 01390 break; 01391 01392 default: 01393 ret = HAL_ERROR; 01394 break; 01395 } 01396 01397 if(ret == HAL_OK) 01398 { 01399 /* Set the source of USB clock*/ 01400 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 01401 } 01402 else 01403 { 01404 /* set overall return value */ 01405 status = ret; 01406 } 01407 01408 } 01409 01410 /*------------------------------------- SDMMC Configuration ------------------------------------*/ 01411 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 01412 { 01413 /* Check the parameters */ 01414 assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); 01415 01416 switch(PeriphClkInit->SdmmcClockSelection) 01417 { 01418 case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ 01419 /* Enable SDMMC Clock output generated form System PLL . */ 01420 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 01421 01422 /* SDMMC clock source configuration done later after clock selection check */ 01423 break; 01424 01425 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ 01426 01427 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 01428 01429 /* SDMMC clock source configuration done later after clock selection check */ 01430 break; 01431 01432 default: 01433 ret = HAL_ERROR; 01434 break; 01435 } 01436 01437 if(ret == HAL_OK) 01438 { 01439 /* Set the source of SDMMC clock*/ 01440 __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 01441 } 01442 else 01443 { 01444 /* set overall return value */ 01445 status = ret; 01446 } 01447 } 01448 01449 #if defined(LTDC) 01450 /*-------------------------------------- LTDC Configuration -----------------------------------*/ 01451 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 01452 { 01453 if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK) 01454 { 01455 status=HAL_ERROR; 01456 } 01457 } 01458 #endif /* LTDC */ 01459 01460 /*------------------------------ RNG Configuration -------------------------*/ 01461 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 01462 { 01463 01464 switch(PeriphClkInit->RngClockSelection) 01465 { 01466 case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ 01467 /* Enable RNG Clock output generated form System RNG . */ 01468 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 01469 01470 /* RNG clock source configuration done later after clock selection check */ 01471 break; 01472 01473 case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/ 01474 01475 /* RNG clock source configuration done later after clock selection check */ 01476 break; 01477 01478 case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/ 01479 01480 /* RNG clock source configuration done later after clock selection check */ 01481 break; 01482 case RCC_RNGCLKSOURCE_HSI48: 01483 /* HSI48 oscillator is used as source of RNG clock */ 01484 /* RNG clock source configuration done later after clock selection check */ 01485 break; 01486 01487 default: 01488 ret = HAL_ERROR; 01489 break; 01490 } 01491 01492 if(ret == HAL_OK) 01493 { 01494 /* Set the source of RNG clock*/ 01495 __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 01496 } 01497 else 01498 { 01499 /* set overall return value */ 01500 status = ret; 01501 } 01502 01503 } 01504 01505 /*------------------------------ SWPMI1 Configuration ------------------------*/ 01506 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 01507 { 01508 /* Check the parameters */ 01509 assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); 01510 01511 /* Configure the SWPMI1 interface clock source */ 01512 __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 01513 } 01514 #if defined(HRTIM1) 01515 /*------------------------------ HRTIM1 clock Configuration ----------------*/ 01516 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 01517 { 01518 /* Check the parameters */ 01519 assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); 01520 01521 /* Configure the HRTIM1 clock source */ 01522 __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 01523 } 01524 #endif /*HRTIM1*/ 01525 /*------------------------------ DFSDM1 Configuration ------------------------*/ 01526 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 01527 { 01528 /* Check the parameters */ 01529 assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); 01530 01531 /* Configure the DFSDM1 interface clock source */ 01532 __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 01533 } 01534 01535 #if defined(DFSDM2_BASE) 01536 /*------------------------------ DFSDM2 Configuration ------------------------*/ 01537 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) 01538 { 01539 /* Check the parameters */ 01540 assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); 01541 01542 /* Configure the DFSDM2 interface clock source */ 01543 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); 01544 } 01545 #endif /* DFSDM2 */ 01546 01547 /*------------------------------------ TIM configuration --------------------------------------*/ 01548 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 01549 { 01550 /* Check the parameters */ 01551 assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); 01552 01553 /* Configure Timer Prescaler */ 01554 __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 01555 } 01556 01557 /*------------------------------------ CKPER configuration --------------------------------------*/ 01558 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 01559 { 01560 /* Check the parameters */ 01561 assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); 01562 01563 /* Configure the CKPER clock source */ 01564 __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 01565 } 01566 01567 /*------------------------------ CEC Configuration ------------------------*/ 01568 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 01569 { 01570 /* Check the parameters */ 01571 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); 01572 01573 /* Configure the CEC interface clock source */ 01574 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 01575 } 01576 01577 if (status == HAL_OK) 01578 { 01579 return HAL_OK; 01580 } 01581 return HAL_ERROR; 01582 } 01583 01584 /** 01585 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. 01586 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 01587 * returns the configuration information for the Extended Peripherals clocks : 01588 * (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123, 01589 * USART234578, USART16, RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC. 01590 * SAI4A*, SAI4B*, SPI6, RTC, TIM). 01591 * @retval None 01592 * 01593 * (*) : Available on some STM32H7 lines only. 01594 */ 01595 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) 01596 { 01597 /* Set all possible values for the extended clock type parameter------------*/ 01598 PeriphClkInit->PeriphClockSelection = 01599 RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | 01600 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 | 01601 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | 01602 RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | 01603 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | 01604 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM | 01605 RCC_PERIPHCLK_CKPER; 01606 01607 #if defined(I2C5) 01608 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235; 01609 #else 01610 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123; 01611 #endif /*I2C5*/ 01612 #if defined(RCC_CDCCIP1R_SAI2ASEL) 01613 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A; 01614 #endif /* RCC_CDCCIP1R_SAI2ASEL */ 01615 #if defined(RCC_CDCCIP1R_SAI2BSEL) 01616 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B; 01617 #endif /* RCC_CDCCIP1R_SAI2BSEL */ 01618 #if defined(SAI3) 01619 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23; 01620 #endif /* SAI3 */ 01621 #if defined(SAI4) 01622 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A; 01623 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B; 01624 #endif /* SAI4 */ 01625 #if defined(DFSDM2_BASE) 01626 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2; 01627 #endif /* DFSDM2 */ 01628 #if defined(QUADSPI) 01629 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI; 01630 #endif /* QUADSPI */ 01631 #if defined(OCTOSPI1) || defined(OCTOSPI2) 01632 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI; 01633 #endif /* OCTOSPI1 || OCTOSPI2 */ 01634 #if defined(HRTIM1) 01635 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1; 01636 #endif /* HRTIM1 */ 01637 #if defined(LTDC) 01638 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC; 01639 #endif /* LTDC */ 01640 #if defined(DSI) 01641 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI; 01642 #endif /* DSI */ 01643 01644 /* Get the PLL3 Clock configuration -----------------------------------------------*/ 01645 PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos); 01646 PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ 1U; 01647 PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ 1U; 01648 PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ 1U; 01649 PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ 1U; 01650 PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos); 01651 PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos); 01652 01653 /* Get the PLL2 Clock configuration -----------------------------------------------*/ 01654 PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> RCC_PLLCKSELR_DIVM2_Pos); 01655 PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ 1U; 01656 PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ 1U; 01657 PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ 1U; 01658 PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ 1U; 01659 PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos); 01660 PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos); 01661 01662 /* Get the USART1 configuration --------------------------------------------*/ 01663 PeriphClkInit->Usart16ClockSelection = __HAL_RCC_GET_USART16_SOURCE(); 01664 /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/ 01665 PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE(); 01666 /* Get the LPUART1 clock source --------------------------------------------*/ 01667 PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); 01668 #if defined(I2C5) 01669 /* Get the I2C1/2/3/5 clock source -----------------------------------------*/ 01670 PeriphClkInit->I2c1235ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); 01671 #else 01672 /* Get the I2C1/2/3 clock source -------------------------------------------*/ 01673 PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); 01674 #endif /*I2C5*/ 01675 /* Get the LPTIM1 clock source ---------------------------------------------*/ 01676 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); 01677 /* Get the LPTIM2 clock source ---------------------------------------------*/ 01678 PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); 01679 /* Get the LPTIM3/4/5 clock source -----------------------------------------*/ 01680 PeriphClkInit->Lptim345ClockSelection = __HAL_RCC_GET_LPTIM345_SOURCE(); 01681 /* Get the SAI1 clock source -----------------------------------------------*/ 01682 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); 01683 #if defined(SAI3) 01684 /* Get the SAI2/3 clock source ---------------------------------------------*/ 01685 PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE(); 01686 #endif /*SAI3*/ 01687 #if defined(RCC_CDCCIP1R_SAI2ASEL_0) 01688 /* Get the SAI2A clock source ---------------------------------------------*/ 01689 PeriphClkInit->Sai2AClockSelection = __HAL_RCC_GET_SAI2A_SOURCE(); 01690 #endif /*SAI2A*/ 01691 #if defined(RCC_CDCCIP1R_SAI2BSEL_0) 01692 /* Get the SAI2B clock source ---------------------------------------------*/ 01693 PeriphClkInit->Sai2BClockSelection = __HAL_RCC_GET_SAI2B_SOURCE(); 01694 #endif /*SAI2B*/ 01695 #if defined(SAI4) 01696 /* Get the SAI4A clock source ----------------------------------------------*/ 01697 PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE(); 01698 /* Get the SAI4B clock source ----------------------------------------------*/ 01699 PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE(); 01700 #endif /*SAI4*/ 01701 /* Get the RTC clock source ------------------------------------------------*/ 01702 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); 01703 /* Get the USB clock source ------------------------------------------------*/ 01704 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); 01705 /* Get the SDMMC clock source ----------------------------------------------*/ 01706 PeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE(); 01707 /* Get the RNG clock source ------------------------------------------------*/ 01708 PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); 01709 #if defined(HRTIM1) 01710 /* Get the HRTIM1 clock source ---------------------------------------------*/ 01711 PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE(); 01712 #endif /* HRTIM1 */ 01713 /* Get the ADC clock source ------------------------------------------------*/ 01714 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); 01715 /* Get the SWPMI1 clock source ---------------------------------------------*/ 01716 PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE(); 01717 /* Get the DFSDM1 clock source ---------------------------------------------*/ 01718 PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); 01719 #if defined(DFSDM2_BASE) 01720 /* Get the DFSDM2 clock source ---------------------------------------------*/ 01721 PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); 01722 #endif /* DFSDM2 */ 01723 /* Get the SPDIFRX clock source --------------------------------------------*/ 01724 PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); 01725 /* Get the SPI1/2/3 clock source -------------------------------------------*/ 01726 PeriphClkInit->Spi123ClockSelection = __HAL_RCC_GET_SPI123_SOURCE(); 01727 /* Get the SPI4/5 clock source ---------------------------------------------*/ 01728 PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE(); 01729 /* Get the SPI6 clock source -----------------------------------------------*/ 01730 PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE(); 01731 /* Get the FDCAN clock source ----------------------------------------------*/ 01732 PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); 01733 /* Get the CEC clock source ------------------------------------------------*/ 01734 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); 01735 /* Get the FMC clock source ------------------------------------------------*/ 01736 PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE(); 01737 #if defined(QUADSPI) 01738 /* Get the QSPI clock source -----------------------------------------------*/ 01739 PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE(); 01740 #endif /* QUADSPI */ 01741 #if defined(OCTOSPI1) || defined(OCTOSPI2) 01742 /* Get the OSPI clock source -----------------------------------------------*/ 01743 PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); 01744 #endif /* OCTOSPI1 || OCTOSPI2 */ 01745 01746 #if defined(DSI) 01747 /* Get the DSI clock source ------------------------------------------------*/ 01748 PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); 01749 #endif /*DSI*/ 01750 01751 /* Get the CKPER clock source ----------------------------------------------*/ 01752 PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE(); 01753 01754 /* Get the TIM Prescaler configuration -------------------------------------*/ 01755 if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U) 01756 { 01757 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; 01758 } 01759 else 01760 { 01761 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; 01762 } 01763 } 01764 01765 /** 01766 * @brief Return the peripheral clock frequency for a given peripheral(SAI..) 01767 * @note Return 0 if peripheral clock identifier not managed by this API 01768 * @param PeriphClk: Peripheral clock identifier 01769 * This parameter can be one of the following values: 01770 * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock 01771 * @arg RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock (*) 01772 * @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*) 01773 * @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*) 01774 * @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*) 01775 * @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*) 01776 * @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock 01777 * @arg RCC_PERIPHCLK_ADC : ADC peripheral clock 01778 * @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock 01779 * @arg RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock 01780 * @retval Frequency in KHz 01781 * 01782 * (*) : Available on some STM32H7 lines only. 01783 */ 01784 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) 01785 { 01786 PLL1_ClocksTypeDef pll1_clocks; 01787 PLL2_ClocksTypeDef pll2_clocks; 01788 PLL3_ClocksTypeDef pll3_clocks; 01789 01790 /* This variable is used to store the clock frequency (value in Hz) */ 01791 uint32_t frequency; 01792 /* This variable is used to store the SAI and CKP clock source */ 01793 uint32_t saiclocksource; 01794 uint32_t ckpclocksource; 01795 uint32_t srcclk; 01796 01797 if (PeriphClk == RCC_PERIPHCLK_SAI1) 01798 { 01799 01800 saiclocksource= __HAL_RCC_GET_SAI1_SOURCE(); 01801 01802 switch (saiclocksource) 01803 { 01804 case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ 01805 { 01806 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 01807 { 01808 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 01809 frequency = pll1_clocks.PLL1_Q_Frequency; 01810 } 01811 else 01812 { 01813 frequency = 0; 01814 } 01815 break; 01816 } 01817 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ 01818 { 01819 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 01820 { 01821 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 01822 frequency = pll2_clocks.PLL2_P_Frequency; 01823 } 01824 else 01825 { 01826 frequency = 0; 01827 } 01828 break; 01829 } 01830 01831 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ 01832 { 01833 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 01834 { 01835 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 01836 frequency = pll3_clocks.PLL3_P_Frequency; 01837 } 01838 else 01839 { 01840 frequency = 0; 01841 } 01842 break; 01843 } 01844 01845 case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ 01846 { 01847 01848 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 01849 01850 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 01851 { 01852 /* In Case the CKPER Source is HSI */ 01853 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 01854 } 01855 01856 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 01857 { 01858 /* In Case the CKPER Source is CSI */ 01859 frequency = CSI_VALUE; 01860 } 01861 01862 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 01863 { 01864 /* In Case the CKPER Source is HSE */ 01865 frequency = HSE_VALUE; 01866 } 01867 01868 else 01869 { 01870 /* In Case the CKPER is disabled*/ 01871 frequency = 0; 01872 } 01873 01874 break; 01875 } 01876 01877 case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ 01878 { 01879 frequency = EXTERNAL_CLOCK_VALUE; 01880 break; 01881 } 01882 default : 01883 { 01884 frequency = 0; 01885 break; 01886 } 01887 } 01888 } 01889 01890 #if defined(SAI3) 01891 else if (PeriphClk == RCC_PERIPHCLK_SAI23) 01892 { 01893 01894 saiclocksource= __HAL_RCC_GET_SAI23_SOURCE(); 01895 01896 switch (saiclocksource) 01897 { 01898 case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ 01899 { 01900 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 01901 { 01902 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 01903 frequency = pll1_clocks.PLL1_Q_Frequency; 01904 } 01905 else 01906 { 01907 frequency = 0; 01908 } 01909 break; 01910 } 01911 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ 01912 { 01913 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 01914 { 01915 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 01916 frequency = pll2_clocks.PLL2_P_Frequency; 01917 } 01918 else 01919 { 01920 frequency = 0; 01921 } 01922 break; 01923 } 01924 01925 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ 01926 { 01927 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 01928 { 01929 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 01930 frequency = pll3_clocks.PLL3_P_Frequency; 01931 } 01932 else 01933 { 01934 frequency = 0; 01935 } 01936 break; 01937 } 01938 01939 case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ 01940 { 01941 01942 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 01943 01944 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 01945 { 01946 /* In Case the CKPER Source is HSI */ 01947 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 01948 } 01949 01950 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 01951 { 01952 /* In Case the CKPER Source is CSI */ 01953 frequency = CSI_VALUE; 01954 } 01955 01956 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 01957 { 01958 /* In Case the CKPER Source is HSE */ 01959 frequency = HSE_VALUE; 01960 } 01961 01962 else 01963 { 01964 /* In Case the CKPER is disabled*/ 01965 frequency = 0; 01966 } 01967 01968 break; 01969 } 01970 01971 case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ 01972 { 01973 frequency = EXTERNAL_CLOCK_VALUE; 01974 break; 01975 } 01976 default : 01977 { 01978 frequency = 0; 01979 break; 01980 } 01981 } 01982 } 01983 #endif /* SAI3 */ 01984 01985 #if defined(RCC_CDCCIP1R_SAI2ASEL) 01986 01987 else if (PeriphClk == RCC_PERIPHCLK_SAI2A) 01988 { 01989 saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE(); 01990 01991 switch (saiclocksource) 01992 { 01993 case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */ 01994 { 01995 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 01996 { 01997 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 01998 frequency = pll1_clocks.PLL1_Q_Frequency; 01999 } 02000 else 02001 { 02002 frequency = 0; 02003 } 02004 break; 02005 } 02006 case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */ 02007 { 02008 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 02009 { 02010 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 02011 frequency = pll2_clocks.PLL2_P_Frequency; 02012 } 02013 else 02014 { 02015 frequency = 0; 02016 } 02017 break; 02018 } 02019 02020 case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */ 02021 { 02022 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 02023 { 02024 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 02025 frequency = pll3_clocks.PLL3_P_Frequency; 02026 } 02027 else 02028 { 02029 frequency = 0; 02030 } 02031 break; 02032 } 02033 02034 case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A */ 02035 { 02036 02037 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 02038 02039 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 02040 { 02041 /* In Case the CKPER Source is HSI */ 02042 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 02043 } 02044 02045 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 02046 { 02047 /* In Case the CKPER Source is CSI */ 02048 frequency = CSI_VALUE; 02049 } 02050 02051 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 02052 { 02053 /* In Case the CKPER Source is HSE */ 02054 frequency = HSE_VALUE; 02055 } 02056 02057 else 02058 { 02059 /* In Case the CKPER is disabled*/ 02060 frequency = 0; 02061 } 02062 02063 break; 02064 } 02065 02066 case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */ 02067 { 02068 frequency = EXTERNAL_CLOCK_VALUE; 02069 break; 02070 } 02071 02072 default : 02073 { 02074 frequency = 0; 02075 break; 02076 } 02077 } 02078 02079 } 02080 #endif 02081 02082 #if defined(RCC_CDCCIP1R_SAI2BSEL_0) 02083 else if (PeriphClk == RCC_PERIPHCLK_SAI2B) 02084 { 02085 02086 saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE(); 02087 02088 switch (saiclocksource) 02089 { 02090 case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */ 02091 { 02092 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 02093 { 02094 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 02095 frequency = pll1_clocks.PLL1_Q_Frequency; 02096 } 02097 else 02098 { 02099 frequency = 0; 02100 } 02101 break; 02102 } 02103 case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */ 02104 { 02105 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 02106 { 02107 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 02108 frequency = pll2_clocks.PLL2_P_Frequency; 02109 } 02110 else 02111 { 02112 frequency = 0; 02113 } 02114 break; 02115 } 02116 02117 case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */ 02118 { 02119 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 02120 { 02121 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 02122 frequency = pll3_clocks.PLL3_P_Frequency; 02123 } 02124 else 02125 { 02126 frequency = 0; 02127 } 02128 break; 02129 } 02130 02131 case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/ 02132 { 02133 02134 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 02135 02136 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 02137 { 02138 /* In Case the CKPER Source is HSI */ 02139 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 02140 } 02141 02142 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 02143 { 02144 /* In Case the CKPER Source is CSI */ 02145 frequency = CSI_VALUE; 02146 } 02147 02148 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 02149 { 02150 /* In Case the CKPER Source is HSE */ 02151 frequency = HSE_VALUE; 02152 } 02153 02154 else 02155 { 02156 /* In Case the CKPER is disabled*/ 02157 frequency = 0; 02158 } 02159 break; 02160 } 02161 02162 case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */ 02163 { 02164 frequency = EXTERNAL_CLOCK_VALUE; 02165 break; 02166 } 02167 02168 default : 02169 { 02170 frequency = 0; 02171 break; 02172 } 02173 } 02174 } 02175 #endif 02176 02177 #if defined(SAI4) 02178 else if (PeriphClk == RCC_PERIPHCLK_SAI4A) 02179 { 02180 02181 saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE(); 02182 02183 switch (saiclocksource) 02184 { 02185 case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ 02186 { 02187 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 02188 { 02189 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 02190 frequency = pll1_clocks.PLL1_Q_Frequency; 02191 } 02192 else 02193 { 02194 frequency = 0; 02195 } 02196 break; 02197 } 02198 case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ 02199 { 02200 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 02201 { 02202 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 02203 frequency = pll2_clocks.PLL2_P_Frequency; 02204 } 02205 else 02206 { 02207 frequency = 0; 02208 } 02209 break; 02210 } 02211 02212 case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ 02213 { 02214 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 02215 { 02216 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 02217 frequency = pll3_clocks.PLL3_P_Frequency; 02218 } 02219 else 02220 { 02221 frequency = 0; 02222 } 02223 break; 02224 } 02225 02226 case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ 02227 { 02228 02229 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 02230 02231 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 02232 { 02233 /* In Case the CKPER Source is HSI */ 02234 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 02235 } 02236 02237 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 02238 { 02239 /* In Case the CKPER Source is CSI */ 02240 frequency = CSI_VALUE; 02241 } 02242 02243 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 02244 { 02245 /* In Case the CKPER Source is HSE */ 02246 frequency = HSE_VALUE; 02247 } 02248 02249 else 02250 { 02251 /* In Case the CKPER is disabled*/ 02252 frequency = 0; 02253 } 02254 02255 break; 02256 } 02257 02258 case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ 02259 { 02260 frequency = EXTERNAL_CLOCK_VALUE; 02261 break; 02262 } 02263 02264 default : 02265 { 02266 frequency = 0; 02267 break; 02268 } 02269 } 02270 } 02271 02272 else if (PeriphClk == RCC_PERIPHCLK_SAI4B) 02273 { 02274 02275 saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE(); 02276 02277 switch (saiclocksource) 02278 { 02279 case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ 02280 { 02281 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 02282 { 02283 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 02284 frequency = pll1_clocks.PLL1_Q_Frequency; 02285 } 02286 else 02287 { 02288 frequency = 0; 02289 } 02290 break; 02291 } 02292 case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ 02293 { 02294 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 02295 { 02296 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 02297 frequency = pll2_clocks.PLL2_P_Frequency; 02298 } 02299 else 02300 { 02301 frequency = 0; 02302 } 02303 break; 02304 } 02305 02306 case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ 02307 { 02308 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 02309 { 02310 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 02311 frequency = pll3_clocks.PLL3_P_Frequency; 02312 } 02313 else 02314 { 02315 frequency = 0; 02316 } 02317 break; 02318 } 02319 02320 case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ 02321 { 02322 02323 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 02324 02325 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 02326 { 02327 /* In Case the CKPER Source is HSI */ 02328 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 02329 } 02330 02331 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 02332 { 02333 /* In Case the CKPER Source is CSI */ 02334 frequency = CSI_VALUE; 02335 } 02336 02337 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 02338 { 02339 /* In Case the CKPER Source is HSE */ 02340 frequency = HSE_VALUE; 02341 } 02342 02343 else 02344 { 02345 /* In Case the CKPER is disabled*/ 02346 frequency = 0; 02347 } 02348 02349 break; 02350 } 02351 02352 case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ 02353 { 02354 frequency = EXTERNAL_CLOCK_VALUE; 02355 break; 02356 } 02357 02358 default : 02359 { 02360 frequency = 0; 02361 break; 02362 } 02363 } 02364 } 02365 #endif /*SAI4*/ 02366 else if (PeriphClk == RCC_PERIPHCLK_SPI123) 02367 { 02368 /* Get SPI1/2/3 clock source */ 02369 srcclk= __HAL_RCC_GET_SPI123_SOURCE(); 02370 02371 switch (srcclk) 02372 { 02373 case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ 02374 { 02375 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 02376 { 02377 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 02378 frequency = pll1_clocks.PLL1_Q_Frequency; 02379 } 02380 else 02381 { 02382 frequency = 0; 02383 } 02384 break; 02385 } 02386 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ 02387 { 02388 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 02389 { 02390 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 02391 frequency = pll2_clocks.PLL2_P_Frequency; 02392 } 02393 else 02394 { 02395 frequency = 0; 02396 } 02397 break; 02398 } 02399 02400 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ 02401 { 02402 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 02403 { 02404 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 02405 frequency = pll3_clocks.PLL3_P_Frequency; 02406 } 02407 else 02408 { 02409 frequency = 0; 02410 } 02411 break; 02412 } 02413 02414 case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ 02415 { 02416 02417 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 02418 02419 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 02420 { 02421 /* In Case the CKPER Source is HSI */ 02422 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 02423 } 02424 02425 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 02426 { 02427 /* In Case the CKPER Source is CSI */ 02428 frequency = CSI_VALUE; 02429 } 02430 02431 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 02432 { 02433 /* In Case the CKPER Source is HSE */ 02434 frequency = HSE_VALUE; 02435 } 02436 02437 else 02438 { 02439 /* In Case the CKPER is disabled*/ 02440 frequency = 0; 02441 } 02442 02443 break; 02444 } 02445 02446 case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ 02447 { 02448 frequency = EXTERNAL_CLOCK_VALUE; 02449 break; 02450 } 02451 default : 02452 { 02453 frequency = 0; 02454 break; 02455 } 02456 } 02457 } 02458 else if (PeriphClk == RCC_PERIPHCLK_ADC) 02459 { 02460 /* Get ADC clock source */ 02461 srcclk= __HAL_RCC_GET_ADC_SOURCE(); 02462 02463 switch (srcclk) 02464 { 02465 case RCC_ADCCLKSOURCE_PLL2: 02466 { 02467 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 02468 { 02469 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 02470 frequency = pll2_clocks.PLL2_P_Frequency; 02471 } 02472 else 02473 { 02474 frequency = 0; 02475 } 02476 break; 02477 } 02478 case RCC_ADCCLKSOURCE_PLL3: 02479 { 02480 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 02481 { 02482 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 02483 frequency = pll3_clocks.PLL3_R_Frequency; 02484 } 02485 else 02486 { 02487 frequency = 0; 02488 } 02489 break; 02490 } 02491 02492 case RCC_ADCCLKSOURCE_CLKP: 02493 { 02494 02495 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 02496 02497 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 02498 { 02499 /* In Case the CKPER Source is HSI */ 02500 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 02501 } 02502 02503 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 02504 { 02505 /* In Case the CKPER Source is CSI */ 02506 frequency = CSI_VALUE; 02507 } 02508 02509 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 02510 { 02511 /* In Case the CKPER Source is HSE */ 02512 frequency = HSE_VALUE; 02513 } 02514 02515 else 02516 { 02517 /* In Case the CKPER is disabled*/ 02518 frequency = 0; 02519 } 02520 02521 break; 02522 } 02523 02524 default : 02525 { 02526 frequency = 0; 02527 break; 02528 } 02529 } 02530 } 02531 else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 02532 { 02533 /* Get SDMMC clock source */ 02534 srcclk= __HAL_RCC_GET_SDMMC_SOURCE(); 02535 02536 switch (srcclk) 02537 { 02538 case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ 02539 { 02540 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 02541 { 02542 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 02543 frequency = pll1_clocks.PLL1_Q_Frequency; 02544 } 02545 else 02546 { 02547 frequency = 0; 02548 } 02549 break; 02550 } 02551 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ 02552 { 02553 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 02554 { 02555 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 02556 frequency = pll2_clocks.PLL2_R_Frequency; 02557 } 02558 else 02559 { 02560 frequency = 0; 02561 } 02562 break; 02563 } 02564 02565 default : 02566 { 02567 frequency = 0; 02568 break; 02569 } 02570 } 02571 } 02572 else if (PeriphClk == RCC_PERIPHCLK_SPI6) 02573 { 02574 /* Get SPI6 clock source */ 02575 srcclk= __HAL_RCC_GET_SPI6_SOURCE(); 02576 02577 switch (srcclk) 02578 { 02579 case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ 02580 { 02581 frequency = HAL_RCCEx_GetD3PCLK1Freq(); 02582 break; 02583 } 02584 case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ 02585 { 02586 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 02587 { 02588 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 02589 frequency = pll2_clocks.PLL2_Q_Frequency; 02590 } 02591 else 02592 { 02593 frequency = 0; 02594 } 02595 break; 02596 } 02597 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ 02598 { 02599 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 02600 { 02601 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 02602 frequency = pll3_clocks.PLL3_Q_Frequency; 02603 } 02604 else 02605 { 02606 frequency = 0; 02607 } 02608 break; 02609 } 02610 case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ 02611 { 02612 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 02613 { 02614 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 02615 } 02616 else 02617 { 02618 frequency = 0; 02619 } 02620 break; 02621 } 02622 case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ 02623 { 02624 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 02625 { 02626 frequency = CSI_VALUE; 02627 } 02628 else 02629 { 02630 frequency = 0; 02631 } 02632 break; 02633 } 02634 case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ 02635 { 02636 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 02637 { 02638 frequency = HSE_VALUE; 02639 } 02640 else 02641 { 02642 frequency = 0; 02643 } 02644 break; 02645 } 02646 #if defined(RCC_SPI6CLKSOURCE_PIN) 02647 case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */ 02648 { 02649 frequency = EXTERNAL_CLOCK_VALUE; 02650 break; 02651 } 02652 #endif /* RCC_SPI6CLKSOURCE_PIN */ 02653 default : 02654 { 02655 frequency = 0; 02656 break; 02657 } 02658 } 02659 } 02660 else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 02661 { 02662 /* Get FDCAN clock source */ 02663 srcclk= __HAL_RCC_GET_FDCAN_SOURCE(); 02664 02665 switch (srcclk) 02666 { 02667 case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ 02668 { 02669 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 02670 { 02671 frequency = HSE_VALUE; 02672 } 02673 else 02674 { 02675 frequency = 0; 02676 } 02677 break; 02678 } 02679 case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ 02680 { 02681 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 02682 { 02683 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 02684 frequency = pll1_clocks.PLL1_Q_Frequency; 02685 } 02686 else 02687 { 02688 frequency = 0; 02689 } 02690 break; 02691 } 02692 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ 02693 { 02694 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 02695 { 02696 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 02697 frequency = pll2_clocks.PLL2_Q_Frequency; 02698 } 02699 else 02700 { 02701 frequency = 0; 02702 } 02703 break; 02704 } 02705 default : 02706 { 02707 frequency = 0; 02708 break; 02709 } 02710 } 02711 } 02712 else 02713 { 02714 frequency = 0; 02715 } 02716 02717 return frequency; 02718 } 02719 02720 02721 /** 02722 * @brief Returns the D1PCLK1 frequency 02723 * @note Each time D1PCLK1 changes, this function must be called to update the 02724 * right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect. 02725 * @retval D1PCLK1 frequency 02726 */ 02727 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void) 02728 { 02729 #if defined(RCC_D1CFGR_D1PPRE) 02730 /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ 02731 return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU)); 02732 #else 02733 /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ 02734 return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)>> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU)); 02735 #endif 02736 } 02737 02738 /** 02739 * @brief Returns the D3PCLK1 frequency 02740 * @note Each time D3PCLK1 changes, this function must be called to update the 02741 * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. 02742 * @retval D3PCLK1 frequency 02743 */ 02744 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) 02745 { 02746 #if defined(RCC_D3CFGR_D3PPRE) 02747 /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ 02748 return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 02749 #else 02750 /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ 02751 return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); 02752 #endif 02753 } 02754 /** 02755 * @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency 02756 * @note The PLL2 clock frequencies computed by this function is not the real 02757 * frequency in the chip. It is calculated based on the predefined 02758 * constant and the selected clock source: 02759 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. 02760 * @note This function can be used by the user application to compute the 02761 * baud-rate for the communication peripherals or configure other parameters. 02762 * 02763 * @note Each time PLL2CLK changes, this function must be called to update the 02764 * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. 02765 * @param PLL2_Clocks structure. 02766 * @retval None 02767 */ 02768 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks) 02769 { 02770 uint32_t pllsource, pll2m, pll2fracen, hsivalue; 02771 float_t fracn2, pll2vco; 02772 02773 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N 02774 PLL2xCLK = PLL2_VCO / PLL2x 02775 */ 02776 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 02777 pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12); 02778 pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 02779 fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3)); 02780 02781 if (pll2m != 0U) 02782 { 02783 switch (pllsource) 02784 { 02785 02786 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ 02787 02788 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 02789 { 02790 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 02791 pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 02792 } 02793 else 02794 { 02795 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 02796 } 02797 break; 02798 02799 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ 02800 pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 02801 break; 02802 02803 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ 02804 pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 02805 break; 02806 02807 default: 02808 pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 02809 break; 02810 } 02811 PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9) + (float_t)1 )) ; 02812 PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ; 02813 PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ; 02814 } 02815 else 02816 { 02817 PLL2_Clocks->PLL2_P_Frequency = 0U; 02818 PLL2_Clocks->PLL2_Q_Frequency = 0U; 02819 PLL2_Clocks->PLL2_R_Frequency = 0U; 02820 } 02821 } 02822 02823 /** 02824 * @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency 02825 * @note The PLL3 clock frequencies computed by this function is not the real 02826 * frequency in the chip. It is calculated based on the predefined 02827 * constant and the selected clock source: 02828 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. 02829 * @note This function can be used by the user application to compute the 02830 * baud-rate for the communication peripherals or configure other parameters. 02831 * 02832 * @note Each time PLL3CLK changes, this function must be called to update the 02833 * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. 02834 * @param PLL3_Clocks structure. 02835 * @retval None 02836 */ 02837 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks) 02838 { 02839 uint32_t pllsource, pll3m, pll3fracen, hsivalue; 02840 float_t fracn3, pll3vco; 02841 02842 /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N 02843 PLL3xCLK = PLL3_VCO / PLLxR 02844 */ 02845 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 02846 pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20) ; 02847 pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 02848 fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3)); 02849 02850 if (pll3m != 0U) 02851 { 02852 switch (pllsource) 02853 { 02854 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ 02855 02856 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 02857 { 02858 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 02859 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 02860 } 02861 else 02862 { 02863 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 02864 } 02865 break; 02866 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ 02867 pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 02868 break; 02869 02870 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ 02871 pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 02872 break; 02873 02874 default: 02875 pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 02876 break; 02877 } 02878 PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9) + (float_t)1 )) ; 02879 PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ; 02880 PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ; 02881 } 02882 else 02883 { 02884 PLL3_Clocks->PLL3_P_Frequency = 0U; 02885 PLL3_Clocks->PLL3_Q_Frequency = 0U; 02886 PLL3_Clocks->PLL3_R_Frequency = 0U; 02887 } 02888 02889 } 02890 02891 /** 02892 * @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency 02893 * @note The PLL1 clock frequencies computed by this function is not the real 02894 * frequency in the chip. It is calculated based on the predefined 02895 * constant and the selected clock source: 02896 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. 02897 * @note This function can be used by the user application to compute the 02898 * baud-rate for the communication peripherals or configure other parameters. 02899 * 02900 * @note Each time PLL1CLK changes, this function must be called to update the 02901 * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. 02902 * @param PLL1_Clocks structure. 02903 * @retval None 02904 */ 02905 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks) 02906 { 02907 uint32_t pllsource, pll1m, pll1fracen, hsivalue; 02908 float_t fracn1, pll1vco; 02909 02910 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 02911 pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4); 02912 pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 02913 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); 02914 02915 if (pll1m != 0U) 02916 { 02917 switch (pllsource) 02918 { 02919 02920 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ 02921 02922 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 02923 { 02924 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 02925 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 02926 } 02927 else 02928 { 02929 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 02930 } 02931 break; 02932 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ 02933 pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 02934 break; 02935 02936 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ 02937 pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 02938 break; 02939 02940 default: 02941 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 02942 break; 02943 } 02944 02945 PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + (float_t)1 )) ; 02946 PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + (float_t)1 )) ; 02947 PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + (float_t)1 )) ; 02948 } 02949 else 02950 { 02951 PLL1_Clocks->PLL1_P_Frequency = 0U; 02952 PLL1_Clocks->PLL1_Q_Frequency = 0U; 02953 PLL1_Clocks->PLL1_R_Frequency = 0U; 02954 } 02955 02956 } 02957 02958 /** 02959 * @brief Returns the main System frequency 02960 * @note Each time System clock changes, this function must be called to update the 02961 * right core clock value. Otherwise, any configuration based on this function will be incorrect. 02962 * @note The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency 02963 * and updated within this function 02964 * @retval HCLK frequency 02965 */ 02966 uint32_t HAL_RCCEx_GetD1SysClockFreq(void) 02967 { 02968 uint32_t common_system_clock; 02969 02970 #if defined(RCC_D1CFGR_D1CPRE) 02971 common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 02972 #else 02973 common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); 02974 #endif 02975 02976 /* Update the SystemD2Clock global variable */ 02977 #if defined(RCC_D1CFGR_HPRE) 02978 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 02979 #else 02980 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); 02981 #endif 02982 02983 #if defined(DUAL_CORE) && defined(CORE_CM4) 02984 SystemCoreClock = SystemD2Clock; 02985 #else 02986 SystemCoreClock = common_system_clock; 02987 #endif /* DUAL_CORE && CORE_CM4 */ 02988 02989 return common_system_clock; 02990 } 02991 /** 02992 * @} 02993 */ 02994 02995 /** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions 02996 * @brief Extended Peripheral Control functions 02997 * @{ 02998 */ 02999 /** 03000 * @brief Enables the LSE Clock Security System. 03001 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled 03002 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC 03003 * clock with HAL_RCCEx_PeriphCLKConfig(). 03004 * @retval None 03005 */ 03006 void HAL_RCCEx_EnableLSECSS(void) 03007 { 03008 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; 03009 } 03010 03011 /** 03012 * @brief Disables the LSE Clock Security System. 03013 * @note LSE Clock Security System can only be disabled after a LSE failure detection. 03014 * @retval None 03015 */ 03016 void HAL_RCCEx_DisableLSECSS(void) 03017 { 03018 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; 03019 /* Disable LSE CSS IT if any */ 03020 __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); 03021 } 03022 03023 /** 03024 * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. 03025 * @note LSE Clock Security System Interrupt is mapped on EXTI line 18 03026 * @retval None 03027 */ 03028 void HAL_RCCEx_EnableLSECSS_IT(void) 03029 { 03030 /* Enable LSE CSS */ 03031 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; 03032 03033 /* Enable LSE CSS IT */ 03034 __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); 03035 03036 /* Enable IT on EXTI Line 18 */ 03037 #if defined(DUAL_CORE) && defined(CORE_CM4) 03038 __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT(); 03039 #else 03040 __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); 03041 #endif /* DUAL_CORE && CORE_CM4 */ 03042 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); 03043 } 03044 03045 /** 03046 * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock 03047 * @param WakeUpClk: Wakeup clock 03048 * This parameter can be one of the following values: 03049 * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection 03050 * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection 03051 * @note This function shall not be called after the Clock Security System on HSE has been 03052 * enabled. 03053 * @retval None 03054 */ 03055 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) 03056 { 03057 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); 03058 03059 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); 03060 } 03061 03062 /** 03063 * @brief Configure the oscillator Kernel clock source for wakeup from Stop 03064 * @param WakeUpClk: Kernel Wakeup clock 03065 * This parameter can be one of the following values: 03066 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection 03067 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection 03068 * @retval None 03069 */ 03070 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk) 03071 { 03072 assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk)); 03073 03074 __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk); 03075 } 03076 03077 #if defined(DUAL_CORE) 03078 /** 03079 * @brief Enable COREx boot independently of CMx_B option byte value 03080 * @param RCC_BootCx: Boot Core to be enabled 03081 * This parameter can be one of the following values: 03082 * @arg RCC_BOOT_C1: CM7 core selection 03083 * @arg RCC_BOOT_C2: CM4 core selection 03084 * @note This bit can be set by software but is cleared by hardware after a system reset or STANDBY 03085 * 03086 * @retval None 03087 */ 03088 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx) 03089 { 03090 assert_param(IS_RCC_BOOT_CORE(RCC_BootCx)); 03091 SET_BIT(RCC->GCR, RCC_BootCx) ; 03092 } 03093 03094 #endif /*DUAL_CORE*/ 03095 03096 #if defined(DUAL_CORE) 03097 /** 03098 * @brief Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs 03099 * @param RCC_WWDGx: WWDGx to be configured 03100 * This parameter can be one of the following values: 03101 * @arg RCC_WWDG1: WWDG1 generates system reset 03102 * @arg RCC_WWDG2: WWDG2 generates system reset 03103 * @note This bit can be set by software but is cleared by hardware during a system reset 03104 * 03105 * @retval None 03106 */ 03107 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) 03108 { 03109 assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); 03110 SET_BIT(RCC->GCR, RCC_WWDGx) ; 03111 } 03112 03113 #else 03114 #if defined(RCC_GCR_WW1RSC) 03115 /** 03116 * @brief Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs 03117 * @param RCC_WWDGx: WWDGx to be configured 03118 * This parameter can be one of the following values: 03119 * @arg RCC_WWDG1: WWDG1 generates system reset 03120 * @note This bit can be set by software but is cleared by hardware during a system reset 03121 * 03122 * @retval None 03123 */ 03124 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) 03125 { 03126 assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); 03127 SET_BIT(RCC->GCR, RCC_WWDGx) ; 03128 } 03129 #endif 03130 #endif /*DUAL_CORE*/ 03131 03132 /** 03133 * @} 03134 */ 03135 03136 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions 03137 * @brief Extended Clock Recovery System Control functions 03138 * 03139 @verbatim 03140 =============================================================================== 03141 ##### Extended Clock Recovery System Control functions ##### 03142 =============================================================================== 03143 [..] 03144 For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: 03145 03146 (#) In System clock config, HSI48 needs to be enabled 03147 03148 (#) Enable CRS clock in IP MSP init which will use CRS functions 03149 03150 (#) Call CRS functions as follows: 03151 (##) Prepare synchronization configuration necessary for HSI48 calibration 03152 (+++) Default values can be set for frequency Error Measurement (reload and error limit) 03153 and also HSI48 oscillator smooth trimming. 03154 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate 03155 directly reload value with target and synchronization frequencies values 03156 (##) Call function HAL_RCCEx_CRSConfig which 03157 (+++) Resets CRS registers to their default values. 03158 (+++) Configures CRS registers with synchronization configuration 03159 (+++) Enables automatic calibration and frequency error counter feature 03160 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the 03161 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be 03162 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock 03163 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs 03164 should be used as SYNC signal. 03165 03166 (##) A polling function is provided to wait for complete synchronization 03167 (+++) Call function HAL_RCCEx_CRSWaitSynchronization() 03168 (+++) According to CRS status, user can decide to adjust again the calibration or continue 03169 application if synchronization is OK 03170 03171 (#) User can retrieve information related to synchronization in calling function 03172 HAL_RCCEx_CRSGetSynchronizationInfo() 03173 03174 (#) Regarding synchronization status and synchronization information, user can try a new calibration 03175 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. 03176 Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value), 03177 it means that the actual frequency is lower than the target (and so, that the TRIM value should be 03178 incremented), while when it is detected during the up-counting phase it means that the actual frequency 03179 is higher (and that the TRIM value should be decremented). 03180 03181 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go 03182 through CRS Handler (CRS_IRQn/CRS_IRQHandler) 03183 (++) Call function HAL_RCCEx_CRSConfig() 03184 (++) Enable CRS_IRQn (thanks to NVIC functions) 03185 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) 03186 (++) Implement CRS status management in the following user callbacks called from 03187 HAL_RCCEx_CRS_IRQHandler(): 03188 (+++) HAL_RCCEx_CRS_SyncOkCallback() 03189 (+++) HAL_RCCEx_CRS_SyncWarnCallback() 03190 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() 03191 (+++) HAL_RCCEx_CRS_ErrorCallback() 03192 03193 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). 03194 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) 03195 03196 @endverbatim 03197 * @{ 03198 */ 03199 03200 /** 03201 * @brief Start automatic synchronization for polling mode 03202 * @param pInit Pointer on RCC_CRSInitTypeDef structure 03203 * @retval None 03204 */ 03205 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) 03206 { 03207 uint32_t value; 03208 03209 /* Check the parameters */ 03210 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); 03211 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); 03212 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); 03213 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); 03214 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); 03215 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); 03216 03217 /* CONFIGURATION */ 03218 03219 /* Before configuration, reset CRS registers to their default values*/ 03220 __HAL_RCC_CRS_FORCE_RESET(); 03221 __HAL_RCC_CRS_RELEASE_RESET(); 03222 03223 /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */ 03224 /* Set the SYNCSRC[1:0] bits according to Source value */ 03225 /* Set the SYNCSPOL bit according to Polarity value */ 03226 if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2)) 03227 { 03228 /* Use Rev.Y value of USB2 */ 03229 value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity); 03230 } 03231 else 03232 { 03233 value = (pInit->Prescaler | pInit->Source | pInit->Polarity); 03234 } 03235 /* Set the RELOAD[15:0] bits according to ReloadValue value */ 03236 value |= pInit->ReloadValue; 03237 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ 03238 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); 03239 WRITE_REG(CRS->CFGR, value); 03240 03241 /* Adjust HSI48 oscillator smooth trimming */ 03242 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ 03243 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); 03244 03245 /* START AUTOMATIC SYNCHRONIZATION*/ 03246 03247 /* Enable Automatic trimming & Frequency error counter */ 03248 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); 03249 } 03250 03251 /** 03252 * @brief Generate the software synchronization event 03253 * @retval None 03254 */ 03255 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) 03256 { 03257 SET_BIT(CRS->CR, CRS_CR_SWSYNC); 03258 } 03259 03260 /** 03261 * @brief Return synchronization info 03262 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure 03263 * @retval None 03264 */ 03265 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) 03266 { 03267 /* Check the parameter */ 03268 assert_param(pSynchroInfo != (void *)NULL); 03269 03270 /* Get the reload value */ 03271 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); 03272 03273 /* Get HSI48 oscillator smooth trimming */ 03274 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); 03275 03276 /* Get Frequency error capture */ 03277 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); 03278 03279 /* Get Frequency error direction */ 03280 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); 03281 } 03282 03283 /** 03284 * @brief Wait for CRS Synchronization status. 03285 * @param Timeout Duration of the time-out 03286 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization 03287 * frequency. 03288 * @note If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. 03289 * @retval Combination of Synchronization status 03290 * This parameter can be a combination of the following values: 03291 * @arg @ref RCC_CRS_TIMEOUT 03292 * @arg @ref RCC_CRS_SYNCOK 03293 * @arg @ref RCC_CRS_SYNCWARN 03294 * @arg @ref RCC_CRS_SYNCERR 03295 * @arg @ref RCC_CRS_SYNCMISS 03296 * @arg @ref RCC_CRS_TRIMOVF 03297 */ 03298 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) 03299 { 03300 uint32_t crsstatus = RCC_CRS_NONE; 03301 uint32_t tickstart; 03302 03303 /* Get time-out */ 03304 tickstart = HAL_GetTick(); 03305 03306 /* Wait for CRS flag or time-out detection */ 03307 do 03308 { 03309 if(Timeout != HAL_MAX_DELAY) 03310 { 03311 if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) 03312 { 03313 crsstatus = RCC_CRS_TIMEOUT; 03314 } 03315 } 03316 /* Check CRS SYNCOK flag */ 03317 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) 03318 { 03319 /* CRS SYNC event OK */ 03320 crsstatus |= RCC_CRS_SYNCOK; 03321 03322 /* Clear CRS SYNC event OK bit */ 03323 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); 03324 } 03325 03326 /* Check CRS SYNCWARN flag */ 03327 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) 03328 { 03329 /* CRS SYNC warning */ 03330 crsstatus |= RCC_CRS_SYNCWARN; 03331 03332 /* Clear CRS SYNCWARN bit */ 03333 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); 03334 } 03335 03336 /* Check CRS TRIM overflow flag */ 03337 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) 03338 { 03339 /* CRS SYNC Error */ 03340 crsstatus |= RCC_CRS_TRIMOVF; 03341 03342 /* Clear CRS Error bit */ 03343 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); 03344 } 03345 03346 /* Check CRS Error flag */ 03347 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) 03348 { 03349 /* CRS SYNC Error */ 03350 crsstatus |= RCC_CRS_SYNCERR; 03351 03352 /* Clear CRS Error bit */ 03353 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); 03354 } 03355 03356 /* Check CRS SYNC Missed flag */ 03357 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) 03358 { 03359 /* CRS SYNC Missed */ 03360 crsstatus |= RCC_CRS_SYNCMISS; 03361 03362 /* Clear CRS SYNC Missed bit */ 03363 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); 03364 } 03365 03366 /* Check CRS Expected SYNC flag */ 03367 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) 03368 { 03369 /* frequency error counter reached a zero value */ 03370 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); 03371 } 03372 } while(RCC_CRS_NONE == crsstatus); 03373 03374 return crsstatus; 03375 } 03376 03377 /** 03378 * @brief Handle the Clock Recovery System interrupt request. 03379 * @retval None 03380 */ 03381 void HAL_RCCEx_CRS_IRQHandler(void) 03382 { 03383 uint32_t crserror = RCC_CRS_NONE; 03384 /* Get current IT flags and IT sources values */ 03385 uint32_t itflags = READ_REG(CRS->ISR); 03386 uint32_t itsources = READ_REG(CRS->CR); 03387 03388 /* Check CRS SYNCOK flag */ 03389 if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) 03390 { 03391 /* Clear CRS SYNC event OK flag */ 03392 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); 03393 03394 /* user callback */ 03395 HAL_RCCEx_CRS_SyncOkCallback(); 03396 } 03397 /* Check CRS SYNCWARN flag */ 03398 else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) 03399 { 03400 /* Clear CRS SYNCWARN flag */ 03401 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); 03402 03403 /* user callback */ 03404 HAL_RCCEx_CRS_SyncWarnCallback(); 03405 } 03406 /* Check CRS Expected SYNC flag */ 03407 else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) 03408 { 03409 /* frequency error counter reached a zero value */ 03410 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); 03411 03412 /* user callback */ 03413 HAL_RCCEx_CRS_ExpectedSyncCallback(); 03414 } 03415 /* Check CRS Error flags */ 03416 else 03417 { 03418 if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) 03419 { 03420 if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) 03421 { 03422 crserror |= RCC_CRS_SYNCERR; 03423 } 03424 if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) 03425 { 03426 crserror |= RCC_CRS_SYNCMISS; 03427 } 03428 if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) 03429 { 03430 crserror |= RCC_CRS_TRIMOVF; 03431 } 03432 03433 /* Clear CRS Error flags */ 03434 WRITE_REG(CRS->ICR, CRS_ICR_ERRC); 03435 03436 /* user error callback */ 03437 HAL_RCCEx_CRS_ErrorCallback(crserror); 03438 } 03439 } 03440 } 03441 03442 /** 03443 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. 03444 * @retval none 03445 */ 03446 __weak void HAL_RCCEx_CRS_SyncOkCallback(void) 03447 { 03448 /* NOTE : This function should not be modified, when the callback is needed, 03449 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file 03450 */ 03451 } 03452 03453 /** 03454 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. 03455 * @retval none 03456 */ 03457 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void) 03458 { 03459 /* NOTE : This function should not be modified, when the callback is needed, 03460 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file 03461 */ 03462 } 03463 03464 /** 03465 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. 03466 * @retval none 03467 */ 03468 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) 03469 { 03470 /* NOTE : This function should not be modified, when the callback is needed, 03471 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file 03472 */ 03473 } 03474 03475 /** 03476 * @brief RCCEx Clock Recovery System Error interrupt callback. 03477 * @param Error Combination of Error status. 03478 * This parameter can be a combination of the following values: 03479 * @arg @ref RCC_CRS_SYNCERR 03480 * @arg @ref RCC_CRS_SYNCMISS 03481 * @arg @ref RCC_CRS_TRIMOVF 03482 * @retval none 03483 */ 03484 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) 03485 { 03486 /* Prevent unused argument(s) compilation warning */ 03487 UNUSED(Error); 03488 03489 /* NOTE : This function should not be modified, when the callback is needed, 03490 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file 03491 */ 03492 } 03493 03494 03495 /** 03496 * @} 03497 */ 03498 03499 /** 03500 * @} 03501 */ 03502 03503 /** @defgroup RCCEx_Private_functions RCCEx Private Functions 03504 * @{ 03505 */ 03506 /** 03507 * @brief Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it 03508 * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that 03509 * contains the configuration parameters as well as VCI, VCO clock ranges. 03510 * @param Divider divider parameter to be updated 03511 * @note PLL2 is temporary disabled to apply new parameters 03512 * 03513 * @retval HAL status 03514 */ 03515 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) 03516 { 03517 03518 uint32_t tickstart; 03519 HAL_StatusTypeDef status = HAL_OK; 03520 assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M)); 03521 assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N)); 03522 assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P)); 03523 assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R)); 03524 assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q)); 03525 assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); 03526 assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); 03527 assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); 03528 03529 /* Check that PLL2 OSC clock source is already set */ 03530 if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 03531 { 03532 return HAL_ERROR; 03533 } 03534 03535 03536 else 03537 { 03538 /* Disable PLL2. */ 03539 __HAL_RCC_PLL2_DISABLE(); 03540 03541 /* Get Start Tick*/ 03542 tickstart = HAL_GetTick(); 03543 03544 /* Wait till PLL is disabled */ 03545 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 03546 { 03547 if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 03548 { 03549 return HAL_TIMEOUT; 03550 } 03551 } 03552 03553 /* Configure PLL2 multiplication and division factors. */ 03554 __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 03555 pll2->PLL2N, 03556 pll2->PLL2P, 03557 pll2->PLL2Q, 03558 pll2->PLL2R); 03559 03560 /* Select PLL2 input reference frequency range: VCI */ 03561 __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 03562 03563 /* Select PLL2 output frequency range : VCO */ 03564 __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 03565 03566 /* Disable PLL2FRACN . */ 03567 __HAL_RCC_PLL2FRACN_DISABLE(); 03568 03569 /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ 03570 __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 03571 03572 /* Enable PLL2FRACN . */ 03573 __HAL_RCC_PLL2FRACN_ENABLE(); 03574 03575 /* Enable the PLL2 clock output */ 03576 if(Divider == DIVIDER_P_UPDATE) 03577 { 03578 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 03579 } 03580 else if(Divider == DIVIDER_Q_UPDATE) 03581 { 03582 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 03583 } 03584 else 03585 { 03586 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 03587 } 03588 03589 /* Enable PLL2. */ 03590 __HAL_RCC_PLL2_ENABLE(); 03591 03592 /* Get Start Tick*/ 03593 tickstart = HAL_GetTick(); 03594 03595 /* Wait till PLL2 is ready */ 03596 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 03597 { 03598 if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 03599 { 03600 return HAL_TIMEOUT; 03601 } 03602 } 03603 03604 } 03605 03606 03607 return status; 03608 } 03609 03610 03611 /** 03612 * @brief Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it 03613 * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that 03614 * contains the configuration parameters as well as VCI, VCO clock ranges. 03615 * @param Divider divider parameter to be updated 03616 * @note PLL3 is temporary disabled to apply new parameters 03617 * 03618 * @retval HAL status 03619 */ 03620 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) 03621 { 03622 uint32_t tickstart; 03623 HAL_StatusTypeDef status = HAL_OK; 03624 assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M)); 03625 assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N)); 03626 assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P)); 03627 assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R)); 03628 assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q)); 03629 assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); 03630 assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); 03631 assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); 03632 03633 /* Check that PLL3 OSC clock source is already set */ 03634 if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 03635 { 03636 return HAL_ERROR; 03637 } 03638 03639 03640 else 03641 { 03642 /* Disable PLL3. */ 03643 __HAL_RCC_PLL3_DISABLE(); 03644 03645 /* Get Start Tick*/ 03646 tickstart = HAL_GetTick(); 03647 /* Wait till PLL3 is ready */ 03648 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 03649 { 03650 if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) 03651 { 03652 return HAL_TIMEOUT; 03653 } 03654 } 03655 03656 /* Configure the PLL3 multiplication and division factors. */ 03657 __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 03658 pll3->PLL3N, 03659 pll3->PLL3P, 03660 pll3->PLL3Q, 03661 pll3->PLL3R); 03662 03663 /* Select PLL3 input reference frequency range: VCI */ 03664 __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 03665 03666 /* Select PLL3 output frequency range : VCO */ 03667 __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 03668 03669 /* Disable PLL3FRACN . */ 03670 __HAL_RCC_PLL3FRACN_DISABLE(); 03671 03672 /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ 03673 __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 03674 03675 /* Enable PLL3FRACN . */ 03676 __HAL_RCC_PLL3FRACN_ENABLE(); 03677 03678 /* Enable the PLL3 clock output */ 03679 if(Divider == DIVIDER_P_UPDATE) 03680 { 03681 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 03682 } 03683 else if(Divider == DIVIDER_Q_UPDATE) 03684 { 03685 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 03686 } 03687 else 03688 { 03689 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 03690 } 03691 03692 /* Enable PLL3. */ 03693 __HAL_RCC_PLL3_ENABLE(); 03694 03695 /* Get Start Tick*/ 03696 tickstart = HAL_GetTick(); 03697 03698 /* Wait till PLL3 is ready */ 03699 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 03700 { 03701 if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) 03702 { 03703 return HAL_TIMEOUT; 03704 } 03705 } 03706 03707 } 03708 03709 03710 return status; 03711 } 03712 03713 /** 03714 * @brief Handle the RCC LSE Clock Security System interrupt request. 03715 * @retval None 03716 */ 03717 void HAL_RCCEx_LSECSS_IRQHandler(void) 03718 { 03719 /* Check RCC LSE CSSF flag */ 03720 if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) 03721 { 03722 03723 /* Clear RCC LSE CSS pending bit */ 03724 __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); 03725 03726 /* RCC LSE Clock Security System interrupt user callback */ 03727 HAL_RCCEx_LSECSS_Callback(); 03728 03729 } 03730 } 03731 03732 /** 03733 * @brief RCCEx LSE Clock Security System interrupt callback. 03734 * @retval none 03735 */ 03736 __weak void HAL_RCCEx_LSECSS_Callback(void) 03737 { 03738 /* NOTE : This function should not be modified, when the callback is needed, 03739 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file 03740 */ 03741 } 03742 03743 03744 03745 /** 03746 * @} 03747 */ 03748 03749 #endif /* HAL_RCC_MODULE_ENABLED */ 03750 /** 03751 * @} 03752 */ 03753 03754 /** 03755 * @} 03756 */ 03757
1.7.6.1