Modules
	RCCEx CRS Extended Features
Defines
#define	__HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)
	Macros to enable or disable PLL2.
#define	__HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
#define	__HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
	Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
#define	__HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
#define	__HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
	Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.
#define	__HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
#define	__HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__)
	Macro to configures the PLL2 multiplication and division factors.
#define	__HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))
	Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.
#define	__HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
	Macro to select the PLL2 reference frequency range.
#define	__HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
	Macro to select the PLL2 reference frequency range.
#define	__HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)
	Macros to enable or disable the main PLL3.
#define	__HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
#define	__HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
	Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.
#define	__HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
#define	__HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
	Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
#define	__HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
#define	__HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__)
	Macro to configures the PLL3 multiplication and division factors.
#define	__HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
	Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.
#define	__HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
	Macro to select the PLL3 reference frequency range.
#define	__HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
	Macro to select the PLL3 reference frequency range.
#define	__HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
	Macro to Configure the SAI1 clock source.
#define	__HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
	Macro to get the SAI1 clock source.
#define	__HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
	Macro to Configure the SPDIFRX clock source.
#define	__HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
	Macro to get the SPDIFRX clock source.
#define	__HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
	Macro to Configure the SAI4A clock source.
#define	__HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
	Macro to get the SAI4A clock source.
#define	__HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
	Macro to Configure the SAI4B clock source.
#define	__HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
	Macro to get the SAI4B clock source.
#define	__HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__))
	macro to configure the I2C1/2/3/5* clock (I2C123CLK).
#define	__HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG
#define	__HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL)))
	macro to get the I2C1/2/3/5* clock source.
#define	__HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
#define	__HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG
	macro to configure the I2C1 clock (I2C1CLK).
#define	__HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
	macro to get the I2C1 clock source.
#define	__HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG
	macro to configure the I2C2 clock (I2C2CLK).
#define	__HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
	macro to get the I2C2 clock source.
#define	__HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG
	macro to configure the I2C3 clock (I2C3CLK).
#define	__HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
	macro to get the I2C3 clock source.
#define	__HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
	macro to configure the I2C4 clock (I2C4CLK).
#define	__HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
	macro to get the I2C4 clock source.
#define	__HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG
	macro to configure the I2C5 clock (I2C5CLK).
#define	__HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
	macro to get the I2C5 clock source.
#define	__HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
	macro to configure the USART1/6/9* /10* clock (USART16CLK).
#define	__HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG
#define	__HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL)))
	macro to get the USART1/6/9* /10* clock source.
#define	__HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE
#define	__HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))
	macro to configure the USART234578 clock (USART234578CLK).
#define	__HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
	macro to get the USART2/3/4/5/7/8 clock source.
#define	__HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG
	macro to configure the USART1 clock (USART1CLK).
#define	__HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE
	macro to get the USART1 clock source.
#define	__HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG
	macro to configure the USART2 clock (USART2CLK).
#define	__HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE
	macro to get the USART2 clock source.
#define	__HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG
	macro to configure the USART3 clock (USART3CLK).
#define	__HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE
	macro to get the USART3 clock source.
#define	__HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG
	macro to configure the UART4 clock (UART4CLK).
#define	__HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE
	macro to get the UART4 clock source.
#define	__HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG
	macro to configure the UART5 clock (UART5CLK).
#define	__HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE
	macro to get the UART5 clock source.
#define	__HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG
	macro to configure the USART6 clock (USART6CLK).
#define	__HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE
	macro to get the USART6 clock source.
#define	__HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG
	macro to configure the UART5 clock (UART7CLK).
#define	__HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE
	macro to get the UART7 clock source.
#define	__HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG
	macro to configure the UART8 clock (UART8CLK).
#define	__HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE
	macro to get the UART8 clock source.
#define	__HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG
	macro to configure the UART9 clock (UART9CLK).
#define	__HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE
	macro to get the UART9 clock source.
#define	__HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG
	macro to configure the USART10 clock (USART10CLK).
#define	__HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE
	macro to get the USART10 clock source.
#define	__HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
	macro to configure the LPUART1 clock (LPUART1CLK).
#define	__HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
	macro to get the LPUART1 clock source.
#define	__HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
	macro to configure the LPTIM1 clock source.
#define	__HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
	macro to get the LPTIM1 clock source.
#define	__HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
	macro to configure the LPTIM2 clock source.
#define	__HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
	macro to get the LPTIM2 clock source.
#define	__HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
	macro to configure the LPTIM3/4/5 clock source.
#define	__HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
	macro to get the LPTIM3/4/5 clock source.
#define	__HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG
	macro to configure the LPTIM3 clock source.
#define	__HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
	macro to get the LPTIM3 clock source.
#define	__HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG
	macro to configure the LPTIM4 clock source.
#define	__HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
	macro to get the LPTIM4 clock source.
#define	__HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG
	macro to configure the LPTIM5 clock source.
#define	__HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
	macro to get the LPTIM5 clock source.
#define	__HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
	macro to configure the OSPI clock source.
#define	__HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL)))
	macro to get the OSPI clock source.
#define	__HAL_RCC_FMC_CONFIG(__FMCCLKSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
	macro to configure the FMC clock source.
#define	__HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
	macro to get the FMC clock source.
#define	__HAL_RCC_USB_CONFIG(__USBCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
	Macro to configure the USB clock (USBCLK).
#define	__HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
	Macro to get the USB clock source.
#define	__HAL_RCC_ADC_CONFIG(__ADCCLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
	Macro to configure the ADC clock.
#define	__HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
	Macro to get the ADC clock source.
#define	__HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
	Macro to configure the SWPMI1 clock.
#define	__HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
	Macro to get the SWPMI1 clock source.
#define	__HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
	Macro to configure the DFSDM1 clock.
#define	__HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
	Macro to get the DFSDM1 clock source.
#define	__HAL_RCC_CEC_CONFIG(__CECCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
	macro to configure the CEC clock (CECCLK).
#define	__HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
	macro to get the CEC clock source.
#define	__HAL_RCC_CLKP_CONFIG(__CLKPSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
	Macro to configure the CLKP : Oscillator clock for peripheral.
#define	__HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
	Macro to get the Oscillator clock for peripheral source.
#define	__HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
	Macro to configure the FDCAN clock.
#define	__HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
	Macro to get the FDCAN clock.
#define	__HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
	Macro to Configure the SPI1/2/3 clock source.
#define	__HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
	Macro to get the SPI1/2/3 clock source.
#define	__HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG
	Macro to Configure the SPI1 clock source.
#define	__HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE
	Macro to get the SPI1 clock source.
#define	__HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG
	Macro to Configure the SPI2 clock source.
#define	__HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE
	Macro to get the SPI2 clock source.
#define	__HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG
	Macro to Configure the SPI3 clock source.
#define	__HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE
	Macro to get the SPI3 clock source.
#define	__HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
	Macro to Configure the SPI4/5 clock source.
#define	__HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
	Macro to get the SPI4/5 clock source.
#define	__HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG
	Macro to Configure the SPI4 clock source.
#define	__HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE
	Macro to get the SPI4 clock source.
#define	__HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG
	Macro to Configure the SPI5 clock source.
#define	__HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE
	Macro to get the SPI5 clock source.
#define	__HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
	Macro to Configure the SPI6 clock source.
#define	__HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
	Macro to get the SPI6 clock source.
#define	__HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
	Macro to configure the SDMMC clock.
#define	__HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
	Macro to get the SDMMC clock.
#define	__HAL_RCC_RNG_CONFIG(__RNGCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
	macro to configure the RNG clock (RNGCLK).
#define	__HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
	macro to get the RNG clock source.
#define	__HAL_RCC_TIMCLKPRESCALER(__PRESC__)
	Macro to configure the Timers clocks prescalers.
#define	__HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
	Enable the RCC LSE CSS Extended Interrupt Line.
#define	__HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
	Disable the RCC LSE CSS Extended Interrupt Line.
#define	__HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
	Enable the RCC LSE CSS Event Line.
#define	__HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
	Disable the RCC LSE CSS Event Line.
#define	__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
	Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define	__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
	Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define	__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
	Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define	__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
	Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define	__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()
	Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define	__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()
	Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define	__HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
	Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
#define	__HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
	Clear the RCC LSE CSS EXTI flag.
#define	__HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
	Generate a Software interrupt on the RCC LSE CSS EXTI line.
#define	__HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
	Enable the specified CRS interrupts.
#define	__HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
	Disable the specified CRS interrupts.
#define	__HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
	Check whether the CRS interrupt has occurred or not.
#define	RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
	Clear the CRS interrupt pending bits.
#define	__HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)
#define	__HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
	Check whether the specified CRS flag is set or not.
#define	RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
	Clear the CRS specified FLAG.
#define	__HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)

Define Documentation

#define __HAL_RCC_ADC_CONFIG ( __ADCCLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))

Macro to configure the ADC clock.

Parameters:

__ADCCLKSource__

specifies the ADC digital interface clock source. This parameter can be one of the following values:

RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock

Definition at line 3111 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_CEC_CONFIG ( __CECCLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))

macro to configure the CEC clock (CECCLK).

Parameters:

__CECCLKSource__

specifies the CEC clock source. This parameter can be one of the following values:

RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock

Definition at line 3207 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_CLKP_CONFIG ( __CLKPSource__ ) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))

Macro to configure the CLKP : Oscillator clock for peripheral.

Parameters:

__CLKPSource__

specifies Oscillator clock for peripheral This parameter can be one of the following values:

RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral

Definition at line 3234 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_CRS_CLEAR_FLAG ( __FLAG__ )

Value:

do { \
                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
                                                 { \
                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
                                                 } \
                                                 else \
                                                 { \
                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \
                                                 } \
                                               } while(0)

Definition at line 3823 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define __HAL_RCC_CRS_CLEAR_IT ( __INTERRUPT__ )

Value:

do { \
                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
                                                 { \
                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
                                                 } \
                                                 else \
                                                 { \
                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
                                                 } \
                                               } while(0)

Definition at line 3779 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(CRS->CR, (__INTERRUPT__))

Disable the specified CRS interrupts.

Parameters:

__INTERRUPT__

specifies the CRS interrupt sources to be disabled. This parameter can be any combination of the following values:

RCC_CRS_IT_SYNCOK SYNC event OK interrupt
RCC_CRS_IT_SYNCWARN SYNC warning interrupt
RCC_CRS_IT_ERR Synchronization or trimming error interrupt
RCC_CRS_IT_ESYNC Expected SYNC interrupt

Return values:

None

Definition at line 3752 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(CRS->CR, (__INTERRUPT__))

Enable the specified CRS interrupts.

Parameters:

__INTERRUPT__

specifies the CRS interrupt sources to be enabled. This parameter can be any combination of the following values:

RCC_CRS_IT_SYNCOK SYNC event OK interrupt
RCC_CRS_IT_SYNCWARN SYNC warning interrupt
RCC_CRS_IT_ERR Synchronization or trimming error interrupt
RCC_CRS_IT_ESYNC Expected SYNC interrupt

Return values:

None

Definition at line 3740 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_GET_FLAG ( __FLAG__ ) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))

Check whether the specified CRS flag is set or not.

Parameters:

__FLAG__

specifies the flag to check. This parameter can be one of the following values:

RCC_CRS_FLAG_SYNCOK SYNC event OK
RCC_CRS_FLAG_SYNCWARN SYNC warning
RCC_CRS_FLAG_ERR Error
RCC_CRS_FLAG_ESYNC Expected SYNC
RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
RCC_CRS_FLAG_SYNCERR SYNC error
RCC_CRS_FLAG_SYNCMISS SYNC missed

Return values:

The	new state of _FLAG_ (TRUE or FALSE).

Definition at line 3803 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define __HAL_RCC_CRS_GET_IT_SOURCE ( __INTERRUPT__ ) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)

Check whether the CRS interrupt has occurred or not.

Parameters:

__INTERRUPT__

specifies the CRS interrupt source to check. This parameter can be one of the following values:

RCC_CRS_IT_SYNCOK SYNC event OK interrupt
RCC_CRS_IT_SYNCWARN SYNC warning interrupt
RCC_CRS_IT_ERR Synchronization or trimming error interrupt
RCC_CRS_IT_ESYNC Expected SYNC interrupt

Return values:

The	new state of __INTERRUPT__ (SET or RESET).

Definition at line 3763 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_DFSDM1_CONFIG ( __DFSDM1CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))

Macro to configure the DFSDM1 clock.

Parameters:

__DFSDM1CLKSource__

specifies the DFSDM1 clock source. This parameter can be one of the following values:

RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock

Definition at line 3162 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_FDCAN_CONFIG ( __FDCANCLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))

Macro to configure the FDCAN clock.

Parameters:

__FDCANCLKSource__

specifies clock source for FDCAN This parameter can be one of the following values:

RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock

Definition at line 3262 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_FMC_CONFIG ( __FMCCLKSource__ ) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))

macro to configure the FMC clock source.

Parameters:

__FMCCLKSource__

specifies the FMC clock source.

RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock

Definition at line 3056 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_ADC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))

Macro to get the ADC clock source.

Return values:

The	clock source can be one of the following values: RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock

Definition at line 3125 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_CEC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))

macro to get the CEC clock source.

Return values:

The	clock source can be one of the following values: RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock

Definition at line 3221 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_CLKP_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))

Macro to get the Oscillator clock for peripheral source.

Return values:

The	clock source can be one of the following values: RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral

Definition at line 3248 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_DFSDM1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))

Macro to get the DFSDM1 clock source.

Return values:

The	clock source can be one of the following values: RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock

Definition at line 3175 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_FDCAN_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))

Macro to get the FDCAN clock.

Return values:

The	clock source can be one of the following values: RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock

Definition at line 3276 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_FMC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))

macro to get the FMC clock source.

Return values:

The

clock source can be one of the following values:

RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock

Definition at line 3071 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C1235_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL)))

macro to get the I2C1/2/3/5* clock source.

Return values:

The

clock source can be one of the following values:

RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock
RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock
RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock
RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock

(**): Available on stm32h72xxx and stm32h73xxx family lines.

Definition at line 2291 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE

Definition at line 2293 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE

macro to get the I2C1 clock source.

Return values:

The	clock source can be one of the following values: RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock

Definition at line 2319 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE

macro to get the I2C2 clock source.

Return values:

The	clock source can be one of the following values: RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock

Definition at line 2347 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE

macro to get the I2C3 clock source.

Return values:

The	clock source can be one of the following values: RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock

Definition at line 2375 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2C4_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))

macro to get the I2C4 clock source.

Return values:

The	clock source can be one of the following values: RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock

Definition at line 2405 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE

macro to get the I2C5 clock source.

Return values:

The	clock source can be one of the following values: RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK5 selected as I2C5 clock RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock

Definition at line 2431 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_LPTIM1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))

macro to get the LPTIM1 clock source.

Return values:

The

clock source can be one of the following values:

RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock

Definition at line 2826 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_GET_LPTIM2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))

macro to get the LPTIM2 clock source.

Return values:

The

clock source can be one of the following values:

RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock

Definition at line 2860 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_GET_LPTIM345_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))

macro to get the LPTIM3/4/5 clock source.

Return values:

The

clock source can be one of the following values:

RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock

Definition at line 2893 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE

macro to get the LPTIM3 clock source.

Return values:

The

clock source can be one of the following values:

RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock

Definition at line 2919 of file stm32h7xx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE

macro to get the LPTIM4 clock source.

Return values:

The

clock source can be one of the following values:

RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock

Definition at line 2944 of file stm32h7xx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE

macro to get the LPTIM5 clock source.

Return values:

The

clock source can be one of the following values:

RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock

Definition at line 2970 of file stm32h7xx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_GET_LPUART1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))

macro to get the LPUART1 clock source.

Return values:

The

clock source can be one of the following values:

RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock

Definition at line 2792 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_OSPI_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL)))

macro to get the OSPI clock source.

Return values:

The

clock source can be one of the following values:

RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock
RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock
RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock
RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock

Definition at line 3023 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_RNG_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))

macro to get the RNG clock source.

Return values:

The	clock source can be one of the following values: RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock

Definition at line 3566 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SAI1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))

Macro to get the SAI1 clock source.

Return values:

The	clock source can be one of the following values: RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock

Definition at line 2031 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SAI4A_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))

Macro to get the SAI4A clock source.

Return values:

The	clock source can be one of the following values: RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2 RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3 RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock = CLKP RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock

Definition at line 2223 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SAI4B_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))

Macro to get the SAI4B clock source.

Return values:

The	clock source can be one of the following values: RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock

Definition at line 2250 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SDMMC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))

Macro to get the SDMMC clock.

Definition at line 3536 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SPDIFRX_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))

Macro to get the SPDIFRX clock source.

Return values:

None

Definition at line 2060 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SPI123_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))

Macro to get the SPI1/2/3 clock source.

Return values:

The

clock source can be one of the following values:

RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock

Definition at line 3312 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE

Macro to get the SPI1 clock source.

Return values:

The	clock source can be one of the following values: RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock

Definition at line 3339 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE

Macro to get the SPI2 clock source.

Return values:

The	clock source can be one of the following values: RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock

Definition at line 3363 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE

Macro to get the SPI3 clock source.

Return values:

The	clock source can be one of the following values: RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock

Definition at line 3387 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SPI45_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))

Macro to get the SPI4/5 clock source.

Return values:

The

clock source can be one of the following values:

RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE

Definition at line 3420 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE

Macro to get the SPI4 clock source.

Return values:

The

clock source can be one of the following values:

RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE

Definition at line 3449 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE

Macro to get the SPI5 clock source.

Return values:

The

clock source can be one of the following values:

RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE

Definition at line 3475 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SPI6_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))

Macro to get the SPI6 clock source.

Return values:

The

clock source can be one of the following values:

RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN

Definition at line 3514 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SWPMI1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))

Macro to get the SWPMI1 clock source.

Return values:

The	clock source can be one of the following values: RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock

Definition at line 3150 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE

macro to get the UART4 clock source.

Return values:

The

clock source can be one of the following values:

RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

Definition at line 2613 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE

macro to get the UART5 clock source.

Return values:

The

clock source can be one of the following values:

RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

Definition at line 2637 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE

macro to get the UART7 clock source.

Return values:

The

clock source can be one of the following values:

RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

Definition at line 2685 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE

macro to get the UART8 clock source.

Return values:

The

clock source can be one of the following values:

RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

Definition at line 2709 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE

macro to get the UART9 clock source.

Return values:

The

clock source can be one of the following values:

RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock
RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock
RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock
RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock

Definition at line 2734 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE

macro to get the USART10 clock source.

Return values:

The

clock source can be one of the following values:

RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock

Definition at line 2760 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART16910_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL)))

macro to get the USART1/6/9* /10* clock source.

Return values:

The

clock source can be one of the following values:

RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock

(*) : Available on some STM32H7 lines only.

Definition at line 2480 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE

Definition at line 2482 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE

macro to get the USART1 clock source.

Return values:

The

clock source can be one of the following values:

RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

Definition at line 2541 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART234578_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))

macro to get the USART2/3/4/5/7/8 clock source.

Return values:

The

clock source can be one of the following values:

RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock

Definition at line 2514 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE

macro to get the USART2 clock source.

Return values:

The

clock source can be one of the following values:

RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

Definition at line 2565 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE

macro to get the USART3 clock source.

Return values:

The

clock source can be one of the following values:

RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

Definition at line 2589 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE

macro to get the USART6 clock source.

Return values:

The

clock source can be one of the following values:

RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

Definition at line 2661 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USB_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))

Macro to get the USB clock source.

Return values:

The	clock source can be one of the following values: RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock

Definition at line 3098 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_I2C1235_CONFIG ( __I2C1235CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__))

macro to configure the I2C1/2/3/5* clock (I2C123CLK).

Parameters:

__I2C1235CLKSource__

specifies the I2C1/2/3/5* clock source. This parameter can be one of the following values:

RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock
RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock
RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock
RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock

(**): Available on stm32h72xxx and stm32h73xxx family lines.

Definition at line 2271 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG

Definition at line 2274 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG

macro to configure the I2C1 clock (I2C1CLK).

Parameters:

__I2C1CLKSource__

specifies the I2C1 clock source. This parameter can be one of the following values:

RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock

Definition at line 2306 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG

macro to configure the I2C2 clock (I2C2CLK).

Parameters:

__I2C2CLKSource__

specifies the I2C2 clock source. This parameter can be one of the following values:

RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock

Definition at line 2334 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG

macro to configure the I2C3 clock (I2C3CLK).

Parameters:

__I2C3CLKSource__

specifies the I2C3 clock source. This parameter can be one of the following values:

RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock

Definition at line 2362 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_CONFIG ( __I2C4CLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))

macro to configure the I2C4 clock (I2C4CLK).

Parameters:

__I2C4CLKSource__

specifies the I2C4 clock source. This parameter can be one of the following values:

RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock

Definition at line 2390 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG

macro to configure the I2C5 clock (I2C5CLK).

Parameters:

__I2C5CLKSource__

specifies the I2C5 clock source. This parameter can be one of the following values:

RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C5 clock
RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock
RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock
RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock

Definition at line 2420 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_CONFIG ( __LPTIM1CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))

macro to configure the LPTIM1 clock source.

Parameters:

__LPTIM1CLKSource__

specifies the LPTIM1 clock source. This parameter can be one of the following values:

RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock

Definition at line 2809 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_LPTIM2_CONFIG ( __LPTIM2CLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))

macro to configure the LPTIM2 clock source.

Parameters:

__LPTIM2CLKSource__

specifies the LPTIM2 clock source. This parameter can be one of the following values:

RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock

Definition at line 2843 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_LPTIM345_CONFIG ( __LPTIM345CLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))

macro to configure the LPTIM3/4/5 clock source.

Parameters:

__LPTIM345CLKSource__

specifies the LPTIM3/4/5 clock source.

RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock

Definition at line 2876 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG

macro to configure the LPTIM3 clock source.

Parameters:

__LPTIM3CLKSource__

specifies the LPTIM3 clock source.

RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock

Definition at line 2908 of file stm32h7xx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG

macro to configure the LPTIM4 clock source.

Parameters:

__LPTIM4CLKSource__

specifies the LPTIM4 clock source.

RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock

Definition at line 2932 of file stm32h7xx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG

macro to configure the LPTIM5 clock source.

Parameters:

__LPTIM5CLKSource__

specifies the LPTIM5 clock source.

RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock

Definition at line 2958 of file stm32h7xx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPUART1_CONFIG ( __LPUART1CLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))

macro to configure the LPUART1 clock (LPUART1CLK).

Parameters:

__LPUART1CLKSource__

specifies the LPUART1 clock source. This parameter can be one of the following values:

RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock

Definition at line 2775 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)

Clear the RCC LSE CSS EXTI flag.

Return values:

None.

Definition at line 3709 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Event Line.

Return values:

None.

Definition at line 3625 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Falling Trigger.

Return values:

None.

Definition at line 3664 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Line.

Return values:

None

Definition at line 3613 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Rising Trigger.

Return values:

None.

Definition at line 3677 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE ( )

Value:

do {                                                       \
    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

Return values:

None.

Definition at line 3693 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Event Line.

Return values:

None.

Definition at line 3619 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Falling Trigger.

Return values:

None.

Definition at line 3657 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Line.

Return values:

None

Definition at line 3607 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnableLSECSS_IT().

#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Rising Trigger.

Return values:

None.

Definition at line 3671 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnableLSECSS_IT().

#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE ( )

Value:

do {                                                      \
    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

Return values:

None.

Definition at line 3683 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)

Generate a Software interrupt on the RCC LSE CSS EXTI line.

Return values:

None.

Definition at line 3728 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_GET_FLAG ( ) (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)

Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.

Return values:

EXTI	RCC LSE CSS Line Status.

Definition at line 3703 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_OSPI_CONFIG ( __OSPICLKSource__ ) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))

macro to configure the OSPI clock source.

Parameters:

__OSPICLKSource__

specifies the OSPI clock source.

RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock
RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock
RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock
RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock

Definition at line 3009 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLL2_CONFIG	(	__PLL2M__,
		__PLL2N__,
		__PLL2P__,
		__PLL2Q__,
		__PLL2R__
	)

Value:

do{ \
                       MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U));  \
                       WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
                       ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
                    } while(0)

Macro to configures the PLL2 multiplication and division factors.

Note:: This function must be used only when PLL2 is disabled.

Parameters:

__PLL2M__ specifies the division factor for PLL2 VCO input clock This parameter must be a number between 1 and 63.

Note:: You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.

Parameters:

__PLL2N__ specifies the multiplication factor for PLL2 VCO output clock This parameter must be a number between 4 and 512 or between 8 and 420(*).

Note:: You have to set the PLL2N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)

Parameters:

__PLL2P__	specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.
__PLL2Q__	specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.
__PLL2R__	specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.

Note:: To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to __PLL2P__, __PLL2Q__ or __PLL2R__ parameters.

Return values:

None	(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Definition at line 1829 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)

Definition at line 1766 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLL2ON)

Macros to enable or disable PLL2.

Note:: After enabling PLL2, the application software should wait on PLL2RDY flag to be set indicating that PLL2 clock is stable and can be used as kernel clock source.; PLL2 is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 1765 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2_VCIRANGE ( __RCC_PLL2VCIRange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))

Macro to select the PLL2 reference frequency range.

Parameters:

__RCC_PLL2VCIRange__

specifies the PLL2 input frequency range This parameter can be one of the following values:

RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz

Return values:

None

Definition at line 1864 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2_VCORANGE ( __RCC_PLL2VCORange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))

Macro to select the PLL2 reference frequency range.

Parameters:

__RCC_PLL2VCORange__

Specifies the PLL2 input frequency range This parameter can be one of the following values:

RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Return values:

None

Definition at line 1878 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2CLKOUT_DISABLE ( __RCC_PLL2ClockOut__ ) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))

Definition at line 1786 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLL2CLKOUT_ENABLE ( __RCC_PLL2ClockOut__ ) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))

Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)

Note:: Enabling/disabling those Clocks can be done only when the PLL2 is disabled, This is mainly used to save Power.

Parameters:

__RCC_PLL2ClockOut__

Specifies the PLL2 clock to be outputted This parameter can be one of the following values:

RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)

(*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.

Return values:

None

Definition at line 1784 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2FRACN_CONFIG ( __RCC_PLL2FRACN__ ) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))

Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.

Note:: These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO

Parameters:

__RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO It should be a value between 0 and 8191

Note:: Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 150 to 420 MHz if PLL2VCOSEL = 1.

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Return values:

None

Definition at line 1852 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2FRACN_DISABLE ( ) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)

Definition at line 1795 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2FRACN_ENABLE ( ) SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)

Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.

Note:: Enabling/disabling Fractional Part can be any time without the need to stop the PLL2

Return values:

None

Definition at line 1793 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL3_CONFIG	(	__PLL3M__,
		__PLL3N__,
		__PLL3P__,
		__PLL3Q__,
		__PLL3R__
	)

Value:

do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U));  \
                         WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
                                   ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
                       } while(0)

Macro to configures the PLL3 multiplication and division factors.

Note:: This function must be used only when PLL3 is disabled.

Parameters:

__PLL3M__ specifies the division factor for PLL3 VCO input clock This parameter must be a number between 1 and 63.

Note:: You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.

Parameters:

__PLL3N__ specifies the multiplication factor for PLL3 VCO output clock This parameter must be a number between 4 and 512.

Note:: You have to set the PLL3N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)

Parameters:

__PLL3P__	specifies the division factor for peripheral kernel clocks This parameter must be a number between 2 and 128 (where odd numbers not allowed)
__PLL3Q__	specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
__PLL3R__	specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128

Note:: To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to __PLL3P__, __PLL3Q__ or __PLL3R__ parameters.

Return values:

None	(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Definition at line 1951 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)

Definition at line 1888 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLL3ON)

Macros to enable or disable the main PLL3.

Note:: After enabling PLL3, the application software should wait on PLL3RDY flag to be set indicating that PLL3 clock is stable and can be used as kernel clock source.; PLL3 is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 1887 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3_VCIRANGE ( __RCC_PLL3VCIRange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))

Macro to select the PLL3 reference frequency range.

Parameters:

__RCC_PLL3VCIRange__

specifies the PLL1 input frequency range This parameter can be one of the following values:

RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz

Return values:

None

Definition at line 1986 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3_VCORANGE ( __RCC_PLL3VCORange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))

Macro to select the PLL3 reference frequency range.

Parameters:

__RCC_PLL3VCORange__

specifies the PLL1 input frequency range This parameter can be one of the following values:

RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Return values:

None

Definition at line 2000 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3CLKOUT_DISABLE ( __RCC_PLL3ClockOut__ ) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))

Definition at line 1917 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLL3CLKOUT_ENABLE ( __RCC_PLL3ClockOut__ ) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))

Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)

Note:: Enabling/disabling those Clocks can be done only when the PLL3 is disabled, This is mainly used to save Power.

Parameters:

__RCC_PLL3ClockOut__

specifies the PLL3 clock to be outputted This parameter can be one of the following values:

RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)

(*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.

Return values:

None

Definition at line 1915 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3FRACN_CONFIG ( __RCC_PLL3FRACN__ ) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)

Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.

Note:: These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO

Parameters:

__RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value between 0 and 8191

Note:: Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 150 to 420 MHz if PLL3VCOSEL = 1.

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Return values:

None

Definition at line 1975 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3FRACN_DISABLE ( ) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)

Definition at line 1897 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3FRACN_ENABLE ( ) SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)

Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.

Note:: Enabling/disabling Fractional Part can be any time without the need to stop the PLL3

Return values:

None

Definition at line 1895 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_RNG_CONFIG ( __RNGCLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))

macro to configure the RNG clock (RNGCLK).

Parameters:

__RNGCLKSource__

specifies the RNG clock source. This parameter can be one of the following values:

RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock

Definition at line 3551 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI1_CONFIG ( __RCC_SAI1CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))

Macro to Configure the SAI1 clock source.

Parameters:

__RCC_SAI1CLKSource__

defines the SAI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:

RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC
RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock

Return values:

None

Definition at line 2015 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI4A_CONFIG ( __RCC_SAI4ACLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))

Macro to Configure the SAI4A clock source.

Parameters:

__RCC_SAI4ACLKSource__

defines the SAI4A clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:

RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL
RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2
RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3
RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock = CLKP
RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock

Return values:

None

Definition at line 2212 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI4B_CONFIG ( __RCC_SAI4BCLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))

Macro to Configure the SAI4B clock source.

Parameters:

__RCC_SAI4BCLKSource__

defines the SAI4B clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:

RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP
RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock

Return values:

None

Definition at line 2239 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SDMMC_CONFIG ( __SDMMCCLKSource__ ) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))

Macro to configure the SDMMC clock.

Parameters:

__SDMMCCLKSource__

specifies clock source for SDMMC This parameter can be one of the following values:

RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock
RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock

Definition at line 3526 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPDIFRX_CONFIG ( __RCC_SPDIFCLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))

Macro to Configure the SPDIFRX clock source.

Parameters:

__RCC_SPDIFCLKSource__

defines the SPDIFRX clock source. This clock is derived from system PLL, PLL2, PLL3, or internal OSC clock This parameter can be one of the following values:

RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL
RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI

Return values:

None

Definition at line 2048 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI123_CONFIG ( __RCC_SPI123CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))

Macro to Configure the SPI1/2/3 clock source.

Parameters:

__RCC_SPI123CLKSource__

defines the SPI1/2/3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:

RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock

Return values:

None

Definition at line 3296 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG

Macro to Configure the SPI1 clock source.

Parameters:

__RCC_SPI1CLKSource__

defines the SPI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:

RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock

Return values:

None

Definition at line 3329 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG

Macro to Configure the SPI2 clock source.

Parameters:

__RCC_SPI2CLKSource__

defines the SPI2 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:

RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock

Return values:

None

Definition at line 3353 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG

Macro to Configure the SPI3 clock source.

Parameters:

__RCC_SPI3CLKSource__

defines the SPI3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:

RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock

Return values:

None

Definition at line 3377 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI45_CONFIG ( __RCC_SPI45CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))

Macro to Configure the SPI4/5 clock source.

Parameters:

__RCC_SPI45CLKSource__

defines the SPI4/5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:

RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE

Return values:

None

Definition at line 3403 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG

Macro to Configure the SPI4 clock source.

Parameters:

__RCC_SPI4CLKSource__

defines the SPI4 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:

RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE

Return values:

None

Definition at line 3438 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG

Macro to Configure the SPI5 clock source.

Parameters:

__RCC_SPI5CLKSource__

defines the SPI5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:

RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE

Return values:

None

Definition at line 3464 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_CONFIG ( __RCC_SPI6CLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))

Macro to Configure the SPI6 clock source.

Parameters:

__RCC_SPI6CLKSource__

defines the SPI6 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:

RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*)

Return values:

None	(*) : Available on stm32h7a3xx and stm32h7b3xx family lines.

Definition at line 3496 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SWPMI1_CONFIG ( __SWPMI1CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))

Macro to configure the SWPMI1 clock.

Parameters:

__SWPMI1CLKSource__

specifies the SWPMI1 clock source. This parameter can be one of the following values:

RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock

Definition at line 3137 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_TIMCLKPRESCALER ( __PRESC__ )

Value:

do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
                                                 RCC->CFGR |= (__PRESC__);       \
                                                }while(0)

Macro to configure the Timers clocks prescalers.

Parameters:

__PRESC__

specifies the Timers clocks prescalers selection This parameter can be one of the following values:

RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, else it is equal to 4 x Frcc_pclkx_d2

Definition at line 3599 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG

macro to configure the UART4 clock (UART4CLK).

Parameters:

__UART4CLKSource__

specifies the UART4 clock source. This parameter can be one of the following values:

RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

Definition at line 2602 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG

macro to configure the UART5 clock (UART5CLK).

Parameters:

__UART5CLKSource__

specifies the UART5 clock source. This parameter can be one of the following values:

RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

Definition at line 2626 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG

macro to configure the UART5 clock (UART7CLK).

Parameters:

__UART7CLKSource__

specifies the UART7 clock source. This parameter can be one of the following values:

RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

Definition at line 2674 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG

macro to configure the UART8 clock (UART8CLK).

Parameters:

__UART8CLKSource__

specifies the UART8 clock source. This parameter can be one of the following values:

RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

Definition at line 2698 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG

macro to configure the UART9 clock (UART9CLK).

Parameters:

__UART8CLKSource__

specifies the UART8 clock source. This parameter can be one of the following values:

RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock
RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock
RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock
RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock

Definition at line 2723 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG

macro to configure the USART10 clock (USART10CLK).

Parameters:

__UART8CLKSource__

specifies the UART8 clock source. This parameter can be one of the following values:

RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock

Definition at line 2749 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART16910_CONFIG ( __USART16910CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))

macro to configure the USART1/6/9* /10* clock (USART16CLK).

Parameters:

__USART16910CLKSource__

specifies the USART1/6/9* /10* clock source. This parameter can be one of the following values:

RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock

(*) : Available on some STM32H7 lines only.

Definition at line 2456 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG

Definition at line 2459 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG

macro to configure the USART1 clock (USART1CLK).

Parameters:

__USART1CLKSource__

specifies the USART1 clock source. This parameter can be one of the following values:

RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

Definition at line 2530 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART234578_CONFIG ( __USART234578CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))

macro to configure the USART234578 clock (USART234578CLK).

Parameters:

__USART234578CLKSource__

specifies the USART2/3/4/5/7/8 clock source. This parameter can be one of the following values: