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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_rcc_ex.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC HAL Extension module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file in 00013 * the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 ****************************************************************************** 00016 */ 00017 00018 /* Define to prevent recursive inclusion -------------------------------------*/ 00019 #ifndef STM32H7xx_HAL_RCC_EX_H 00020 #define STM32H7xx_HAL_RCC_EX_H 00021 00022 #ifdef __cplusplus 00023 extern "C" { 00024 #endif 00025 00026 /* Includes ------------------------------------------------------------------*/ 00027 #include "stm32h7xx_hal_def.h" 00028 00029 /** @addtogroup STM32H7xx_HAL_Driver 00030 * @{ 00031 */ 00032 00033 /** @addtogroup RCCEx 00034 * @{ 00035 */ 00036 00037 /* Exported types ------------------------------------------------------------*/ 00038 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 00039 * @{ 00040 */ 00041 00042 /** 00043 * @brief PLL2 Clock structure definition 00044 */ 00045 typedef struct 00046 { 00047 00048 uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. 00049 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 00050 00051 uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. 00052 This parameter must be a number between Min_Data = 4 and Max_Data = 512 00053 or between Min_Data = 8 and Max_Data = 420(*) 00054 (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ 00055 00056 uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. 00057 This parameter must be a number between Min_Data = 2 and Max_Data = 128 00058 odd division factors are not allowed */ 00059 00060 uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. 00061 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 00062 00063 uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. 00064 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 00065 uint32_t PLL2RGE; /*!<PLL2RGE: PLL2 clock Input range 00066 This parameter must be a value of @ref RCC_PLL2_VCI_Range */ 00067 uint32_t PLL2VCOSEL; /*!<PLL2VCOSEL: PLL2 clock Output range 00068 This parameter must be a value of @ref RCC_PLL2_VCO_Range */ 00069 00070 uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for 00071 PLL2 VCO It should be a value between 0 and 8191 */ 00072 }RCC_PLL2InitTypeDef; 00073 00074 /** 00075 * @brief PLL3 Clock structure definition 00076 */ 00077 typedef struct 00078 { 00079 00080 uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. 00081 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 00082 00083 uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock. 00084 This parameter must be a number between Min_Data = 4 and Max_Data = 512 00085 or between Min_Data = 8 and Max_Data = 420(*) 00086 (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ 00087 00088 uint32_t PLL3P; /*!< PLL3P: Division factor for system clock. 00089 This parameter must be a number between Min_Data = 2 and Max_Data = 128 00090 odd division factors are not allowed */ 00091 00092 uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks. 00093 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 00094 00095 uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks. 00096 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 00097 uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range 00098 This parameter must be a value of @ref RCC_PLL3_VCI_Range */ 00099 uint32_t PLL3VCOSEL; /*!<PLL3VCOSEL: PLL3 clock Output range 00100 This parameter must be a value of @ref RCC_PLL3_VCO_Range */ 00101 00102 uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for 00103 PLL3 VCO It should be a value between 0 and 8191 */ 00104 }RCC_PLL3InitTypeDef; 00105 00106 /** 00107 * @brief RCC PLL1 Clocks structure definition 00108 */ 00109 typedef struct 00110 { 00111 uint32_t PLL1_P_Frequency; 00112 uint32_t PLL1_Q_Frequency; 00113 uint32_t PLL1_R_Frequency; 00114 }PLL1_ClocksTypeDef; 00115 00116 /** 00117 * @brief RCC PLL2 Clocks structure definition 00118 */ 00119 typedef struct 00120 { 00121 uint32_t PLL2_P_Frequency; 00122 uint32_t PLL2_Q_Frequency; 00123 uint32_t PLL2_R_Frequency; 00124 }PLL2_ClocksTypeDef; 00125 00126 /** 00127 * @brief RCC PLL3 Clocks structure definition 00128 */ 00129 typedef struct 00130 { 00131 uint32_t PLL3_P_Frequency; 00132 uint32_t PLL3_Q_Frequency; 00133 uint32_t PLL3_R_Frequency; 00134 }PLL3_ClocksTypeDef; 00135 00136 00137 /** 00138 * @brief RCC extended clocks structure definition 00139 */ 00140 typedef struct 00141 { 00142 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00143 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00144 00145 RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters. 00146 This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */ 00147 00148 RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters. 00149 This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */ 00150 00151 uint32_t FmcClockSelection; /*!< Specifies FMC clock source 00152 This parameter can be a value of @ref RCCEx_FMC_Clock_Source */ 00153 00154 #if defined(QUADSPI) 00155 uint32_t QspiClockSelection; /*!< Specifies QSPI clock source 00156 This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */ 00157 #endif /* QUADSPI */ 00158 00159 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00160 uint32_t OspiClockSelection; /*!< Specifies OSPI clock source 00161 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 00162 #endif /*(OCTOSPI1) || (OCTOSPI2)*/ 00163 00164 00165 #if defined(DSI) 00166 uint32_t DsiClockSelection; /*!< Specifies DSI clock source 00167 This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ 00168 #endif /* DSI */ 00169 00170 uint32_t SdmmcClockSelection; /*!< Specifies SDMMC clock source 00171 This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */ 00172 00173 uint32_t CkperClockSelection; /*!< Specifies CKPER clock source 00174 This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */ 00175 00176 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source 00177 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 00178 00179 #if defined(SAI3) 00180 uint32_t Sai23ClockSelection; /*!< Specifies SAI2/3 clock source 00181 This parameter can be a value of @ref RCCEx_SAI23_Clock_Source */ 00182 #endif /* SAI3 */ 00183 00184 #if defined(RCC_CDCCIP1R_SAI2ASEL) 00185 uint32_t Sai2AClockSelection; /*!< Specifies SAI2A clock source 00186 This parameter can be a value of @ref RCCEx_SAI2A_Clock_Source */ 00187 #endif /* RCC_CDCCIP1R_SAI2ASEL */ 00188 00189 #if defined(RCC_CDCCIP1R_SAI2BSEL) 00190 uint32_t Sai2BClockSelection; /*!< Specifies SAI2B clock source 00191 This parameter can be a value of @ref RCCEx_SAI2B_Clock_Source */ 00192 #endif /* RCC_CDCCIP1R_SAI2BSEL */ 00193 00194 uint32_t Spi123ClockSelection; /*!< Specifies SPI1/2/3 clock source 00195 This parameter can be a value of @ref RCCEx_SPI123_Clock_Source */ 00196 00197 uint32_t Spi45ClockSelection; /*!< Specifies SPI4/5 clock source 00198 This parameter can be a value of @ref RCCEx_SPI45_Clock_Source */ 00199 00200 uint32_t SpdifrxClockSelection; /*!< Specifies SPDIFRX Clock clock source 00201 This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ 00202 00203 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock clock source 00204 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ 00205 00206 #if defined(DFSDM2_BASE) 00207 uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock clock source 00208 This parameter can be a value of @ref RCCEx_DFSDM2_Clock_Source */ 00209 #endif /* DFSDM2_BASE */ 00210 00211 #if defined(FDCAN1) || defined(FDCAN2) 00212 uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source 00213 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 00214 #endif /*FDCAN1 || FDCAN2*/ 00215 00216 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 Clock clock source 00217 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ 00218 00219 uint32_t Usart234578ClockSelection; /*!< Specifies USART2/3/4/5/7/8 clock source 00220 This parameter can be a value of @ref RCCEx_USART234578_Clock_Source */ 00221 00222 uint32_t Usart16ClockSelection; /*!< Specifies USART1/6 clock source 00223 This parameter can be a value of @ref RCCEx_USART16_Clock_Source */ 00224 00225 uint32_t RngClockSelection; /*!< Specifies RNG clock source 00226 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 00227 00228 #if defined(I2C5) 00229 uint32_t I2c1235ClockSelection; /*!< Specifies I2C1/2/3/5 clock source 00230 This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source */ 00231 #else 00232 uint32_t I2c123ClockSelection; /*!< Specifies I2C1/2/3 clock source 00233 This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source */ 00234 #endif /*I2C5*/ 00235 00236 uint32_t UsbClockSelection; /*!< Specifies USB clock source 00237 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 00238 00239 uint32_t CecClockSelection; /*!< Specifies CEC clock source 00240 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 00241 00242 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source 00243 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 00244 00245 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source 00246 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 00247 00248 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source 00249 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 00250 00251 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source 00252 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 00253 00254 uint32_t Lptim345ClockSelection; /*!< Specifies LPTIM3/4/5 clock source 00255 This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source */ 00256 00257 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source 00258 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 00259 #if defined(SAI4) 00260 uint32_t Sai4AClockSelection; /*!< Specifies SAI4A clock source 00261 This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source */ 00262 00263 uint32_t Sai4BClockSelection; /*!< Specifies SAI4B clock source 00264 This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source */ 00265 #endif /* SAI4 */ 00266 00267 uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source 00268 This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */ 00269 00270 uint32_t RTCClockSelection; /*!< Specifies RTC Clock clock source 00271 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00272 00273 #if defined(HRTIM1) 00274 uint32_t Hrtim1ClockSelection; /*!< Specifies HRTIM1 Clock clock source 00275 This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */ 00276 #endif /* HRTIM1 */ 00277 00278 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 00279 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ 00280 }RCC_PeriphCLKInitTypeDef; 00281 00282 /*!< Alias for Inter STM32H7 lines compatibility regarding RCC_PeriphCLKInitTypeDef field : I2C5 available on some lines only */ 00283 #if defined(I2C5) 00284 #define I2c123ClockSelection I2c1235ClockSelection 00285 #else 00286 #define I2c1235ClockSelection I2c123ClockSelection 00287 #endif /*I2C5*/ 00288 00289 00290 /** 00291 * @brief RCC_CRS Init structure definition 00292 */ 00293 typedef struct 00294 { 00295 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 00296 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 00297 00298 uint32_t Source; /*!< Specifies the SYNC signal source. 00299 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 00300 00301 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 00302 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 00303 00304 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 00305 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 00306 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 00307 00308 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 00309 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 00310 00311 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 00312 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 00313 00314 }RCC_CRSInitTypeDef; 00315 00316 /** 00317 * @brief RCC_CRS Synchronization structure definition 00318 */ 00319 typedef struct 00320 { 00321 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 00322 This parameter must be a number between 0 and 0xFFFF */ 00323 00324 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 00325 This parameter must be a number between 0 and 0x3F */ 00326 00327 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 00328 value latched in the time of the last SYNC event. 00329 This parameter must be a number between 0 and 0xFFFF */ 00330 00331 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 00332 frequency error counter latched in the time of the last SYNC event. 00333 It shows whether the actual frequency is below or above the target. 00334 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 00335 00336 }RCC_CRSSynchroInfoTypeDef; 00337 00338 /** 00339 * @} 00340 */ 00341 00342 00343 /* Exported constants --------------------------------------------------------*/ 00344 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 00345 * @{ 00346 */ 00347 00348 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 00349 * @{ 00350 */ 00351 00352 #if defined(UART9) && defined(USART10) 00353 #define RCC_PERIPHCLK_USART16910 (0x00000001U) 00354 #define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16910 00355 #define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16910 00356 #define RCC_PERIPHCLK_UART9 RCC_PERIPHCLK_USART16910 00357 #define RCC_PERIPHCLK_USART10 RCC_PERIPHCLK_USART16910 00358 /*alias*/ 00359 #define RCC_PERIPHCLK_USART16 RCC_PERIPHCLK_USART16910 00360 #else 00361 #define RCC_PERIPHCLK_USART16 (0x00000001U) 00362 #define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16 00363 #define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16 00364 /* alias */ 00365 #define RCC_PERIPHCLK_USART16910 RCC_PERIPHCLK_USART16 00366 #endif /* UART9 && USART10*/ 00367 #define RCC_PERIPHCLK_USART234578 (0x00000002U) 00368 #define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578 00369 #define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578 00370 #define RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578 00371 #define RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578 00372 #define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578 00373 #define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578 00374 #define RCC_PERIPHCLK_LPUART1 (0x00000004U) 00375 #if defined(I2C5) 00376 #define RCC_PERIPHCLK_I2C1235 (0x00000008U) 00377 #define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C1235 00378 #define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C1235 00379 #define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C1235 00380 /* alias */ 00381 #define RCC_PERIPHCLK_I2C123 RCC_PERIPHCLK_I2C1235 00382 #else 00383 #define RCC_PERIPHCLK_I2C123 (0x00000008U) 00384 #define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123 00385 #define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123 00386 #define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123 00387 #endif /*I2C5*/ 00388 #define RCC_PERIPHCLK_I2C4 (0x00000010U) 00389 #if defined(I2C5) 00390 #define RCC_PERIPHCLK_I2C5 RCC_PERIPHCLK_I2C1235 00391 #endif /*I2C5*/ 00392 #define RCC_PERIPHCLK_LPTIM1 (0x00000020U) 00393 #define RCC_PERIPHCLK_LPTIM2 (0x00000040U) 00394 #define RCC_PERIPHCLK_LPTIM345 (0x00000080U) 00395 #define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345 00396 #if defined(LPTIM4) 00397 #define RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345 00398 #endif /*LPTIM4*/ 00399 #if defined(LPTIM5) 00400 #define RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345 00401 #endif /*LPTIM5*/ 00402 #define RCC_PERIPHCLK_SAI1 (0x00000100U) 00403 #if defined(SAI3) 00404 #define RCC_PERIPHCLK_SAI23 (0x00000200U) 00405 #define RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23 00406 #define RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23 00407 #endif /* SAI3 */ 00408 #if defined(RCC_CDCCIP1R_SAI2ASEL_0) 00409 #define RCC_PERIPHCLK_SAI2A (0x00000200U) 00410 #endif /* RCC_CDCCIP1R_SAI2ASEL_0 */ 00411 #if defined(RCC_CDCCIP1R_SAI2BSEL_0) 00412 #define RCC_PERIPHCLK_SAI2B (0x00000400U) 00413 #endif /* RCC_CDCCIP1R_SAI2BSEL_0 */ 00414 #if defined(SAI4) 00415 #define RCC_PERIPHCLK_SAI4A (0x00000400U) 00416 #define RCC_PERIPHCLK_SAI4B (0x00000800U) 00417 #endif /* SAI4 */ 00418 #define RCC_PERIPHCLK_SPI123 (0x00001000U) 00419 #define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123 00420 #define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123 00421 #define RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123 00422 #define RCC_PERIPHCLK_SPI45 (0x00002000U) 00423 #define RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45 00424 #define RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45 00425 #define RCC_PERIPHCLK_SPI6 (0x00004000U) 00426 #define RCC_PERIPHCLK_FDCAN (0x00008000U) 00427 #define RCC_PERIPHCLK_SDMMC (0x00010000U) 00428 #define RCC_PERIPHCLK_RNG (0x00020000U) 00429 #define RCC_PERIPHCLK_USB (0x00040000U) 00430 #define RCC_PERIPHCLK_ADC (0x00080000U) 00431 #define RCC_PERIPHCLK_SWPMI1 (0x00100000U) 00432 #define RCC_PERIPHCLK_DFSDM1 (0x00200000U) 00433 #if defined(DFSDM2_BASE) 00434 #define RCC_PERIPHCLK_DFSDM2 (0x00000800U) 00435 #endif /* DFSDM2 */ 00436 #define RCC_PERIPHCLK_RTC (0x00400000U) 00437 #define RCC_PERIPHCLK_CEC (0x00800000U) 00438 #define RCC_PERIPHCLK_FMC (0x01000000U) 00439 #if defined(QUADSPI) 00440 #define RCC_PERIPHCLK_QSPI (0x02000000U) 00441 #endif /* QUADSPI */ 00442 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00443 #define RCC_PERIPHCLK_OSPI (0x02000000U) 00444 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ 00445 #define RCC_PERIPHCLK_DSI (0x04000000U) 00446 #define RCC_PERIPHCLK_SPDIFRX (0x08000000U) 00447 #if defined(HRTIM1) 00448 #define RCC_PERIPHCLK_HRTIM1 (0x10000000U) 00449 #endif /* HRTIM1 */ 00450 #if defined(LTDC) 00451 #define RCC_PERIPHCLK_LTDC (0x20000000U) 00452 #endif /* LTDC */ 00453 #define RCC_PERIPHCLK_TIM (0x40000000U) 00454 #define RCC_PERIPHCLK_CKPER (0x80000000U) 00455 00456 /** 00457 * @} 00458 */ 00459 00460 00461 /** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output 00462 * @{ 00463 */ 00464 #define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN 00465 #define RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN 00466 #define RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN 00467 00468 /** 00469 * @} 00470 */ 00471 00472 /** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output 00473 * @{ 00474 */ 00475 #define RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN 00476 #define RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN 00477 #define RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN 00478 00479 /** 00480 * @} 00481 */ 00482 00483 /** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range 00484 * @{ 00485 */ 00486 #define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ 00487 #define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ 00488 #define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ 00489 #define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ 00490 00491 /** 00492 * @} 00493 */ 00494 00495 00496 /** @defgroup RCC_PLL2_VCO_Range RCC PLL2 VCO Range 00497 * @{ 00498 */ 00499 #define RCC_PLL2VCOWIDE (0x00000000U) 00500 #define RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL 00501 00502 /** 00503 * @} 00504 */ 00505 00506 /** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range 00507 * @{ 00508 */ 00509 #define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ 00510 #define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ 00511 #define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ 00512 #define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ 00513 00514 /** 00515 * @} 00516 */ 00517 00518 00519 /** @defgroup RCC_PLL3_VCO_Range RCC PLL3 VCO Range 00520 * @{ 00521 */ 00522 #define RCC_PLL3VCOWIDE (0x00000000U) 00523 #define RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL 00524 00525 /** 00526 * @} 00527 */ 00528 00529 /** @defgroup RCCEx_USART16_Clock_Source RCCEx USART1/6 Clock Source 00530 * @{ 00531 */ 00532 #if defined(RCC_D2CCIP2R_USART16SEL) 00533 #define RCC_USART16CLKSOURCE_D2PCLK2 (0x00000000U) 00534 /* alias */ 00535 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 00536 #define RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0 00537 #define RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1 00538 #define RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1) 00539 #define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2 00540 #define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2) 00541 00542 #elif defined(RCC_CDCCIP2R_USART16910SEL) 00543 #define RCC_USART16910CLKSOURCE_CDPCLK2 (0x00000000U) 00544 /* alias */ 00545 #define RCC_USART16910CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_CDPCLK2 00546 #define RCC_USART16910CLKSOURCE_PLL2 RCC_CDCCIP2R_USART16910SEL_0 00547 #define RCC_USART16910CLKSOURCE_PLL3 RCC_CDCCIP2R_USART16910SEL_1 00548 #define RCC_USART16910CLKSOURCE_HSI (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1) 00549 #define RCC_USART16910CLKSOURCE_CSI RCC_CDCCIP2R_USART16910SEL_2 00550 #define RCC_USART16910CLKSOURCE_LSE (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2) 00551 00552 /* Aliases */ 00553 #define RCC_USART16CLKSOURCE_CDPCLK2 RCC_USART16910CLKSOURCE_CDPCLK2 00554 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_CDPCLK2 00555 #define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_CDPCLK2 00556 #define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2 00557 #define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3 00558 #define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI 00559 #define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI 00560 #define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE 00561 00562 #else /* RCC_D2CCIP2R_USART16910SEL */ 00563 #define RCC_USART16910CLKSOURCE_D2PCLK2 (0x00000000U) 00564 #define RCC_USART16910CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16910SEL_0 00565 #define RCC_USART16910CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16910SEL_1 00566 #define RCC_USART16910CLKSOURCE_HSI (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1) 00567 #define RCC_USART16910CLKSOURCE_CSI RCC_D2CCIP2R_USART16910SEL_2 00568 #define RCC_USART16910CLKSOURCE_LSE (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2) 00569 00570 /* Aliases */ 00571 #define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2 00572 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2 00573 #define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2 00574 #define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3 00575 #define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI 00576 #define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI 00577 #define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE 00578 #endif /* RCC_D2CCIP2R_USART16SEL */ 00579 /** 00580 * @} 00581 */ 00582 00583 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source 00584 * @{ 00585 */ 00586 #define RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 00587 #define RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 00588 #define RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 00589 #define RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 00590 #define RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 00591 #define RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 00592 /** 00593 * @} 00594 */ 00595 00596 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source 00597 * @{ 00598 */ 00599 #define RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 00600 #define RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 00601 #define RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 00602 #define RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 00603 #define RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 00604 #define RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 00605 00606 /** 00607 * @} 00608 */ 00609 00610 #if defined(UART9) 00611 /** @defgroup RCCEx_UART9_Clock_Source RCCEx UART9 Clock Source 00612 * @{ 00613 */ 00614 #define RCC_UART9CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 00615 #define RCC_UART9CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 00616 #define RCC_UART9CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 00617 #define RCC_UART9CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 00618 #define RCC_UART9CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 00619 #define RCC_UART9CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 00620 /** 00621 * @} 00622 */ 00623 #endif /* UART9 */ 00624 00625 #if defined(USART10) 00626 /** @defgroup RCCEx_USART10_Clock_Source RCCEx USART10 Clock Source 00627 * @{ 00628 */ 00629 #define RCC_USART10CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 00630 #define RCC_USART10CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 00631 #define RCC_USART10CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 00632 #define RCC_USART10CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 00633 #define RCC_USART10CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 00634 #define RCC_USART10CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 00635 /** 00636 * @} 00637 */ 00638 #endif /* USART10 */ 00639 00640 /** @defgroup RCCEx_USART234578_Clock_Source RCCEx USART2/3/4/5/7/8 Clock Source 00641 * @{ 00642 */ 00643 #if defined(RCC_D2CCIP2R_USART28SEL) 00644 #define RCC_USART234578CLKSOURCE_D2PCLK1 (0x00000000U) 00645 /* alias */ 00646 #define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 00647 #define RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0 00648 #define RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1 00649 #define RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1) 00650 #define RCC_USART234578CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2 00651 #define RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2) 00652 #else 00653 #define RCC_USART234578CLKSOURCE_CDPCLK1 (0x00000000U) 00654 /* alias */ 00655 #define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1 00656 #define RCC_USART234578CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1 00657 #define RCC_USART234578CLKSOURCE_PLL2 RCC_CDCCIP2R_USART234578SEL_0 00658 #define RCC_USART234578CLKSOURCE_PLL3 RCC_CDCCIP2R_USART234578SEL_1 00659 #define RCC_USART234578CLKSOURCE_HSI (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1) 00660 #define RCC_USART234578CLKSOURCE_CSI RCC_CDCCIP2R_USART234578SEL_2 00661 #define RCC_USART234578CLKSOURCE_LSE (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2) 00662 #endif /* RCC_D2CCIP2R_USART28SEL */ 00663 /** 00664 * @} 00665 */ 00666 00667 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source 00668 * @{ 00669 */ 00670 #define RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 00671 #define RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 00672 #define RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 00673 #define RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 00674 #define RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 00675 #define RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 00676 00677 /** 00678 * @} 00679 */ 00680 00681 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source 00682 * @{ 00683 */ 00684 #define RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 00685 #define RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 00686 #define RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 00687 #define RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 00688 #define RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 00689 #define RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 00690 00691 /** 00692 * @} 00693 */ 00694 00695 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source 00696 * @{ 00697 */ 00698 #define RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 00699 #define RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 00700 #define RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 00701 #define RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 00702 #define RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 00703 #define RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 00704 00705 /** 00706 * @} 00707 */ 00708 00709 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source 00710 * @{ 00711 */ 00712 #define RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 00713 #define RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 00714 #define RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 00715 #define RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 00716 #define RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 00717 #define RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 00718 00719 /** 00720 * @} 00721 */ 00722 00723 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source 00724 * @{ 00725 */ 00726 #define RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 00727 #define RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 00728 #define RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 00729 #define RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 00730 #define RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 00731 #define RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 00732 00733 /** 00734 * @} 00735 */ 00736 00737 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source 00738 * @{ 00739 */ 00740 #define RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 00741 #define RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 00742 #define RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 00743 #define RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 00744 #define RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 00745 #define RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 00746 00747 /** 00748 * @} 00749 */ 00750 00751 /** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source 00752 * @{ 00753 */ 00754 #if defined(RCC_D3CCIPR_LPUART1SEL) 00755 #define RCC_LPUART1CLKSOURCE_D3PCLK1 (0x00000000U) 00756 /* alias */ 00757 #define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_D3PCLK1 00758 #define RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0 00759 #define RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1 00760 #define RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1) 00761 #define RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2 00762 #define RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0) 00763 #else 00764 #define RCC_LPUART1CLKSOURCE_SRDPCLK4 (0x00000000U) 00765 /* alias*/ 00766 #define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_SRDPCLK4 00767 #define RCC_LPUART1CLKSOURCE_D3PCLK1 RCC_LPUART1CLKSOURCE_SRDPCLK4 00768 #define RCC_LPUART1CLKSOURCE_PLL2 RCC_SRDCCIPR_LPUART1SEL_0 00769 #define RCC_LPUART1CLKSOURCE_PLL3 RCC_SRDCCIPR_LPUART1SEL_1 00770 #define RCC_LPUART1CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1) 00771 #define RCC_LPUART1CLKSOURCE_CSI RCC_SRDCCIPR_LPUART1SEL_2 00772 #define RCC_LPUART1CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0) 00773 #endif /* RCC_D3CCIPR_LPUART1SEL */ 00774 /** 00775 * @} 00776 */ 00777 00778 /** @defgroup RCCEx_I2C1235_Clock_Source RCCEx I2C1/2/3/5 Clock Source 00779 * @{ 00780 */ 00781 #if defined (RCC_D2CCIP2R_I2C123SEL) 00782 #define RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U) 00783 #define RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0 00784 #define RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1 00785 #define RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1) 00786 /* aliases */ 00787 #define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 00788 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 00789 #define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 00790 #define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 00791 #elif defined(RCC_CDCCIP2R_I2C123SEL) 00792 #define RCC_I2C123CLKSOURCE_CDPCLK1 (0x00000000U) 00793 /* alias */ 00794 #define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_CDPCLK1 00795 #define RCC_I2C123CLKSOURCE_PLL3 RCC_CDCCIP2R_I2C123SEL_0 00796 #define RCC_I2C123CLKSOURCE_HSI RCC_CDCCIP2R_I2C123SEL_1 00797 #define RCC_I2C123CLKSOURCE_CSI (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1) 00798 /* aliases */ 00799 #define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 00800 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 00801 #define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 00802 #define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 00803 #elif defined(I2C5) 00804 #define RCC_I2C1235CLKSOURCE_D2PCLK1 (0x00000000U) 00805 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C1235SEL_0 00806 #define RCC_I2C1235CLKSOURCE_HSI RCC_D2CCIP2R_I2C1235SEL_1 00807 #define RCC_I2C1235CLKSOURCE_CSI (RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1) 00808 /* aliases */ 00809 #define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 00810 #define RCC_I2C123CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 00811 #define RCC_I2C123CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 00812 #define RCC_I2C123CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 00813 #endif /* RCC_D2CCIP2R_I2C123SEL */ 00814 /** 00815 * @} 00816 */ 00817 00818 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source 00819 * @{ 00820 */ 00821 #if defined(I2C5) 00822 #define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 00823 #define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 00824 #define RCC_I2C1CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 00825 #define RCC_I2C1CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 00826 #else 00827 #define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 00828 #define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 00829 #define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 00830 #define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 00831 #endif /*I2C5*/ 00832 00833 /** 00834 * @} 00835 */ 00836 00837 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source 00838 * @{ 00839 */ 00840 #if defined(I2C5) 00841 #define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 00842 #define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 00843 #define RCC_I2C2CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 00844 #define RCC_I2C2CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 00845 #else 00846 #define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 00847 #define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 00848 #define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 00849 #define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 00850 #endif /*I2C5*/ 00851 00852 /** 00853 * @} 00854 */ 00855 00856 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source 00857 * @{ 00858 */ 00859 #if defined(I2C5) 00860 #define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 00861 #define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 00862 #define RCC_I2C3CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 00863 #define RCC_I2C3CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 00864 #else 00865 #define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 00866 #define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 00867 #define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 00868 #define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 00869 #endif /*I2C5*/ 00870 00871 /** 00872 * @} 00873 */ 00874 00875 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source 00876 * @{ 00877 */ 00878 #if defined(RCC_D3CCIPR_I2C4SEL) 00879 #define RCC_I2C4CLKSOURCE_D3PCLK1 (0x00000000U) 00880 #define RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0 00881 #define RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1 00882 #define RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1) 00883 #else 00884 #define RCC_I2C4CLKSOURCE_SRDPCLK4 (0x00000000U) 00885 /* alias */ 00886 #define RCC_I2C4CLKSOURCE_D3PCLK1 RCC_I2C4CLKSOURCE_SRDPCLK4 00887 #define RCC_I2C4CLKSOURCE_PLL3 RCC_SRDCCIPR_I2C4SEL_0 00888 #define RCC_I2C4CLKSOURCE_HSI RCC_SRDCCIPR_I2C4SEL_1 00889 #define RCC_I2C4CLKSOURCE_CSI (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1) 00890 #endif /* RCC_D3CCIPR_I2C4SEL */ 00891 00892 /** 00893 * @} 00894 */ 00895 #if defined(I2C5) 00896 /** @defgroup RCCEx_I2C5_Clock_Source RCCEx I2C5 Clock Source 00897 * @{ 00898 */ 00899 #define RCC_I2C5CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 00900 #define RCC_I2C5CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 00901 #define RCC_I2C5CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 00902 #define RCC_I2C5CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 00903 00904 /** 00905 * @} 00906 */ 00907 #endif /*I2C5*/ 00908 00909 /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source 00910 * @{ 00911 */ 00912 #if defined(RCC_D2CCIP2R_RNGSEL) 00913 #define RCC_RNGCLKSOURCE_HSI48 (0x00000000U) 00914 #define RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0 00915 #define RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1 00916 #define RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL 00917 #else 00918 #define RCC_RNGCLKSOURCE_HSI48 (0x00000000U) 00919 #define RCC_RNGCLKSOURCE_PLL RCC_CDCCIP2R_RNGSEL_0 00920 #define RCC_RNGCLKSOURCE_LSE RCC_CDCCIP2R_RNGSEL_1 00921 #define RCC_RNGCLKSOURCE_LSI RCC_CDCCIP2R_RNGSEL 00922 #endif /* RCC_D2CCIP2R_RNGSEL */ 00923 00924 /** 00925 * @} 00926 */ 00927 #if defined(HRTIM1) 00928 00929 /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source 00930 * @{ 00931 */ 00932 #define RCC_HRTIM1CLK_TIMCLK (0x00000000U) 00933 #define RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL 00934 00935 /** 00936 * @} 00937 */ 00938 #endif /*HRTIM1*/ 00939 00940 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source 00941 * @{ 00942 */ 00943 #if defined(RCC_D2CCIP2R_USBSEL) 00944 #define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0 00945 #define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1 00946 #define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL 00947 #else 00948 #define RCC_USBCLKSOURCE_PLL RCC_CDCCIP2R_USBSEL_0 00949 #define RCC_USBCLKSOURCE_PLL3 RCC_CDCCIP2R_USBSEL_1 00950 #define RCC_USBCLKSOURCE_HSI48 RCC_CDCCIP2R_USBSEL 00951 #endif /* RCC_D2CCIP2R_USBSEL */ 00952 00953 /** 00954 * @} 00955 */ 00956 00957 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 00958 * @{ 00959 */ 00960 #if defined(RCC_D2CCIP1R_SAI1SEL) 00961 #define RCC_SAI1CLKSOURCE_PLL (0x00000000U) 00962 #define RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0 00963 #define RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1 00964 #define RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1) 00965 #define RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2 00966 #else 00967 #define RCC_SAI1CLKSOURCE_PLL (0x00000000U) 00968 #define RCC_SAI1CLKSOURCE_PLL2 RCC_CDCCIP1R_SAI1SEL_0 00969 #define RCC_SAI1CLKSOURCE_PLL3 RCC_CDCCIP1R_SAI1SEL_1 00970 #define RCC_SAI1CLKSOURCE_PIN (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1) 00971 #define RCC_SAI1CLKSOURCE_CLKP RCC_CDCCIP1R_SAI1SEL_2 00972 #endif /* RCC_D2CCIP1R_SAI1SEL */ 00973 /** 00974 * @} 00975 */ 00976 00977 #if defined(SAI3) 00978 /** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source 00979 * @{ 00980 */ 00981 #define RCC_SAI23CLKSOURCE_PLL (0x00000000U) 00982 #define RCC_SAI23CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0 00983 #define RCC_SAI23CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1 00984 #define RCC_SAI23CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1) 00985 #define RCC_SAI23CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2 00986 /** 00987 * @} 00988 */ 00989 00990 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 00991 * @{ 00992 */ 00993 #define RCC_SAI2CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL 00994 #define RCC_SAI2CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2 00995 #define RCC_SAI2CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3 00996 #define RCC_SAI2CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN 00997 #define RCC_SAI2CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP 00998 00999 /** 01000 * @} 01001 */ 01002 01003 /** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source 01004 * @{ 01005 */ 01006 #define RCC_SAI3CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL 01007 #define RCC_SAI3CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2 01008 #define RCC_SAI3CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3 01009 #define RCC_SAI3CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN 01010 #define RCC_SAI3CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP 01011 /** 01012 * @} 01013 */ 01014 #endif /* SAI3 */ 01015 01016 #if defined(RCC_CDCCIP1R_SAI2ASEL) 01017 /** @defgroup RCCEx_SAI2A_Clock_Source SAI2A Clock Source 01018 * @{ 01019 */ 01020 #define RCC_SAI2ACLKSOURCE_PLL (0x00000000U) 01021 #define RCC_SAI2ACLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2ASEL_0 01022 #define RCC_SAI2ACLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2ASEL_1 01023 #define RCC_SAI2ACLKSOURCE_PIN (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1) 01024 #define RCC_SAI2ACLKSOURCE_CLKP RCC_CDCCIP1R_SAI2ASEL_2 01025 #define RCC_SAI2ACLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2) 01026 /** 01027 * @} 01028 */ 01029 #endif /* RCC_CDCCIP1R_SAI2ASEL */ 01030 01031 #if defined(RCC_CDCCIP1R_SAI2BSEL) 01032 /** @defgroup RCCEx_SAI2B_Clock_Source SAI2B Clock Source 01033 * @{ 01034 */ 01035 #define RCC_SAI2BCLKSOURCE_PLL (0x00000000U) 01036 #define RCC_SAI2BCLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2BSEL_0 01037 #define RCC_SAI2BCLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2BSEL_1 01038 #define RCC_SAI2BCLKSOURCE_PIN (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1) 01039 #define RCC_SAI2BCLKSOURCE_CLKP RCC_CDCCIP1R_SAI2BSEL_2 01040 #define RCC_SAI2BCLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2) 01041 /** 01042 * @} 01043 */ 01044 #endif /* RCC_CDCCIP1R_SAI2BSEL */ 01045 01046 01047 /** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source 01048 * @{ 01049 */ 01050 #if defined(RCC_D2CCIP1R_SPI123SEL) 01051 #define RCC_SPI123CLKSOURCE_PLL (0x00000000U) 01052 #define RCC_SPI123CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0 01053 #define RCC_SPI123CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1 01054 #define RCC_SPI123CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1) 01055 #define RCC_SPI123CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2 01056 #else 01057 #define RCC_SPI123CLKSOURCE_PLL (0x00000000U) 01058 #define RCC_SPI123CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI123SEL_0 01059 #define RCC_SPI123CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI123SEL_1 01060 #define RCC_SPI123CLKSOURCE_PIN (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1) 01061 #define RCC_SPI123CLKSOURCE_CLKP RCC_CDCCIP1R_SPI123SEL_2 01062 #endif /* RCC_D2CCIP1R_SPI123SEL */ 01063 /** 01064 * @} 01065 */ 01066 01067 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source 01068 * @{ 01069 */ 01070 #define RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL 01071 #define RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 01072 #define RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 01073 #define RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN 01074 #define RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP 01075 01076 /** 01077 * @} 01078 */ 01079 01080 /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source 01081 * @{ 01082 */ 01083 #define RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL 01084 #define RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 01085 #define RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 01086 #define RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN 01087 #define RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP 01088 01089 /** 01090 * @} 01091 */ 01092 01093 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source 01094 * @{ 01095 */ 01096 #define RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL 01097 #define RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 01098 #define RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 01099 #define RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN 01100 #define RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP 01101 01102 /** 01103 * @} 01104 */ 01105 01106 /** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source 01107 * @{ 01108 */ 01109 #if defined(RCC_D2CCIP1R_SPI45SEL) 01110 #define RCC_SPI45CLKSOURCE_D2PCLK1 (0x00000000U) 01111 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1 01112 #define RCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0 01113 #define RCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1 01114 #define RCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1) 01115 #define RCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2 01116 #define RCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2) 01117 #else 01118 #define RCC_SPI45CLKSOURCE_CDPCLK1 (0x00000000U) 01119 /* aliases */ 01120 #define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */ 01121 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 01122 #define RCC_SPI45CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI45SEL_0 01123 #define RCC_SPI45CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI45SEL_1 01124 #define RCC_SPI45CLKSOURCE_HSI (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1) 01125 #define RCC_SPI45CLKSOURCE_CSI RCC_CDCCIP1R_SPI45SEL_2 01126 #define RCC_SPI45CLKSOURCE_HSE (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2) 01127 #endif /* RCC_D2CCIP1R_SPI45SEL */ 01128 /** 01129 * @} 01130 */ 01131 01132 /** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source 01133 * @{ 01134 */ 01135 #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1 01136 #define RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2 01137 #define RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3 01138 #define RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI 01139 #define RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI 01140 #define RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE 01141 01142 /** 01143 * @} 01144 */ 01145 01146 /** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source 01147 * @{ 01148 */ 01149 #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1 01150 #define RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2 01151 #define RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3 01152 #define RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI 01153 #define RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI 01154 #define RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE 01155 01156 /** 01157 * @} 01158 */ 01159 01160 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source 01161 * @{ 01162 */ 01163 #if defined(RCC_D3CCIPR_SPI6SEL) 01164 #define RCC_SPI6CLKSOURCE_D3PCLK1 (0x00000000U) 01165 #define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_D3PCLK1 01166 #define RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0 01167 #define RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1 01168 #define RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1) 01169 #define RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2 01170 #define RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2) 01171 #else 01172 #define RCC_SPI6CLKSOURCE_SRDPCLK4 (0x00000000U) 01173 /* alias */ 01174 #define RCC_SPI6CLKSOURCE_D3PCLK1 RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */ 01175 #define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_SRDPCLK4 01176 #define RCC_SPI6CLKSOURCE_PLL2 RCC_SRDCCIPR_SPI6SEL_0 01177 #define RCC_SPI6CLKSOURCE_PLL3 RCC_SRDCCIPR_SPI6SEL_1 01178 #define RCC_SPI6CLKSOURCE_HSI (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1) 01179 #define RCC_SPI6CLKSOURCE_CSI RCC_SRDCCIPR_SPI6SEL_2 01180 #define RCC_SPI6CLKSOURCE_HSE (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2) 01181 #define RCC_SPI6CLKSOURCE_PIN (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2) 01182 #endif /* RCC_D3CCIPR_SPI6SEL */ 01183 01184 /** 01185 * @} 01186 */ 01187 01188 01189 #if defined(SAI4_Block_A) 01190 /** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source 01191 * @{ 01192 */ 01193 #define RCC_SAI4ACLKSOURCE_PLL (0x00000000U) 01194 #define RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0 01195 #define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1 01196 #define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1) 01197 #define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2 01198 #if defined(RCC_VER_3_0) 01199 #define RCC_SAI4ACLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0) 01200 #endif /*RCC_VER_3_0*/ 01201 01202 /** 01203 * @} 01204 */ 01205 #endif /* SAI4_Block_A */ 01206 01207 01208 01209 #if defined(SAI4_Block_B) 01210 /** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source 01211 * @{ 01212 */ 01213 #define RCC_SAI4BCLKSOURCE_PLL (0x00000000U) 01214 #define RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0 01215 #define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1 01216 #define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1) 01217 #define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2 01218 #if defined(RCC_VER_3_0) 01219 #define RCC_SAI4BCLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0) 01220 #endif /* RCC_VER_3_0 */ 01221 01222 /** 01223 * @} 01224 */ 01225 #endif /* SAI4_Block_B */ 01226 01227 01228 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source 01229 * @{ 01230 */ 01231 #if defined(RCC_D2CCIP2R_LPTIM1SEL) 01232 #define RCC_LPTIM1CLKSOURCE_D2PCLK1 (0x00000000U) 01233 /* alias */ 01234 #define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_D2PCLK1 01235 #define RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0 01236 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1 01237 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1) 01238 #define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2 01239 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2) 01240 #else 01241 #define RCC_LPTIM1CLKSOURCE_CDPCLK1 (0x00000000U) 01242 /* alias */ 01243 #define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1 01244 #define RCC_LPTIM1CLKSOURCE_D2PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1 01245 #define RCC_LPTIM1CLKSOURCE_PLL2 RCC_CDCCIP2R_LPTIM1SEL_0 01246 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_CDCCIP2R_LPTIM1SEL_1 01247 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1) 01248 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CDCCIP2R_LPTIM1SEL_2 01249 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2) 01250 #endif /* RCC_D2CCIP2R_LPTIM1SEL */ 01251 01252 /** 01253 * @} 01254 */ 01255 01256 /** @defgroup RCCEx_LPTIM2_Clock_Source RCCEx LPTIM2 Clock Source 01257 * @{ 01258 */ 01259 #if defined(RCC_D3CCIPR_LPTIM2SEL) 01260 #define RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U) 01261 /* alias */ 01262 #define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_D3PCLK1 01263 #define RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0 01264 #define RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1 01265 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1) 01266 #define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2 01267 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2) 01268 #else 01269 #define RCC_LPTIM2CLKSOURCE_SRDPCLK4 (0x00000000U) 01270 /*alias*/ 01271 #define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_SRDPCLK4 01272 #define RCC_LPTIM2CLKSOURCE_D3PCLK1 RCC_LPTIM2CLKSOURCE_SRDPCLK4 01273 #define RCC_LPTIM2CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM2SEL_0 01274 #define RCC_LPTIM2CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM2SEL_1 01275 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1) 01276 #define RCC_LPTIM2CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM2SEL_2 01277 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2) 01278 #endif /* RCC_D3CCIPR_LPTIM2SEL */ 01279 /** 01280 * @} 01281 */ 01282 01283 /** @defgroup RCCEx_LPTIM345_Clock_Source RCCEx LPTIM3/4/5 Clock Source 01284 * @{ 01285 */ 01286 #if defined(RCC_D3CCIPR_LPTIM345SEL) 01287 #define RCC_LPTIM345CLKSOURCE_D3PCLK1 (0x00000000U) 01288 /* alias*/ 01289 #define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_D3PCLK1 01290 #define RCC_LPTIM345CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0 01291 #define RCC_LPTIM345CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1 01292 #define RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1) 01293 #define RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2 01294 #define RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2) 01295 #else 01296 #define RCC_LPTIM345CLKSOURCE_SRDPCLK4 (0x00000000U) 01297 /* alias */ 01298 #define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_SRDPCLK4 01299 #define RCC_LPTIM345CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_SRDPCLK4 01300 #define RCC_LPTIM345CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM3SEL_0 01301 #define RCC_LPTIM345CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM3SEL_1 01302 #define RCC_LPTIM345CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1) 01303 #define RCC_LPTIM345CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM3SEL_2 01304 #define RCC_LPTIM345CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2) 01305 #endif /* RCC_D3CCIPR_LPTIM345SEL */ 01306 /** 01307 * @} 01308 */ 01309 01310 /** @defgroup RCCEx_LPTIM3_Clock_Source RCCEx LPTIM3 Clock Source 01311 * @{ 01312 */ 01313 #define RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 01314 #define RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 01315 #define RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 01316 #define RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE 01317 #define RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI 01318 #define RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP 01319 01320 /** 01321 * @} 01322 */ 01323 #if defined(LPTIM4) 01324 /** @defgroup RCCEx_LPTIM4_Clock_Source RCCEx LPTIM4 Clock Source 01325 * @{ 01326 */ 01327 #define RCC_LPTIM4CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 01328 #define RCC_LPTIM4CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 01329 #define RCC_LPTIM4CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 01330 #define RCC_LPTIM4CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE 01331 #define RCC_LPTIM4CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI 01332 #define RCC_LPTIM4CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP 01333 /** 01334 * @} 01335 */ 01336 #endif /* LPTIM4 */ 01337 01338 #if defined(LPTIM5) 01339 /** @defgroup RCCEx_LPTIM5_Clock_Source RCCEx LPTIM5 Clock Source 01340 * @{ 01341 */ 01342 #define RCC_LPTIM5CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 01343 #define RCC_LPTIM5CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 01344 #define RCC_LPTIM5CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 01345 #define RCC_LPTIM5CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE 01346 #define RCC_LPTIM5CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI 01347 #define RCC_LPTIM5CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP 01348 01349 /** 01350 * @} 01351 */ 01352 #endif /* LPTIM5 */ 01353 01354 #if defined(QUADSPI) 01355 /** @defgroup RCCEx_QSPI_Clock_Source RCCEx QSPI Clock Source 01356 * @{ 01357 */ 01358 #define RCC_QSPICLKSOURCE_D1HCLK (0x00000000U) 01359 #define RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0 01360 #define RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1 01361 #define RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL 01362 01363 /** 01364 * @} 01365 */ 01366 #endif /* QUADSPI */ 01367 01368 01369 #if defined(OCTOSPI1) || defined(OCTOSPI2) 01370 /** @defgroup RCCEx_OSPI_Clock_Source RCCEx OSPI Clock Source 01371 * @{ 01372 */ 01373 01374 #if defined(RCC_CDCCIPR_OCTOSPISEL) 01375 #define RCC_OSPICLKSOURCE_CDHCLK (0x00000000U) 01376 /*aliases*/ 01377 #define RCC_OSPICLKSOURCE_D1HCLK RCC_OSPICLKSOURCE_CDHCLK 01378 #define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_CDHCLK 01379 #define RCC_OSPICLKSOURCE_PLL RCC_CDCCIPR_OCTOSPISEL_0 01380 #define RCC_OSPICLKSOURCE_PLL2 RCC_CDCCIPR_OCTOSPISEL_1 01381 #define RCC_OSPICLKSOURCE_CLKP RCC_CDCCIPR_OCTOSPISEL 01382 #else 01383 #define RCC_OSPICLKSOURCE_D1HCLK (0x00000000U) 01384 #define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_D1HCLK 01385 #define RCC_OSPICLKSOURCE_PLL RCC_D1CCIPR_OCTOSPISEL_0 01386 #define RCC_OSPICLKSOURCE_PLL2 RCC_D1CCIPR_OCTOSPISEL_1 01387 #define RCC_OSPICLKSOURCE_CLKP RCC_D1CCIPR_OCTOSPISEL 01388 #endif /* RCC_CDCCIPR_OCTOSPISEL */ 01389 01390 01391 /** 01392 * @} 01393 */ 01394 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ 01395 01396 #if defined(DSI) 01397 /** @defgroup RCCEx_DSI_Clock_Source RCCEx DSI Clock Source 01398 * @{ 01399 */ 01400 #define RCC_DSICLKSOURCE_PHY (0x00000000U) 01401 #define RCC_DSICLKSOURCE_PLL2 RCC_D1CCIPR_DSISEL 01402 01403 /** 01404 * @} 01405 */ 01406 #endif /* DSI */ 01407 01408 /** @defgroup RCCEx_FMC_Clock_Source RCCEx FMC Clock Source 01409 * @{ 01410 */ 01411 #if defined(RCC_D1CCIPR_FMCSEL) 01412 #define RCC_FMCCLKSOURCE_D1HCLK (0x00000000U) 01413 #define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_D1HCLK 01414 #define RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0 01415 #define RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1 01416 #define RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL 01417 #else 01418 #define RCC_FMCCLKSOURCE_CDHCLK (0x00000000U) 01419 #define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_CDHCLK 01420 /*alias*/ 01421 #define RCC_FMCCLKSOURCE_D1HCLK RCC_FMCCLKSOURCE_CDHCLK 01422 #define RCC_FMCCLKSOURCE_PLL RCC_CDCCIPR_FMCSEL_0 01423 #define RCC_FMCCLKSOURCE_PLL2 RCC_CDCCIPR_FMCSEL_1 01424 #define RCC_FMCCLKSOURCE_CLKP RCC_CDCCIPR_FMCSEL 01425 #endif /* RCC_D1CCIPR_FMCSEL */ 01426 /** 01427 * @} 01428 */ 01429 01430 #if defined(FDCAN1) || defined(FDCAN2) 01431 /** @defgroup RCCEx_FDCAN_Clock_Source RCCEx FDCAN Clock Source 01432 * @{ 01433 */ 01434 #if defined(RCC_D2CCIP1R_FDCANSEL) 01435 #define RCC_FDCANCLKSOURCE_HSE (0x00000000U) 01436 #define RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0 01437 #define RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1 01438 #else 01439 #define RCC_FDCANCLKSOURCE_HSE (0x00000000U) 01440 #define RCC_FDCANCLKSOURCE_PLL RCC_CDCCIP1R_FDCANSEL_0 01441 #define RCC_FDCANCLKSOURCE_PLL2 RCC_CDCCIP1R_FDCANSEL_1 01442 #endif /* D3_SRAM_BASE */ 01443 /** 01444 * @} 01445 */ 01446 #endif /*FDCAN1 || FDCAN2*/ 01447 01448 01449 /** @defgroup RCCEx_SDMMC_Clock_Source RCCEx SDMMC Clock Source 01450 * @{ 01451 */ 01452 #if defined(RCC_D1CCIPR_SDMMCSEL) 01453 #define RCC_SDMMCCLKSOURCE_PLL (0x00000000U) 01454 #define RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL 01455 #else 01456 #define RCC_SDMMCCLKSOURCE_PLL (0x00000000U) 01457 #define RCC_SDMMCCLKSOURCE_PLL2 RCC_CDCCIPR_SDMMCSEL 01458 #endif /* RCC_D1CCIPR_SDMMCSEL */ 01459 /** 01460 * @} 01461 */ 01462 01463 01464 /** @defgroup RCCEx_ADC_Clock_Source RCCEx ADC Clock Source 01465 * @{ 01466 */ 01467 #if defined(RCC_D3CCIPR_ADCSEL_0) 01468 #define RCC_ADCCLKSOURCE_PLL2 (0x00000000U) 01469 #define RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0 01470 #define RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1 01471 #else 01472 #define RCC_ADCCLKSOURCE_PLL2 (0x00000000U) 01473 #define RCC_ADCCLKSOURCE_PLL3 RCC_SRDCCIPR_ADCSEL_0 01474 #define RCC_ADCCLKSOURCE_CLKP RCC_SRDCCIPR_ADCSEL_1 01475 #endif /* RCC_D3CCIPR_ADCSEL_0 */ 01476 /** 01477 * @} 01478 */ 01479 01480 /** @defgroup RCCEx_SWPMI1_Clock_Source RCCEx SWPMI1 Clock Source 01481 * @{ 01482 */ 01483 #if defined(RCC_D2CCIP1R_SWPSEL) 01484 #define RCC_SWPMI1CLKSOURCE_D2PCLK1 (0x00000000U) 01485 #define RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL 01486 #else 01487 #define RCC_SWPMI1CLKSOURCE_CDPCLK1 (0x00000000U) 01488 /* alias */ 01489 #define RCC_SWPMI1CLKSOURCE_D2PCLK1 RCC_SWPMI1CLKSOURCE_CDPCLK1 01490 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CDCCIP1R_SWPSEL 01491 #endif /* RCC_D2CCIP1R_SWPSEL */ 01492 /** 01493 * @} 01494 */ 01495 01496 /** @defgroup RCCEx_DFSDM1_Clock_Source RCCEx DFSDM1 Clock Source 01497 * @{ 01498 */ 01499 #if defined(RCC_D2CCIP1R_DFSDM1SEL) 01500 #define RCC_DFSDM1CLKSOURCE_D2PCLK1 (0x00000000U) 01501 #define RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL 01502 #else 01503 #define RCC_DFSDM1CLKSOURCE_CDPCLK1 (0x00000000U) 01504 /* alias */ 01505 #define RCC_DFSDM1CLKSOURCE_D2PCLK1 RCC_DFSDM1CLKSOURCE_CDPCLK1 01506 #define RCC_DFSDM1CLKSOURCE_SYS RCC_CDCCIP1R_DFSDM1SEL 01507 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 01508 /** 01509 * @} 01510 */ 01511 01512 #if defined(DFSDM2_BASE) 01513 /** @defgroup RCCEx_DFSDM2_Clock_Source RCCEx DFSDM2 Clock Source 01514 * @{ 01515 */ 01516 #define RCC_DFSDM2CLKSOURCE_SRDPCLK4 (0x00000000U) 01517 /* alias */ 01518 #define RCC_DFSDM2CLKSOURCE_SRDPCLK1 RCC_DFSDM2CLKSOURCE_SRDPCLK4 01519 #define RCC_DFSDM2CLKSOURCE_SYS RCC_SRDCCIPR_DFSDM2SEL 01520 /** 01521 * @} 01522 */ 01523 #endif /* DFSDM2 */ 01524 01525 /** @defgroup RCCEx_SPDIFRX_Clock_Source RCCEx SPDIFRX Clock Source 01526 * @{ 01527 */ 01528 #if defined(RCC_D2CCIP1R_SPDIFSEL_0) 01529 #define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U) 01530 #define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0 01531 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1 01532 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL 01533 #else 01534 #define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U) 01535 #define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_CDCCIP1R_SPDIFSEL_0 01536 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_CDCCIP1R_SPDIFSEL_1 01537 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_CDCCIP1R_SPDIFSEL 01538 #endif /* RCC_D2CCIP1R_SPDIFSEL_0 */ 01539 /** 01540 * @} 01541 */ 01542 01543 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source 01544 * @{ 01545 */ 01546 #if defined(RCC_D2CCIP2R_CECSEL_0) 01547 #define RCC_CECCLKSOURCE_LSE (0x00000000U) 01548 #define RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0 01549 #define RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1 01550 #else 01551 #define RCC_CECCLKSOURCE_LSE (0x00000000U) 01552 #define RCC_CECCLKSOURCE_LSI RCC_CDCCIP2R_CECSEL_0 01553 #define RCC_CECCLKSOURCE_CSI RCC_CDCCIP2R_CECSEL_1 01554 #endif /* RCC_D2CCIP2R_CECSEL_0 */ 01555 /** 01556 * @} 01557 */ 01558 01559 01560 /** @defgroup RCCEx_CLKP_Clock_Source RCCEx CLKP Clock Source 01561 * @{ 01562 */ 01563 #if defined(RCC_D1CCIPR_CKPERSEL_0) 01564 #define RCC_CLKPSOURCE_HSI (0x00000000U) 01565 #define RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0 01566 #define RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1 01567 #else 01568 #define RCC_CLKPSOURCE_HSI (0x00000000U) 01569 #define RCC_CLKPSOURCE_CSI RCC_CDCCIPR_CKPERSEL_0 01570 #define RCC_CLKPSOURCE_HSE RCC_CDCCIPR_CKPERSEL_1 01571 #endif /* RCC_D1CCIPR_CKPERSEL_0 */ 01572 /** 01573 * @} 01574 */ 01575 01576 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection 01577 * @{ 01578 */ 01579 #define RCC_TIMPRES_DESACTIVATED (0x00000000U) 01580 #define RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE 01581 01582 /** 01583 * @} 01584 */ 01585 01586 #if defined(DUAL_CORE) 01587 01588 /** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx 01589 * @{ 01590 */ 01591 #define RCC_BOOT_C1 RCC_GCR_BOOT_C1 01592 #define RCC_BOOT_C2 RCC_GCR_BOOT_C2 01593 01594 /** 01595 * @} 01596 */ 01597 #endif /*DUAL_CORE*/ 01598 01599 #if defined(DUAL_CORE) 01600 /** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx 01601 * @{ 01602 */ 01603 #define RCC_WWDG1 RCC_GCR_WW1RSC 01604 #define RCC_WWDG2 RCC_GCR_WW2RSC 01605 01606 /** 01607 * @} 01608 */ 01609 01610 #else 01611 01612 /** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx 01613 * @{ 01614 */ 01615 #define RCC_WWDG1 RCC_GCR_WW1RSC 01616 01617 /** 01618 * @} 01619 */ 01620 01621 #endif /*DUAL_CORE*/ 01622 01623 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 01624 * @{ 01625 */ 01626 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */ 01627 /** 01628 * @} 01629 */ 01630 01631 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 01632 * @{ 01633 */ 01634 #define RCC_CRS_NONE (0x00000000U) 01635 #define RCC_CRS_TIMEOUT (0x00000001U) 01636 #define RCC_CRS_SYNCOK (0x00000002U) 01637 #define RCC_CRS_SYNCWARN (0x00000004U) 01638 #define RCC_CRS_SYNCERR (0x00000008U) 01639 #define RCC_CRS_SYNCMISS (0x00000010U) 01640 #define RCC_CRS_TRIMOVF (0x00000020U) 01641 /** 01642 * @} 01643 */ 01644 01645 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 01646 * @{ 01647 */ 01648 #define RCC_CRS_SYNC_SOURCE_PIN (0x00000000U) /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only */ 01649 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 01650 #define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB1 SOF (default) */ 01651 #define RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0) /*!< Synchro Signal source USB2 SOF */ 01652 01653 01654 /** 01655 * @} 01656 */ 01657 01658 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 01659 * @{ 01660 */ 01661 #define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ 01662 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 01663 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 01664 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 01665 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 01666 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 01667 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 01668 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 01669 /** 01670 * @} 01671 */ 01672 01673 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 01674 * @{ 01675 */ 01676 #define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ 01677 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 01678 /** 01679 * @} 01680 */ 01681 01682 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 01683 * @{ 01684 */ 01685 #define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 01686 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 01687 /** 01688 * @} 01689 */ 01690 01691 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 01692 * @{ 01693 */ 01694 #define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ 01695 /** 01696 * @} 01697 */ 01698 01699 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 01700 * @{ 01701 */ 01702 #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. 01703 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 01704 corresponds to a higher output frequency */ 01705 /** 01706 * @} 01707 */ 01708 01709 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 01710 * @{ 01711 */ 01712 #define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ 01713 #define RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ 01714 /** 01715 * @} 01716 */ 01717 01718 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 01719 * @{ 01720 */ 01721 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 01722 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 01723 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 01724 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 01725 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 01726 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 01727 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 01728 01729 /** 01730 * @} 01731 */ 01732 01733 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 01734 * @{ 01735 */ 01736 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 01737 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 01738 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 01739 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 01740 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 01741 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 01742 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 01743 01744 /** 01745 * @} 01746 */ 01747 01748 /** 01749 * @} 01750 */ 01751 01752 01753 01754 /* Exported macro ------------------------------------------------------------*/ 01755 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 01756 * @{ 01757 */ 01758 01759 /** @brief Macros to enable or disable PLL2. 01760 * @note After enabling PLL2, the application software should wait on 01761 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 01762 * be used as kernel clock source. 01763 * @note PLL2 is disabled by hardware when entering STOP and STANDBY modes. 01764 */ 01765 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) 01766 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) 01767 01768 /** 01769 * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) 01770 * @note Enabling/disabling those Clocks can be done only when the PLL2 is disabled, 01771 * This is mainly used to save Power. 01772 * @param __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted 01773 * This parameter can be one of the following values: 01774 * @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 01775 * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 01776 * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 01777 * 01778 * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. 01779 * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. 01780 * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. 01781 * 01782 * @retval None 01783 */ 01784 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) 01785 01786 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) 01787 01788 /** 01789 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO 01790 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 01791 * @retval None 01792 */ 01793 #define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) 01794 01795 #define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) 01796 01797 /** 01798 * @brief Macro to configures the PLL2 multiplication and division factors. 01799 * @note This function must be used only when PLL2 is disabled. 01800 * 01801 * @param __PLL2M__ specifies the division factor for PLL2 VCO input clock 01802 * This parameter must be a number between 1 and 63. 01803 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 01804 * frequency ranges from 1 to 16 MHz. 01805 * 01806 * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock 01807 * This parameter must be a number between 4 and 512 or between 8 and 420(*). 01808 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 01809 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 01810 * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) 01811 * 01812 * @param __PLL2P__ specifies the division factor for peripheral kernel clocks 01813 * This parameter must be a number between 1 and 128. 01814 * 01815 * @param __PLL2Q__ specifies the division factor for peripheral kernel clocks 01816 * This parameter must be a number between 1 and 128. 01817 * 01818 * @param __PLL2R__ specifies the division factor for peripheral kernel clocks 01819 * This parameter must be a number between 1 and 128. 01820 * 01821 * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) 01822 * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 01823 * value to __PLL2P__, __PLL2Q__ or __PLL2R__ parameters. 01824 * @retval None 01825 * 01826 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 01827 */ 01828 01829 #define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \ 01830 do{ \ 01831 MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \ 01832 WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \ 01833 ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \ 01834 } while(0) 01835 01836 /** 01837 * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor 01838 * 01839 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO 01840 * 01841 * @param __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO 01842 * It should be a value between 0 and 8191 01843 * @note Warning: the software has to set correctly these bits to insure that the VCO 01844 * output frequency is between its valid frequency range, which is: 01845 * 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 01846 * 150 to 420 MHz if PLL2VCOSEL = 1. 01847 * 01848 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 01849 * 01850 * @retval None 01851 */ 01852 #define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \ 01853 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) 01854 01855 /** @brief Macro to select the PLL2 reference frequency range. 01856 * @param __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range 01857 * This parameter can be one of the following values: 01858 * @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz 01859 * @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz 01860 * @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz 01861 * @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz 01862 * @retval None 01863 */ 01864 #define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \ 01865 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) 01866 01867 01868 /** @brief Macro to select the PLL2 reference frequency range. 01869 * @param __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range 01870 * This parameter can be one of the following values: 01871 * @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) 01872 * @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz 01873 * 01874 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 01875 * 01876 * @retval None 01877 */ 01878 #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \ 01879 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) 01880 01881 /** @brief Macros to enable or disable the main PLL3. 01882 * @note After enabling PLL3, the application software should wait on 01883 * PLL3RDY flag to be set indicating that PLL3 clock is stable and can 01884 * be used as kernel clock source. 01885 * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. 01886 */ 01887 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) 01888 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) 01889 01890 /** 01891 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO 01892 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 01893 * @retval None 01894 */ 01895 #define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) 01896 01897 #define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) 01898 01899 /** 01900 * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) 01901 * @note Enabling/disabling those Clocks can be done only when the PLL3 is disabled, 01902 * This is mainly used to save Power. 01903 * @param __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted 01904 * This parameter can be one of the following values: 01905 * @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 01906 * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 01907 * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 01908 * 01909 * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. 01910 * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. 01911 * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. 01912 * 01913 * @retval None 01914 */ 01915 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) 01916 01917 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) 01918 01919 /** 01920 * @brief Macro to configures the PLL3 multiplication and division factors. 01921 * @note This function must be used only when PLL3 is disabled. 01922 * 01923 * @param __PLL3M__ specifies the division factor for PLL3 VCO input clock 01924 * This parameter must be a number between 1 and 63. 01925 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 01926 * frequency ranges from 1 to 16 MHz. 01927 * 01928 * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock 01929 * This parameter must be a number between 4 and 512. 01930 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 01931 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 01932 * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) 01933 * 01934 * @param __PLL3P__ specifies the division factor for peripheral kernel clocks 01935 * This parameter must be a number between 2 and 128 (where odd numbers not allowed) 01936 * 01937 * @param __PLL3Q__ specifies the division factor for peripheral kernel clocks 01938 * This parameter must be a number between 1 and 128 01939 * 01940 * @param __PLL3R__ specifies the division factor for peripheral kernel clocks 01941 * This parameter must be a number between 1 and 128 01942 * 01943 * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) 01944 * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 01945 * value to __PLL3P__, __PLL3Q__ or __PLL3R__ parameters. 01946 * @retval None 01947 * 01948 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 01949 */ 01950 01951 #define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \ 01952 do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \ 01953 WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \ 01954 ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \ 01955 } while(0) 01956 01957 01958 01959 /** 01960 * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor 01961 * 01962 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO 01963 * 01964 * @param __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO 01965 * It should be a value between 0 and 8191 01966 * @note Warning: the software has to set correctly these bits to insure that the VCO 01967 * output frequency is between its valid frequency range, which is: 01968 * 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 01969 * 150 to 420 MHz if PLL3VCOSEL = 1. 01970 * 01971 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 01972 * 01973 * @retval None 01974 */ 01975 #define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) 01976 01977 /** @brief Macro to select the PLL3 reference frequency range. 01978 * @param __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range 01979 * This parameter can be one of the following values: 01980 * @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz 01981 * @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz 01982 * @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz 01983 * @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz 01984 * @retval None 01985 */ 01986 #define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \ 01987 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) 01988 01989 01990 /** @brief Macro to select the PLL3 reference frequency range. 01991 * @param __RCC_PLL3VCORange__ specifies the PLL1 input frequency range 01992 * This parameter can be one of the following values: 01993 * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) 01994 * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz 01995 * 01996 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 01997 * 01998 * @retval None 01999 */ 02000 #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \ 02001 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) 02002 /** 02003 * @brief Macro to Configure the SAI1 clock source. 02004 * @param __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived 02005 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 02006 * This parameter can be one of the following values: 02007 * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL 02008 * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 02009 * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 02010 * @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC 02011 * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock 02012 * @retval None 02013 */ 02014 #if defined(RCC_D2CCIP1R_SAI1SEL) 02015 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ 02016 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) 02017 #else 02018 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ 02019 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) 02020 #endif /* RCC_D2CCIP1R_SAI1SEL */ 02021 02022 /** @brief Macro to get the SAI1 clock source. 02023 * @retval The clock source can be one of the following values: 02024 * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL 02025 * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 02026 * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 02027 * @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP 02028 * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock 02029 */ 02030 #if defined(RCC_D2CCIP1R_SAI1SEL) 02031 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL))) 02032 #else 02033 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL))) 02034 #endif /* RCC_D2CCIP1R_SAI1SEL */ 02035 02036 /** 02037 * @brief Macro to Configure the SPDIFRX clock source. 02038 * @param __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived 02039 * from system PLL, PLL2, PLL3, or internal OSC clock 02040 * This parameter can be one of the following values: 02041 * @arg RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL 02042 * @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2 02043 * @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3 02044 * @arg RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI 02045 * @retval None 02046 */ 02047 #if defined(RCC_D2CCIP1R_SPDIFSEL) 02048 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ 02049 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) 02050 #else 02051 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ 02052 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) 02053 #endif /* RCC_D2CCIP1R_SPDIFSEL */ 02054 02055 /** 02056 * @brief Macro to get the SPDIFRX clock source. 02057 * @retval None 02058 */ 02059 #if defined(RCC_D2CCIP1R_SPDIFSEL) 02060 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL))) 02061 #else 02062 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL))) 02063 #endif /* RCC_D2CCIP1R_SPDIFSEL */ 02064 02065 #if defined(SAI3) 02066 /** 02067 * @brief Macro to Configure the SAI2/3 clock source. 02068 * @param __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived 02069 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 02070 * This parameter can be one of the following values: 02071 * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL 02072 * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 02073 * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 02074 * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP 02075 * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock 02076 * @retval None 02077 */ 02078 #define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\ 02079 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__)) 02080 02081 /** @brief Macro to get the SAI2/3 clock source. 02082 * @retval The clock source can be one of the following values: 02083 * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL 02084 * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 02085 * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 02086 * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP 02087 * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock 02088 */ 02089 #define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL))) 02090 02091 /** 02092 * @brief Macro to Configure the SAI2 clock source. 02093 * @param __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived 02094 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 02095 * This parameter can be one of the following values: 02096 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL 02097 * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 02098 * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 02099 * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP 02100 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock 02101 * @retval None 02102 */ 02103 #define __HAL_RCC_SAI2_CONFIG __HAL_RCC_SAI23_CONFIG 02104 02105 /** @brief Macro to get the SAI2 clock source. 02106 * @retval The clock source can be one of the following values: 02107 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL 02108 * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 02109 * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 02110 * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP 02111 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock 02112 */ 02113 #define __HAL_RCC_GET_SAI2_SOURCE __HAL_RCC_GET_SAI23_SOURCE 02114 02115 /** 02116 * @brief Macro to Configure the SAI3 clock source. 02117 * @param __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived 02118 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 02119 * This parameter can be one of the following values: 02120 * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL 02121 * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 02122 * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 02123 * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP 02124 * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock 02125 * @retval None 02126 */ 02127 #define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG 02128 02129 /** @brief Macro to get the SAI3 clock source. 02130 * @retval The clock source can be one of the following values: 02131 * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL 02132 * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 02133 * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 02134 * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP 02135 * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock 02136 */ 02137 #define __HAL_RCC_GET_SAI3_SOURCE __HAL_RCC_GET_SAI23_SOURCE 02138 #endif /* SAI3 */ 02139 02140 #if defined(RCC_CDCCIP1R_SAI2ASEL) 02141 /** 02142 * @brief Macro to Configure the SAI2A clock source. 02143 * @param __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived 02144 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 02145 * This parameter can be one of the following values: 02146 * @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL 02147 * @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2 02148 * @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3 02149 * @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock = CLKP 02150 * @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock 02151 * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock 02152 * @retval None 02153 */ 02154 #define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\ 02155 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__)) 02156 02157 /** @brief Macro to get the SAI2A clock source. 02158 * @retval The clock source can be one of the following values: 02159 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL 02160 * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2 02161 * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3 02162 * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock = CLKP 02163 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock 02164 * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock 02165 */ 02166 #define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL))) 02167 #endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */ 02168 02169 #if defined(RCC_CDCCIP1R_SAI2BSEL) 02170 /** 02171 * @brief Macro to Configure the SAI2B clock source. 02172 * @param __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived 02173 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 02174 * This parameter can be one of the following values: 02175 * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL 02176 * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 02177 * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 02178 * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP 02179 * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock 02180 * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock 02181 * @retval None 02182 */ 02183 #define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\ 02184 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__)) 02185 02186 /** @brief Macro to get the SAI2B clock source. 02187 * @retval The clock source can be one of the following values: 02188 * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL 02189 * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 02190 * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 02191 * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP 02192 * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock 02193 * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock 02194 */ 02195 #define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL))) 02196 #endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */ 02197 02198 02199 #if defined(SAI4_Block_A) 02200 /** 02201 * @brief Macro to Configure the SAI4A clock source. 02202 * @param __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived 02203 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 02204 * This parameter can be one of the following values: 02205 * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL 02206 * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2 02207 * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3 02208 * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock = CLKP 02209 * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock 02210 * @retval None 02211 */ 02212 #define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\ 02213 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__)) 02214 02215 /** @brief Macro to get the SAI4A clock source. 02216 * @retval The clock source can be one of the following values: 02217 * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL 02218 * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2 02219 * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3 02220 * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock = CLKP 02221 * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock 02222 */ 02223 #define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL))) 02224 #endif /* SAI4_Block_A */ 02225 02226 #if defined(SAI4_Block_B) 02227 /** 02228 * @brief Macro to Configure the SAI4B clock source. 02229 * @param __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived 02230 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 02231 * This parameter can be one of the following values: 02232 * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL 02233 * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 02234 * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 02235 * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP 02236 * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock 02237 * @retval None 02238 */ 02239 #define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\ 02240 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__)) 02241 02242 /** @brief Macro to get the SAI4B clock source. 02243 * @retval The clock source can be one of the following values: 02244 * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL 02245 * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 02246 * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 02247 * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP 02248 * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock 02249 */ 02250 #define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL))) 02251 #endif /* SAI4_Block_B */ 02252 02253 /** @brief macro to configure the I2C1/2/3/5* clock (I2C123CLK). 02254 * 02255 * @param __I2C1235CLKSource__ specifies the I2C1/2/3/5* clock source. 02256 * This parameter can be one of the following values: 02257 * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock 02258 * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock 02259 * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock 02260 * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock 02261 * 02262 * (**): Available on stm32h72xxx and stm32h73xxx family lines. 02263 */ 02264 #if defined(RCC_D2CCIP2R_I2C123SEL) 02265 #define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ 02266 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) 02267 #elif defined(RCC_CDCCIP2R_I2C123SEL) 02268 #define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ 02269 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) 02270 #else /* RCC_D2CCIP2R_I2C1235SEL */ 02271 #define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) \ 02272 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__)) 02273 /* alias */ 02274 #define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG 02275 #endif /* RCC_D2CCIP2R_I2C123SEL */ 02276 02277 /** @brief macro to get the I2C1/2/3/5* clock source. 02278 * @retval The clock source can be one of the following values: 02279 * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock 02280 * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock 02281 * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock 02282 * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock 02283 * 02284 * (**): Available on stm32h72xxx and stm32h73xxx family lines. 02285 */ 02286 #if defined(RCC_D2CCIP2R_I2C123SEL) 02287 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) 02288 #elif defined(RCC_CDCCIP2R_I2C123SEL) 02289 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL))) 02290 #else /* RCC_D2CCIP2R_I2C1235SEL */ 02291 #define __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL))) 02292 /* alias */ 02293 #define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 02294 #endif /* RCC_D2CCIP2R_I2C123SEL */ 02295 02296 /** @brief macro to configure the I2C1 clock (I2C1CLK). 02297 * 02298 * @param __I2C1CLKSource__ specifies the I2C1 clock source. 02299 * This parameter can be one of the following values: 02300 * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock 02301 * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock 02302 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock 02303 * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock 02304 */ 02305 #if defined(I2C5) 02306 #define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG 02307 #else 02308 #define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG 02309 #endif /*I2C5*/ 02310 02311 /** @brief macro to get the I2C1 clock source. 02312 * @retval The clock source can be one of the following values: 02313 * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock 02314 * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock 02315 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock 02316 * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock 02317 */ 02318 #if defined(I2C5) 02319 #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 02320 #else 02321 #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE 02322 #endif /*I2C5*/ 02323 02324 /** @brief macro to configure the I2C2 clock (I2C2CLK). 02325 * 02326 * @param __I2C2CLKSource__ specifies the I2C2 clock source. 02327 * This parameter can be one of the following values: 02328 * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock 02329 * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock 02330 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock 02331 * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock 02332 */ 02333 #if defined(I2C5) 02334 #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG 02335 #else 02336 #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG 02337 #endif /*I2C5*/ 02338 02339 /** @brief macro to get the I2C2 clock source. 02340 * @retval The clock source can be one of the following values: 02341 * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock 02342 * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock 02343 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock 02344 * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock 02345 */ 02346 #if defined(I2C5) 02347 #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 02348 #else 02349 #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE 02350 #endif /*I2C5*/ 02351 02352 /** @brief macro to configure the I2C3 clock (I2C3CLK). 02353 * 02354 * @param __I2C3CLKSource__ specifies the I2C3 clock source. 02355 * This parameter can be one of the following values: 02356 * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock 02357 * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock 02358 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock 02359 * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock 02360 */ 02361 #if defined(I2C5) 02362 #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG 02363 #else 02364 #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG 02365 #endif /*I2C5*/ 02366 02367 /** @brief macro to get the I2C3 clock source. 02368 * @retval The clock source can be one of the following values: 02369 * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock 02370 * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock 02371 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock 02372 * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock 02373 */ 02374 #if defined(I2C5) 02375 #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 02376 #else 02377 #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE 02378 #endif /*I2C5*/ 02379 02380 /** @brief macro to configure the I2C4 clock (I2C4CLK). 02381 * 02382 * @param __I2C4CLKSource__ specifies the I2C4 clock source. 02383 * This parameter can be one of the following values: 02384 * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock 02385 * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock 02386 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock 02387 * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock 02388 */ 02389 #if defined(RCC_D3CCIPR_I2C4SEL) 02390 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ 02391 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) 02392 #else 02393 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ 02394 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) 02395 #endif /* RCC_D3CCIPR_I2C4SEL */ 02396 02397 /** @brief macro to get the I2C4 clock source. 02398 * @retval The clock source can be one of the following values: 02399 * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock 02400 * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock 02401 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock 02402 * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock 02403 */ 02404 #if defined(RCC_D3CCIPR_I2C4SEL) 02405 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL))) 02406 #else 02407 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL))) 02408 #endif /* RCC_D3CCIPR_I2C4SEL */ 02409 02410 #if defined(I2C5) 02411 /** @brief macro to configure the I2C5 clock (I2C5CLK). 02412 * 02413 * @param __I2C5CLKSource__ specifies the I2C5 clock source. 02414 * This parameter can be one of the following values: 02415 * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C5 clock 02416 * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock 02417 * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock 02418 * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock 02419 */ 02420 #define __HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG 02421 #endif /* I2C5 */ 02422 02423 #if defined(I2C5) 02424 /** @brief macro to get the I2C5 clock source. 02425 * @retval The clock source can be one of the following values: 02426 * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK5 selected as I2C5 clock 02427 * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock 02428 * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock 02429 * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock 02430 */ 02431 #define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 02432 #endif /* I2C5 */ 02433 02434 /** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK). 02435 * 02436 * @param __USART16910CLKSource__ specifies the USART1/6/9* /10* clock source. 02437 * This parameter can be one of the following values: 02438 * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock 02439 * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock 02440 * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock 02441 * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock 02442 * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock 02443 * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock 02444 * 02445 * (*) : Available on some STM32H7 lines only. 02446 */ 02447 #if defined(RCC_D2CCIP2R_USART16SEL) 02448 #define __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) \ 02449 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__)) 02450 #elif defined(RCC_CDCCIP2R_USART16910SEL) 02451 #define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ 02452 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) 02453 /* alias */ 02454 #define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG 02455 #else /* RCC_D2CCIP2R_USART16910SEL */ 02456 #define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ 02457 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) 02458 /* alias */ 02459 #define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG 02460 #endif /* RCC_D2CCIP2R_USART16SEL */ 02461 02462 /** @brief macro to get the USART1/6/9* /10* clock source. 02463 * @retval The clock source can be one of the following values: 02464 * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock 02465 * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock 02466 * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock 02467 * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock 02468 * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock 02469 * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock 02470 * 02471 * (*) : Available on some STM32H7 lines only. 02472 */ 02473 #if defined(RCC_D2CCIP2R_USART16SEL) 02474 #define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) 02475 #elif defined(RCC_CDCCIP2R_USART16910SEL) 02476 #define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL))) 02477 /* alias*/ 02478 #define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE 02479 #else /* RCC_D2CCIP2R_USART16910SEL */ 02480 #define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL))) 02481 /* alias */ 02482 #define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE 02483 #endif /* RCC_D2CCIP2R_USART16SEL */ 02484 02485 /** @brief macro to configure the USART234578 clock (USART234578CLK). 02486 * 02487 * @param __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source. 02488 * This parameter can be one of the following values: 02489 * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock 02490 * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock 02491 * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock 02492 * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock 02493 * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock 02494 * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock 02495 */ 02496 #if defined(RCC_D2CCIP2R_USART28SEL) 02497 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ 02498 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__)) 02499 #else 02500 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ 02501 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__)) 02502 #endif /* RCC_D2CCIP2R_USART28SEL */ 02503 02504 /** @brief macro to get the USART2/3/4/5/7/8 clock source. 02505 * @retval The clock source can be one of the following values: 02506 * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock 02507 * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock 02508 * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock 02509 * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock 02510 * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock 02511 * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock 02512 */ 02513 #if defined(RCC_D2CCIP2R_USART28SEL) 02514 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) 02515 #else 02516 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL))) 02517 #endif /* RCC_D2CCIP2R_USART28SEL */ 02518 02519 /** @brief macro to configure the USART1 clock (USART1CLK). 02520 * 02521 * @param __USART1CLKSource__ specifies the USART1 clock source. 02522 * This parameter can be one of the following values: 02523 * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock 02524 * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock 02525 * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock 02526 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock 02527 * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock 02528 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock 02529 */ 02530 #define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG 02531 02532 /** @brief macro to get the USART1 clock source. 02533 * @retval The clock source can be one of the following values: 02534 * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock 02535 * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock 02536 * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock 02537 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock 02538 * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock 02539 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock 02540 */ 02541 #define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE 02542 02543 /** @brief macro to configure the USART2 clock (USART2CLK). 02544 * 02545 * @param __USART2CLKSource__ specifies the USART2 clock source. 02546 * This parameter can be one of the following values: 02547 * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock 02548 * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock 02549 * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock 02550 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock 02551 * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock 02552 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock 02553 */ 02554 #define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG 02555 02556 /** @brief macro to get the USART2 clock source. 02557 * @retval The clock source can be one of the following values: 02558 * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock 02559 * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock 02560 * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock 02561 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock 02562 * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock 02563 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock 02564 */ 02565 #define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE 02566 02567 /** @brief macro to configure the USART3 clock (USART3CLK). 02568 * 02569 * @param __USART3CLKSource__ specifies the USART3 clock source. 02570 * This parameter can be one of the following values: 02571 * @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock 02572 * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock 02573 * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock 02574 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock 02575 * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock 02576 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock 02577 */ 02578 #define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG 02579 02580 /** @brief macro to get the USART3 clock source. 02581 * @retval The clock source can be one of the following values: 02582 * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock 02583 * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock 02584 * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock 02585 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock 02586 * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock 02587 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock 02588 */ 02589 #define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE 02590 02591 /** @brief macro to configure the UART4 clock (UART4CLK). 02592 * 02593 * @param __UART4CLKSource__ specifies the UART4 clock source. 02594 * This parameter can be one of the following values: 02595 * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock 02596 * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock 02597 * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock 02598 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock 02599 * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock 02600 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock 02601 */ 02602 #define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG 02603 02604 /** @brief macro to get the UART4 clock source. 02605 * @retval The clock source can be one of the following values: 02606 * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock 02607 * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock 02608 * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock 02609 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock 02610 * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock 02611 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock 02612 */ 02613 #define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE 02614 02615 /** @brief macro to configure the UART5 clock (UART5CLK). 02616 * 02617 * @param __UART5CLKSource__ specifies the UART5 clock source. 02618 * This parameter can be one of the following values: 02619 * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock 02620 * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock 02621 * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock 02622 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock 02623 * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock 02624 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock 02625 */ 02626 #define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG 02627 02628 /** @brief macro to get the UART5 clock source. 02629 * @retval The clock source can be one of the following values: 02630 * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock 02631 * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock 02632 * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock 02633 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock 02634 * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock 02635 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock 02636 */ 02637 #define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE 02638 02639 /** @brief macro to configure the USART6 clock (USART6CLK). 02640 * 02641 * @param __USART6CLKSource__ specifies the USART6 clock source. 02642 * This parameter can be one of the following values: 02643 * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock 02644 * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock 02645 * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock 02646 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 02647 * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock 02648 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock 02649 */ 02650 #define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG 02651 02652 /** @brief macro to get the USART6 clock source. 02653 * @retval The clock source can be one of the following values: 02654 * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock 02655 * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock 02656 * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock 02657 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 02658 * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock 02659 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock 02660 */ 02661 #define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE 02662 02663 /** @brief macro to configure the UART5 clock (UART7CLK). 02664 * 02665 * @param __UART7CLKSource__ specifies the UART7 clock source. 02666 * This parameter can be one of the following values: 02667 * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock 02668 * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock 02669 * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock 02670 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock 02671 * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock 02672 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock 02673 */ 02674 #define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG 02675 02676 /** @brief macro to get the UART7 clock source. 02677 * @retval The clock source can be one of the following values: 02678 * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock 02679 * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock 02680 * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock 02681 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock 02682 * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock 02683 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock 02684 */ 02685 #define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE 02686 02687 /** @brief macro to configure the UART8 clock (UART8CLK). 02688 * 02689 * @param __UART8CLKSource__ specifies the UART8 clock source. 02690 * This parameter can be one of the following values: 02691 * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock 02692 * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock 02693 * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock 02694 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock 02695 * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock 02696 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock 02697 */ 02698 #define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG 02699 02700 /** @brief macro to get the UART8 clock source. 02701 * @retval The clock source can be one of the following values: 02702 * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock 02703 * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock 02704 * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock 02705 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock 02706 * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock 02707 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock 02708 */ 02709 #define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE 02710 02711 #if defined(UART9) 02712 /** @brief macro to configure the UART9 clock (UART9CLK). 02713 * 02714 * @param __UART8CLKSource__ specifies the UART8 clock source. 02715 * This parameter can be one of the following values: 02716 * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock 02717 * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock 02718 * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock 02719 * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock 02720 * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock 02721 * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock 02722 */ 02723 #define __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG 02724 02725 /** @brief macro to get the UART9 clock source. 02726 * @retval The clock source can be one of the following values: 02727 * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock 02728 * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock 02729 * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock 02730 * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock 02731 * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock 02732 * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock 02733 */ 02734 #define __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE 02735 #endif /* UART9 */ 02736 02737 #if defined(USART10) 02738 /** @brief macro to configure the USART10 clock (USART10CLK). 02739 * 02740 * @param __UART8CLKSource__ specifies the UART8 clock source. 02741 * This parameter can be one of the following values: 02742 * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock 02743 * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock 02744 * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock 02745 * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock 02746 * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock 02747 * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock 02748 */ 02749 #define __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG 02750 02751 /** @brief macro to get the USART10 clock source. 02752 * @retval The clock source can be one of the following values: 02753 * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock 02754 * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock 02755 * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock 02756 * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock 02757 * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock 02758 * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock 02759 */ 02760 #define __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE 02761 #endif /* USART10 */ 02762 02763 /** @brief macro to configure the LPUART1 clock (LPUART1CLK). 02764 * 02765 * @param __LPUART1CLKSource__ specifies the LPUART1 clock source. 02766 * This parameter can be one of the following values: 02767 * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock 02768 * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock 02769 * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock 02770 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock 02771 * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock 02772 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock 02773 */ 02774 #if defined (RCC_D3CCIPR_LPUART1SEL) 02775 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ 02776 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) 02777 #else 02778 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ 02779 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) 02780 #endif /* RCC_D3CCIPR_LPUART1SEL */ 02781 02782 /** @brief macro to get the LPUART1 clock source. 02783 * @retval The clock source can be one of the following values: 02784 * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock 02785 * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock 02786 * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock 02787 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock 02788 * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock 02789 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock 02790 */ 02791 #if defined (RCC_D3CCIPR_LPUART1SEL) 02792 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL))) 02793 #else 02794 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL))) 02795 #endif /* RCC_D3CCIPR_LPUART1SEL */ 02796 02797 /** @brief macro to configure the LPTIM1 clock source. 02798 * 02799 * @param __LPTIM1CLKSource__ specifies the LPTIM1 clock source. 02800 * This parameter can be one of the following values: 02801 * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock 02802 * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock 02803 * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock 02804 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 02805 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock 02806 * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock 02807 */ 02808 #if defined(RCC_D2CCIP2R_LPTIM1SEL) 02809 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ 02810 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) 02811 #else 02812 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ 02813 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) 02814 #endif /* RCC_D2CCIP2R_LPTIM1SEL */ 02815 02816 /** @brief macro to get the LPTIM1 clock source. 02817 * @retval The clock source can be one of the following values: 02818 * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock 02819 * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock 02820 * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock 02821 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 02822 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock 02823 * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock 02824 */ 02825 #if defined(RCC_D2CCIP2R_LPTIM1SEL) 02826 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL))) 02827 #else 02828 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL))) 02829 #endif /* RCC_D2CCIP2R_LPTIM1SEL */ 02830 02831 /** @brief macro to configure the LPTIM2 clock source. 02832 * 02833 * @param __LPTIM2CLKSource__ specifies the LPTIM2 clock source. 02834 * This parameter can be one of the following values: 02835 * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock 02836 * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock 02837 * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock 02838 * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock 02839 * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock 02840 * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock 02841 */ 02842 #if defined(RCC_D3CCIPR_LPTIM2SEL) 02843 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ 02844 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) 02845 #else 02846 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ 02847 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) 02848 #endif /* RCC_D3CCIPR_LPTIM2SEL */ 02849 02850 /** @brief macro to get the LPTIM2 clock source. 02851 * @retval The clock source can be one of the following values: 02852 * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock 02853 * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock 02854 * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock 02855 * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock 02856 * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock 02857 * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock 02858 */ 02859 #if defined(RCC_D3CCIPR_LPTIM2SEL) 02860 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL))) 02861 #else 02862 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL))) 02863 #endif /* RCC_D3CCIPR_LPTIM2SEL */ 02864 02865 /** @brief macro to configure the LPTIM3/4/5 clock source. 02866 * 02867 * @param __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source. 02868 * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock 02869 * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock 02870 * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock 02871 * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock 02872 * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock 02873 * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock 02874 */ 02875 #if defined(RCC_D3CCIPR_LPTIM345SEL) 02876 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ 02877 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__)) 02878 #else 02879 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ 02880 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__)) 02881 #endif /* RCC_D3CCIPR_LPTIM345SEL */ 02882 02883 /** @brief macro to get the LPTIM3/4/5 clock source. 02884 * @retval The clock source can be one of the following values: 02885 * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock 02886 * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock 02887 * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock 02888 * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock 02889 * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock 02890 * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock 02891 */ 02892 #if defined(RCC_D3CCIPR_LPTIM345SEL) 02893 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) 02894 #else 02895 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL))) 02896 #endif /* RCC_D3CCIPR_LPTIM345SEL */ 02897 02898 /** @brief macro to configure the LPTIM3 clock source. 02899 * 02900 * @param __LPTIM3CLKSource__ specifies the LPTIM3 clock source. 02901 * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock 02902 * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock 02903 * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock 02904 * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock 02905 * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock 02906 * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock 02907 */ 02908 #define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG 02909 02910 /** @brief macro to get the LPTIM3 clock source. 02911 * @retval The clock source can be one of the following values: 02912 * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock 02913 * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock 02914 * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock 02915 * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock 02916 * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock 02917 * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock 02918 */ 02919 #define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE 02920 02921 #if defined(LPTIM4) 02922 /** @brief macro to configure the LPTIM4 clock source. 02923 * 02924 * @param __LPTIM4CLKSource__ specifies the LPTIM4 clock source. 02925 * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock 02926 * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock 02927 * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock 02928 * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock 02929 * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock 02930 * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock 02931 */ 02932 #define __HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG 02933 02934 02935 /** @brief macro to get the LPTIM4 clock source. 02936 * @retval The clock source can be one of the following values: 02937 * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock 02938 * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock 02939 * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock 02940 * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock 02941 * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock 02942 * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock 02943 */ 02944 #define __HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE 02945 #endif /* LPTIM4 */ 02946 02947 #if defined(LPTIM5) 02948 /** @brief macro to configure the LPTIM5 clock source. 02949 * 02950 * @param __LPTIM5CLKSource__ specifies the LPTIM5 clock source. 02951 * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock 02952 * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock 02953 * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock 02954 * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock 02955 * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock 02956 * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock 02957 */ 02958 #define __HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG 02959 02960 02961 /** @brief macro to get the LPTIM5 clock source. 02962 * @retval The clock source can be one of the following values: 02963 * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock 02964 * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock 02965 * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock 02966 * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock 02967 * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock 02968 * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock 02969 */ 02970 #define __HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE 02971 #endif /* LPTIM5 */ 02972 02973 #if defined(QUADSPI) 02974 /** @brief macro to configure the QSPI clock source. 02975 * 02976 * @param __QSPICLKSource__ specifies the QSPI clock source. 02977 * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock 02978 * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock 02979 * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock 02980 * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock 02981 */ 02982 #define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \ 02983 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__)) 02984 02985 02986 /** @brief macro to get the QSPI clock source. 02987 * @retval The clock source can be one of the following values: 02988 * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock 02989 * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock 02990 * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock 02991 * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock 02992 */ 02993 #define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL))) 02994 #endif /* QUADSPI */ 02995 02996 #if defined(OCTOSPI1) || defined(OCTOSPI2) 02997 /** @brief macro to configure the OSPI clock source. 02998 * 02999 * @param __OSPICLKSource__ specifies the OSPI clock source. 03000 * @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock 03001 * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock 03002 * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock 03003 * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock 03004 */ 03005 #if defined(RCC_CDCCIPR_OCTOSPISEL) 03006 #define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ 03007 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) 03008 #else 03009 #define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ 03010 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) 03011 #endif /* RCC_CDCCIPR_OCTOSPISEL */ 03012 03013 /** @brief macro to get the OSPI clock source. 03014 * @retval The clock source can be one of the following values: 03015 * @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock 03016 * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock 03017 * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock 03018 * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock 03019 */ 03020 #if defined(RCC_CDCCIPR_OCTOSPISEL) 03021 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL))) 03022 #else 03023 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL))) 03024 #endif /* RCC_CDCCIPR_OCTOSPISEL */ 03025 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ 03026 03027 03028 #if defined(DSI) 03029 /** @brief macro to configure the DSI clock source. 03030 * 03031 * @param __DSICLKSource__ specifies the DSI clock source. 03032 * @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock 03033 * @arg RCC_RCC_DSICLKSOURCE_PLL2 : PLL2_Q Clock clock is selected as DSI byte lane clock 03034 */ 03035 #define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \ 03036 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__)) 03037 03038 03039 /** @brief macro to get the DSI clock source. 03040 * @retval The clock source can be one of the following values: 03041 * @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock 03042 * @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock 03043 */ 03044 #define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL))) 03045 #endif /*DSI*/ 03046 03047 /** @brief macro to configure the FMC clock source. 03048 * 03049 * @param __FMCCLKSource__ specifies the FMC clock source. 03050 * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock 03051 * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock 03052 * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock 03053 * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock 03054 */ 03055 #if defined(RCC_D1CCIPR_FMCSEL) 03056 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ 03057 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) 03058 #else 03059 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ 03060 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) 03061 #endif /* RCC_D1CCIPR_FMCSEL */ 03062 03063 /** @brief macro to get the FMC clock source. 03064 * @retval The clock source can be one of the following values: 03065 * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock 03066 * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock 03067 * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock 03068 * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock 03069 */ 03070 #if defined(RCC_D1CCIPR_FMCSEL) 03071 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL))) 03072 #else 03073 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL))) 03074 #endif /* RCC_D1CCIPR_FMCSEL */ 03075 03076 /** @brief Macro to configure the USB clock (USBCLK). 03077 * @param __USBCLKSource__ specifies the USB clock source. 03078 * This parameter can be one of the following values: 03079 * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock 03080 * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock 03081 * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock 03082 */ 03083 #if defined(RCC_D2CCIP2R_USBSEL) 03084 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ 03085 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) 03086 #else 03087 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ 03088 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) 03089 #endif /* RCC_D2CCIP2R_USBSEL */ 03090 03091 /** @brief Macro to get the USB clock source. 03092 * @retval The clock source can be one of the following values: 03093 * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock 03094 * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock 03095 * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock 03096 */ 03097 #if defined(RCC_D2CCIP2R_USBSEL) 03098 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL))) 03099 #else 03100 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL))) 03101 #endif /* RCC_D2CCIP2R_USBSEL */ 03102 03103 /** @brief Macro to configure the ADC clock 03104 * @param __ADCCLKSource__ specifies the ADC digital interface clock source. 03105 * This parameter can be one of the following values: 03106 * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock 03107 * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock 03108 * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock 03109 */ 03110 #if defined(RCC_D3CCIPR_ADCSEL) 03111 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ 03112 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) 03113 #else 03114 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ 03115 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) 03116 #endif /* RCC_D3CCIPR_ADCSEL */ 03117 03118 /** @brief Macro to get the ADC clock source. 03119 * @retval The clock source can be one of the following values: 03120 * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock 03121 * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock 03122 * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock 03123 */ 03124 #if defined(RCC_D3CCIPR_ADCSEL) 03125 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL))) 03126 #else 03127 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL))) 03128 #endif /* RCC_D3CCIPR_ADCSEL */ 03129 03130 /** @brief Macro to configure the SWPMI1 clock 03131 * @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source. 03132 * This parameter can be one of the following values: 03133 * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock 03134 * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock 03135 */ 03136 #if defined(RCC_D2CCIP1R_SWPSEL) 03137 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ 03138 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) 03139 #else 03140 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ 03141 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) 03142 #endif /* RCC_D2CCIP1R_SWPSEL */ 03143 03144 /** @brief Macro to get the SWPMI1 clock source. 03145 * @retval The clock source can be one of the following values: 03146 * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock 03147 * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock 03148 */ 03149 #if defined(RCC_D2CCIP1R_SWPSEL) 03150 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL))) 03151 #else 03152 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL))) 03153 #endif /* RCC_D2CCIP1R_SWPSEL */ 03154 03155 /** @brief Macro to configure the DFSDM1 clock 03156 * @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source. 03157 * This parameter can be one of the following values: 03158 * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock 03159 * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock 03160 */ 03161 #if defined(RCC_D2CCIP1R_DFSDM1SEL) 03162 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ 03163 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) 03164 #else 03165 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ 03166 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) 03167 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 03168 03169 /** @brief Macro to get the DFSDM1 clock source. 03170 * @retval The clock source can be one of the following values: 03171 * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock 03172 * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock 03173 */ 03174 #if defined (RCC_D2CCIP1R_DFSDM1SEL) 03175 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL))) 03176 #else 03177 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL))) 03178 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 03179 03180 #if defined(DFSDM2_BASE) 03181 /** @brief Macro to configure the DFSDM2 clock 03182 * @param __DFSDM2CLKSource__ specifies the DFSDM2 clock source. 03183 * This parameter can be one of the following values: 03184 * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) selected as DFSDM2 clock 03185 * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock 03186 */ 03187 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \ 03188 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__)) 03189 03190 /** @brief Macro to get the DFSDM2 clock source. 03191 * @retval The clock source can be one of the following values: 03192 * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) Clock selected as DFSDM2 clock 03193 * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock 03194 */ 03195 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL))) 03196 #endif /* DFSDM2 */ 03197 03198 /** @brief macro to configure the CEC clock (CECCLK). 03199 * 03200 * @param __CECCLKSource__ specifies the CEC clock source. 03201 * This parameter can be one of the following values: 03202 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 03203 * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock 03204 * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock 03205 */ 03206 #if defined(RCC_D2CCIP2R_CECSEL) 03207 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 03208 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) 03209 #else 03210 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 03211 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) 03212 #endif /* RCC_D2CCIP2R_CECSEL */ 03213 03214 /** @brief macro to get the CEC clock source. 03215 * @retval The clock source can be one of the following values: 03216 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 03217 * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock 03218 * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock 03219 */ 03220 #if defined(RCC_D2CCIP2R_CECSEL) 03221 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL))) 03222 #else 03223 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL))) 03224 #endif /* RCC_D2CCIP2R_CECSEL */ 03225 03226 /** @brief Macro to configure the CLKP : Oscillator clock for peripheral 03227 * @param __CLKPSource__ specifies Oscillator clock for peripheral 03228 * This parameter can be one of the following values: 03229 * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral 03230 * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral 03231 * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral 03232 */ 03233 #if defined(RCC_D1CCIPR_CKPERSEL) 03234 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ 03235 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) 03236 #else 03237 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ 03238 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) 03239 #endif /* RCC_D1CCIPR_CKPERSEL */ 03240 03241 /** @brief Macro to get the Oscillator clock for peripheral source. 03242 * @retval The clock source can be one of the following values: 03243 * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral 03244 * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral 03245 * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral 03246 */ 03247 #if defined(RCC_D1CCIPR_CKPERSEL) 03248 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL))) 03249 #else 03250 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL))) 03251 #endif /* RCC_D1CCIPR_CKPERSEL */ 03252 03253 #if defined(FDCAN1) || defined(FDCAN2) 03254 /** @brief Macro to configure the FDCAN clock 03255 * @param __FDCANCLKSource__ specifies clock source for FDCAN 03256 * This parameter can be one of the following values: 03257 * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock 03258 * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock 03259 * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock 03260 */ 03261 #if defined(RCC_D2CCIP1R_FDCANSEL) 03262 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ 03263 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) 03264 #else 03265 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ 03266 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) 03267 #endif /* RCC_D2CCIP1R_FDCANSEL */ 03268 03269 /** @brief Macro to get the FDCAN clock 03270 * @retval The clock source can be one of the following values: 03271 * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock 03272 * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock 03273 * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock 03274 */ 03275 #if defined(RCC_D2CCIP1R_FDCANSEL) 03276 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL))) 03277 #else 03278 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL))) 03279 #endif /* RCC_D2CCIP1R_FDCANSEL */ 03280 03281 #endif /*FDCAN1 || FDCAN2*/ 03282 03283 /** 03284 * @brief Macro to Configure the SPI1/2/3 clock source. 03285 * @param __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived 03286 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 03287 * This parameter can be one of the following values: 03288 * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL 03289 * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 03290 * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 03291 * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP 03292 * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock 03293 * @retval None 03294 */ 03295 #if defined(RCC_D2CCIP1R_SPI123SEL) 03296 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ 03297 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) 03298 #else 03299 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ 03300 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) 03301 #endif /* RCC_D2CCIP1R_SPI123SEL */ 03302 03303 /** @brief Macro to get the SPI1/2/3 clock source. 03304 * @retval The clock source can be one of the following values: 03305 * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL 03306 * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 03307 * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 03308 * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP 03309 * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock 03310 */ 03311 #if defined(RCC_D2CCIP1R_SPI123SEL) 03312 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) 03313 #else 03314 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL))) 03315 #endif /* RCC_D2CCIP1R_SPI123SEL */ 03316 03317 /** 03318 * @brief Macro to Configure the SPI1 clock source. 03319 * @param __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived 03320 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 03321 * This parameter can be one of the following values: 03322 * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL 03323 * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 03324 * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 03325 * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP 03326 * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock 03327 * @retval None 03328 */ 03329 #define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG 03330 03331 /** @brief Macro to get the SPI1 clock source. 03332 * @retval The clock source can be one of the following values: 03333 * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL 03334 * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 03335 * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 03336 * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP 03337 * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock 03338 */ 03339 #define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE 03340 03341 /** 03342 * @brief Macro to Configure the SPI2 clock source. 03343 * @param __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived 03344 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 03345 * This parameter can be one of the following values: 03346 * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL 03347 * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 03348 * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 03349 * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP 03350 * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock 03351 * @retval None 03352 */ 03353 #define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG 03354 03355 /** @brief Macro to get the SPI2 clock source. 03356 * @retval The clock source can be one of the following values: 03357 * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL 03358 * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 03359 * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 03360 * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP 03361 * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock 03362 */ 03363 #define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE 03364 03365 /** 03366 * @brief Macro to Configure the SPI3 clock source. 03367 * @param __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived 03368 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 03369 * This parameter can be one of the following values: 03370 * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL 03371 * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 03372 * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 03373 * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP 03374 * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock 03375 * @retval None 03376 */ 03377 #define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG 03378 03379 /** @brief Macro to get the SPI3 clock source. 03380 * @retval The clock source can be one of the following values: 03381 * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL 03382 * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 03383 * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 03384 * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP 03385 * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock 03386 */ 03387 #define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE 03388 03389 /** 03390 * @brief Macro to Configure the SPI4/5 clock source. 03391 * @param __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived 03392 * from system PCLK, PLL2, PLL3, OSC 03393 * This parameter can be one of the following values: 03394 * @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1 03395 * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 03396 * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 03397 * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI 03398 * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI 03399 * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE 03400 * @retval None 03401 */ 03402 #if defined(RCC_D2CCIP1R_SPI45SEL) 03403 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ 03404 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) 03405 #else 03406 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ 03407 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) 03408 #endif /* RCC_D2CCIP1R_SPI45SEL */ 03409 03410 /** @brief Macro to get the SPI4/5 clock source. 03411 * @retval The clock source can be one of the following values: 03412 * @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1 03413 * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 03414 * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 03415 * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI 03416 * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI 03417 * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE 03418 */ 03419 #if defined(RCC_D2CCIP1R_SPI45SEL) 03420 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) 03421 #else 03422 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL))) 03423 #endif /* RCC_D2CCIP1R_SPI45SEL */ 03424 03425 /** 03426 * @brief Macro to Configure the SPI4 clock source. 03427 * @param __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived 03428 * from system PCLK, PLL2, PLL3, OSC 03429 * This parameter can be one of the following values: 03430 * @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1 03431 * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 03432 * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 03433 * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI 03434 * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI 03435 * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE 03436 * @retval None 03437 */ 03438 #define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG 03439 03440 /** @brief Macro to get the SPI4 clock source. 03441 * @retval The clock source can be one of the following values: 03442 * @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1 03443 * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 03444 * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 03445 * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI 03446 * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI 03447 * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE 03448 */ 03449 #define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE 03450 03451 /** 03452 * @brief Macro to Configure the SPI5 clock source. 03453 * @param __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived 03454 * from system PCLK, PLL2, PLL3, OSC 03455 * This parameter can be one of the following values: 03456 * @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1 03457 * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 03458 * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 03459 * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI 03460 * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI 03461 * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE 03462 * @retval None 03463 */ 03464 #define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG 03465 03466 /** @brief Macro to get the SPI5 clock source. 03467 * @retval The clock source can be one of the following values: 03468 * @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1 03469 * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 03470 * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 03471 * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI 03472 * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI 03473 * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE 03474 */ 03475 #define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE 03476 03477 /** 03478 * @brief Macro to Configure the SPI6 clock source. 03479 * @param __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived 03480 * from system PCLK, PLL2, PLL3, OSC 03481 * This parameter can be one of the following values: 03482 * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 03483 * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 03484 * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 03485 * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI 03486 * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI 03487 * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE 03488 * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*) 03489 * 03490 * @retval None 03491 * 03492 * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines. 03493 * 03494 */ 03495 #if defined(RCC_D3CCIPR_SPI6SEL) 03496 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ 03497 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) 03498 #else 03499 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ 03500 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) 03501 #endif /* RCC_D3CCIPR_SPI6SEL */ 03502 03503 /** @brief Macro to get the SPI6 clock source. 03504 * @retval The clock source can be one of the following values: 03505 * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 03506 * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 03507 * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 03508 * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI 03509 * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI 03510 * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE 03511 * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN 03512 */ 03513 #if defined(RCC_D3CCIPR_SPI6SEL) 03514 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL))) 03515 #else 03516 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL))) 03517 #endif /* RCC_D3CCIPR_SPI6SEL */ 03518 03519 /** @brief Macro to configure the SDMMC clock 03520 * @param __SDMMCCLKSource__ specifies clock source for SDMMC 03521 * This parameter can be one of the following values: 03522 * @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock 03523 * @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock 03524 */ 03525 #if defined(RCC_D1CCIPR_SDMMCSEL) 03526 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ 03527 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) 03528 #else 03529 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ 03530 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) 03531 #endif /* RCC_D1CCIPR_SDMMCSEL */ 03532 03533 /** @brief Macro to get the SDMMC clock 03534 */ 03535 #if defined(RCC_D1CCIPR_SDMMCSEL) 03536 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL))) 03537 #else 03538 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL))) 03539 #endif /* RCC_D1CCIPR_SDMMCSEL */ 03540 03541 /** @brief macro to configure the RNG clock (RNGCLK). 03542 * 03543 * @param __RNGCLKSource__ specifies the RNG clock source. 03544 * This parameter can be one of the following values: 03545 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 03546 * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock 03547 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 03548 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 03549 */ 03550 #if defined(RCC_D2CCIP2R_RNGSEL) 03551 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ 03552 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) 03553 #else 03554 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ 03555 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) 03556 #endif /* RCC_D2CCIP2R_RNGSEL */ 03557 03558 /** @brief macro to get the RNG clock source. 03559 * @retval The clock source can be one of the following values: 03560 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 03561 * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock 03562 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 03563 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 03564 */ 03565 #if defined(RCC_D2CCIP2R_RNGSEL) 03566 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL))) 03567 #else 03568 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL))) 03569 #endif /* RCC_D2CCIP2R_RNGSEL */ 03570 03571 #if defined(HRTIM1) 03572 /** @brief Macro to configure the HRTIM1 prescaler clock source. 03573 * @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source. 03574 * This parameter can be one of the following values: 03575 * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock 03576 * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock 03577 */ 03578 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \ 03579 MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__)) 03580 03581 /** @brief Macro to get the HRTIM1 clock source. 03582 * @retval The clock source can be one of the following values: 03583 * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock 03584 * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock 03585 */ 03586 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL))) 03587 #endif /* HRTIM1 */ 03588 03589 /** @brief Macro to configure the Timers clocks prescalers 03590 * @param __PRESC__ specifies the Timers clocks prescalers selection 03591 * This parameter can be one of the following values: 03592 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 03593 * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, 03594 * else it is equal to 2 x Frcc_pclkx_d2 (default after reset) 03595 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 03596 * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, 03597 * else it is equal to 4 x Frcc_pclkx_d2 03598 */ 03599 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\ 03600 RCC->CFGR |= (__PRESC__); \ 03601 }while(0) 03602 03603 /** 03604 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 03605 * @retval None 03606 */ 03607 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 03608 03609 /** 03610 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 03611 * @retval None 03612 */ 03613 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 03614 03615 /** 03616 * @brief Enable the RCC LSE CSS Event Line. 03617 * @retval None. 03618 */ 03619 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 03620 03621 /** 03622 * @brief Disable the RCC LSE CSS Event Line. 03623 * @retval None. 03624 */ 03625 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 03626 03627 #if defined(DUAL_CORE) 03628 /** 03629 * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4. 03630 * @retval None 03631 */ 03632 #define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) 03633 03634 /** 03635 * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4. 03636 * @retval None 03637 */ 03638 #define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) 03639 03640 /** 03641 * @brief Enable the RCC LSE CSS Event Line for CM4. 03642 * @retval None. 03643 */ 03644 #define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) 03645 03646 /** 03647 * @brief Disable the RCC LSE CSS Event Line for CM4. 03648 * @retval None. 03649 */ 03650 #define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) 03651 #endif /* DUAL_CORE */ 03652 03653 /** 03654 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 03655 * @retval None. 03656 */ 03657 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 03658 03659 03660 /** 03661 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 03662 * @retval None. 03663 */ 03664 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 03665 03666 03667 /** 03668 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 03669 * @retval None. 03670 */ 03671 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 03672 03673 /** 03674 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 03675 * @retval None. 03676 */ 03677 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 03678 03679 /** 03680 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 03681 * @retval None. 03682 */ 03683 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 03684 do { \ 03685 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 03686 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 03687 } while(0) 03688 03689 /** 03690 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 03691 * @retval None. 03692 */ 03693 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 03694 do { \ 03695 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 03696 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 03697 } while(0) 03698 03699 /** 03700 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 03701 * @retval EXTI RCC LSE CSS Line Status. 03702 */ 03703 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 03704 03705 /** 03706 * @brief Clear the RCC LSE CSS EXTI flag. 03707 * @retval None. 03708 */ 03709 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) 03710 03711 #if defined(DUAL_CORE) 03712 /** 03713 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4. 03714 * @retval EXTI RCC LSE CSS Line Status. 03715 */ 03716 #define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 03717 03718 /** 03719 * @brief Clear the RCC LSE CSS EXTI flag or not for CM4. 03720 * @retval None. 03721 */ 03722 #define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) 03723 #endif /* DUAL_CORE */ 03724 /** 03725 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 03726 * @retval None. 03727 */ 03728 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) 03729 03730 /** 03731 * @brief Enable the specified CRS interrupts. 03732 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 03733 * This parameter can be any combination of the following values: 03734 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 03735 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 03736 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 03737 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 03738 * @retval None 03739 */ 03740 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 03741 03742 /** 03743 * @brief Disable the specified CRS interrupts. 03744 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 03745 * This parameter can be any combination of the following values: 03746 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 03747 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 03748 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 03749 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 03750 * @retval None 03751 */ 03752 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 03753 03754 /** @brief Check whether the CRS interrupt has occurred or not. 03755 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 03756 * This parameter can be one of the following values: 03757 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 03758 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 03759 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 03760 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 03761 * @retval The new state of __INTERRUPT__ (SET or RESET). 03762 */ 03763 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 03764 03765 /** @brief Clear the CRS interrupt pending bits 03766 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 03767 * This parameter can be any combination of the following values: 03768 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 03769 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 03770 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 03771 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 03772 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 03773 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 03774 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 03775 */ 03776 /* CRS IT Error Mask */ 03777 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 03778 03779 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 03780 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 03781 { \ 03782 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 03783 } \ 03784 else \ 03785 { \ 03786 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 03787 } \ 03788 } while(0) 03789 03790 /** 03791 * @brief Check whether the specified CRS flag is set or not. 03792 * @param __FLAG__ specifies the flag to check. 03793 * This parameter can be one of the following values: 03794 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 03795 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 03796 * @arg @ref RCC_CRS_FLAG_ERR Error 03797 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 03798 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 03799 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 03800 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 03801 * @retval The new state of _FLAG_ (TRUE or FALSE). 03802 */ 03803 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 03804 03805 /** 03806 * @brief Clear the CRS specified FLAG. 03807 * @param __FLAG__ specifies the flag to clear. 03808 * This parameter can be one of the following values: 03809 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 03810 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 03811 * @arg @ref RCC_CRS_FLAG_ERR Error 03812 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 03813 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 03814 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 03815 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 03816 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 03817 * @retval None 03818 */ 03819 03820 /* CRS Flag Error Mask */ 03821 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 03822 03823 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 03824 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 03825 { \ 03826 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 03827 } \ 03828 else \ 03829 { \ 03830 WRITE_REG(CRS->ICR, (__FLAG__)); \ 03831 } \ 03832 } while(0) 03833 03834 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 03835 * @{ 03836 */ 03837 /** 03838 * @brief Enable the oscillator clock for frequency error counter. 03839 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 03840 * @retval None 03841 */ 03842 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 03843 03844 /** 03845 * @brief Disable the oscillator clock for frequency error counter. 03846 * @retval None 03847 */ 03848 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 03849 03850 /** 03851 * @brief Enable the automatic hardware adjustment of TRIM bits. 03852 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 03853 * @retval None 03854 */ 03855 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 03856 03857 /** 03858 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 03859 * @retval None 03860 */ 03861 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 03862 03863 /** 03864 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 03865 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 03866 * of the synchronization source after pre-scaling. It is then decreased by one in order to 03867 * reach the expected synchronization on the zero value. The formula is the following: 03868 * RELOAD = (fTARGET / fSYNC) -1 03869 * @param __FTARGET__ Target frequency (value in Hz) 03870 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 03871 * @retval None 03872 */ 03873 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 03874 03875 03876 /** 03877 * @} 03878 */ 03879 03880 03881 /** 03882 * @} 03883 */ 03884 03885 03886 /* Exported functions --------------------------------------------------------*/ 03887 /** @addtogroup RCCEx_Exported_Functions 03888 * @{ 03889 */ 03890 03891 /** @addtogroup RCCEx_Exported_Functions_Group1 03892 * @{ 03893 */ 03894 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 03895 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 03896 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 03897 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void); 03898 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void); 03899 uint32_t HAL_RCCEx_GetD1SysClockFreq(void); 03900 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks); 03901 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks); 03902 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks); 03903 /** 03904 * @} 03905 */ 03906 03907 /** @addtogroup RCCEx_Exported_Functions_Group2 03908 * @{ 03909 */ 03910 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 03911 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); 03912 void HAL_RCCEx_EnableLSECSS(void); 03913 void HAL_RCCEx_DisableLSECSS(void); 03914 void HAL_RCCEx_EnableLSECSS_IT(void); 03915 void HAL_RCCEx_LSECSS_IRQHandler(void); 03916 void HAL_RCCEx_LSECSS_Callback(void); 03917 #if defined(DUAL_CORE) 03918 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx); 03919 #endif /*DUAL_CORE*/ 03920 #if defined(RCC_GCR_WW1RSC) 03921 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx); 03922 #endif /*RCC_GCR_WW1RSC*/ 03923 /** 03924 * @} 03925 */ 03926 03927 03928 /** @addtogroup RCCEx_Exported_Functions_Group3 03929 * @{ 03930 */ 03931 03932 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 03933 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 03934 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 03935 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 03936 void HAL_RCCEx_CRS_IRQHandler(void); 03937 void HAL_RCCEx_CRS_SyncOkCallback(void); 03938 void HAL_RCCEx_CRS_SyncWarnCallback(void); 03939 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 03940 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 03941 03942 /** 03943 * @} 03944 */ 03945 03946 /** 03947 * @} 03948 */ 03949 03950 /* Private macros ------------------------------------------------------------*/ 03951 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros 03952 * @{ 03953 */ 03954 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters 03955 * @{ 03956 */ 03957 03958 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \ 03959 ((VALUE) == RCC_PLL2_DIVQ) || \ 03960 ((VALUE) == RCC_PLL2_DIVR)) 03961 03962 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \ 03963 ((VALUE) == RCC_PLL3_DIVQ) || \ 03964 ((VALUE) == RCC_PLL3_DIVR)) 03965 03966 #if defined(RCC_D2CCIP2R_USART16SEL) 03967 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ 03968 ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ 03969 ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ 03970 ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ 03971 ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ 03972 ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) 03973 #else 03974 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ 03975 ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \ 03976 ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ 03977 ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ 03978 ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ 03979 ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ 03980 ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) 03981 /* alias*/ 03982 #define IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE 03983 #endif /* RCC_D2CCIP2R_USART16SEL */ 03984 03985 #if defined(RCC_D2CCIP2R_USART28SEL) 03986 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ 03987 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ 03988 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ 03989 ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ 03990 ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ 03991 ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) 03992 #else 03993 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ 03994 ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \ 03995 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ 03996 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ 03997 ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ 03998 ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ 03999 ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) 04000 #endif /* RCC_D2CCIP2R_USART28SEL */ 04001 04002 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \ 04003 ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \ 04004 ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \ 04005 ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \ 04006 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ 04007 ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) 04008 04009 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \ 04010 ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \ 04011 ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \ 04012 ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \ 04013 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ 04014 ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) 04015 04016 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \ 04017 ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \ 04018 ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \ 04019 ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \ 04020 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ 04021 ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) 04022 04023 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \ 04024 ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \ 04025 ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \ 04026 ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \ 04027 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ 04028 ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) 04029 04030 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \ 04031 ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \ 04032 ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \ 04033 ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \ 04034 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ 04035 ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) 04036 04037 #define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \ 04038 ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \ 04039 ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \ 04040 ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \ 04041 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ 04042 ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) 04043 04044 #define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \ 04045 ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \ 04046 ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \ 04047 ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \ 04048 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ 04049 ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) 04050 04051 #define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \ 04052 ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \ 04053 ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \ 04054 ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \ 04055 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ 04056 ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) 04057 04058 #if defined(UART9) 04059 #define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \ 04060 ((SOURCE) == RCC_UART9CLKSOURCE_PLL2) || \ 04061 ((SOURCE) == RCC_UART9CLKSOURCE_PLL3) || \ 04062 ((SOURCE) == RCC_UART9CLKSOURCE_CSI) || \ 04063 ((SOURCE) == RCC_UART9CLKSOURCE_LSE) || \ 04064 ((SOURCE) == RCC_UART9CLKSOURCE_HSI)) 04065 #endif 04066 04067 #if defined(USART10) 04068 #define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \ 04069 ((SOURCE) == RCC_USART10CLKSOURCE_PLL2) || \ 04070 ((SOURCE) == RCC_USART10CLKSOURCE_PLL3) || \ 04071 ((SOURCE) == RCC_USART10CLKSOURCE_CSI) || \ 04072 ((SOURCE) == RCC_USART10CLKSOURCE_LSE) || \ 04073 ((SOURCE) == RCC_USART10CLKSOURCE_HSI)) 04074 #endif 04075 04076 #define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \ 04077 ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \ 04078 ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \ 04079 ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \ 04080 ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \ 04081 ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI)) 04082 04083 #if defined(I2C5) 04084 #define IS_RCC_I2C1235CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1235CLKSOURCE_PLL3) || \ 04085 ((SOURCE) == RCC_I2C1235CLKSOURCE_HSI) || \ 04086 ((SOURCE) == RCC_I2C1235CLKSOURCE_D2PCLK1) || \ 04087 ((SOURCE) == RCC_I2C1235CLKSOURCE_CSI)) 04088 04089 #define IS_RCC_I2C123CLKSOURCE IS_RCC_I2C1235CLKSOURCE /* For API Backward compatibility */ 04090 #else 04091 #define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \ 04092 ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \ 04093 ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \ 04094 ((SOURCE) == RCC_I2C123CLKSOURCE_CSI)) 04095 #endif /*I2C5*/ 04096 04097 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \ 04098 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ 04099 ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \ 04100 ((SOURCE) == RCC_I2C1CLKSOURCE_CSI)) 04101 04102 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \ 04103 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ 04104 ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \ 04105 ((SOURCE) == RCC_I2C2CLKSOURCE_CSI)) 04106 04107 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \ 04108 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ 04109 ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \ 04110 ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) 04111 04112 #define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \ 04113 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \ 04114 ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \ 04115 ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) 04116 04117 #if defined(I2C5) 04118 #define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \ 04119 ((SOURCE) == RCC_I2C5CLKSOURCE_HSI) || \ 04120 ((SOURCE) == RCC_I2C5CLKSOURCE_D2PCLK1)|| \ 04121 ((SOURCE) == RCC_I2C5CLKSOURCE_CSI)) 04122 #endif /*I2C5*/ 04123 04124 #define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \ 04125 ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \ 04126 ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \ 04127 ((SOURCE) == RCC_RNGCLKSOURCE_LSI)) 04128 04129 #if defined(HRTIM1) 04130 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \ 04131 ((SOURCE) == RCC_HRTIM1CLK_CPUCLK)) 04132 #endif 04133 04134 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \ 04135 ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \ 04136 ((SOURCE) == RCC_USBCLKSOURCE_HSI48)) 04137 04138 #define IS_RCC_SAI1CLK(__SOURCE__) \ 04139 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 04140 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \ 04141 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \ 04142 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \ 04143 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 04144 04145 #if defined(SAI3) 04146 #define IS_RCC_SAI23CLK(__SOURCE__) \ 04147 (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \ 04148 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \ 04149 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \ 04150 ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \ 04151 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN)) 04152 04153 #define IS_RCC_SAI2CLK(__SOURCE__) \ 04154 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 04155 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \ 04156 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \ 04157 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \ 04158 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) 04159 04160 04161 #define IS_RCC_SAI3CLK(__SOURCE__) \ 04162 (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \ 04163 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \ 04164 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \ 04165 ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \ 04166 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN)) 04167 #endif 04168 04169 #if defined(RCC_CDCCIP1R_SAI2ASEL) 04170 #define IS_RCC_SAI2ACLK(__SOURCE__) \ 04171 (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL) || \ 04172 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \ 04173 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \ 04174 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \ 04175 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \ 04176 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF)) 04177 #endif 04178 04179 #if defined(RCC_CDCCIP1R_SAI2BSEL) 04180 #define IS_RCC_SAI2BCLK(__SOURCE__) \ 04181 (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL) || \ 04182 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \ 04183 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \ 04184 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \ 04185 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \ 04186 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF)) 04187 #endif 04188 04189 #define IS_RCC_SPI123CLK(__SOURCE__) \ 04190 (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \ 04191 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \ 04192 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \ 04193 ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \ 04194 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN)) 04195 04196 #define IS_RCC_SPI1CLK(__SOURCE__) \ 04197 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \ 04198 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \ 04199 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \ 04200 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \ 04201 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN)) 04202 04203 #define IS_RCC_SPI2CLK(__SOURCE__) \ 04204 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \ 04205 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \ 04206 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \ 04207 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \ 04208 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN)) 04209 04210 #define IS_RCC_SPI3CLK(__SOURCE__) \ 04211 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \ 04212 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \ 04213 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \ 04214 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \ 04215 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN)) 04216 04217 #define IS_RCC_SPI45CLK(__SOURCE__) \ 04218 (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1) || \ 04219 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \ 04220 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \ 04221 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \ 04222 ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \ 04223 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) 04224 04225 #define IS_RCC_SPI4CLK(__SOURCE__) \ 04226 (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1) || \ 04227 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \ 04228 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \ 04229 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ 04230 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \ 04231 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) 04232 04233 #define IS_RCC_SPI5CLK(__SOURCE__) \ 04234 (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \ 04235 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \ 04236 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \ 04237 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ 04238 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \ 04239 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) 04240 04241 #if defined(RCC_D3CCIPR_SPI6SEL) 04242 #define IS_RCC_SPI6CLK(__SOURCE__) \ 04243 (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ 04244 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ 04245 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ 04246 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 04247 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 04248 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) 04249 #else 04250 #define IS_RCC_SPI6CLK(__SOURCE__) \ 04251 (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ 04252 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ 04253 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ 04254 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 04255 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 04256 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \ 04257 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN)) 04258 #endif /* RCC_D3CCIPR_SPI6SEL */ 04259 04260 #if defined(SAI4) 04261 #define IS_RCC_SAI4ACLK(__SOURCE__) \ 04262 (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \ 04263 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \ 04264 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \ 04265 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \ 04266 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN)) 04267 04268 #define IS_RCC_SAI4BCLK(__SOURCE__) \ 04269 (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || \ 04270 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \ 04271 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \ 04272 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \ 04273 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN)) 04274 #endif /*SAI4*/ 04275 04276 #define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 04277 #define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 04278 #define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 04279 #define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 04280 #define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 04281 04282 #define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 04283 #define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 04284 #define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 04285 #define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 04286 #define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 04287 04288 #define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) || \ 04289 ((VALUE) == RCC_PLL2VCIRANGE_1) || \ 04290 ((VALUE) == RCC_PLL2VCIRANGE_2) || \ 04291 ((VALUE) == RCC_PLL2VCIRANGE_3)) 04292 04293 #define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) || \ 04294 ((VALUE) == RCC_PLL3VCIRANGE_1) || \ 04295 ((VALUE) == RCC_PLL3VCIRANGE_2) || \ 04296 ((VALUE) == RCC_PLL3VCIRANGE_3)) 04297 04298 #define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) || \ 04299 ((VALUE) == RCC_PLL2VCOMEDIUM)) 04300 04301 #define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \ 04302 ((VALUE) == RCC_PLL3VCOMEDIUM)) 04303 04304 #define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \ 04305 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \ 04306 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \ 04307 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \ 04308 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ 04309 ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP)) 04310 04311 #define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \ 04312 ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \ 04313 ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \ 04314 ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \ 04315 ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \ 04316 ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP)) 04317 04318 #define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \ 04319 ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \ 04320 ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \ 04321 ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \ 04322 ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \ 04323 ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP)) 04324 04325 #define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1) || \ 04326 ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \ 04327 ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \ 04328 ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \ 04329 ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \ 04330 ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP)) 04331 04332 #if defined(LPTIM4) 04333 #define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \ 04334 ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \ 04335 ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \ 04336 ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \ 04337 ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \ 04338 ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP)) 04339 #endif /* LPTIM4*/ 04340 04341 #if defined(LPTIM5) 04342 #define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \ 04343 ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \ 04344 ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \ 04345 ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \ 04346 ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \ 04347 ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP)) 04348 #endif /*LPTIM5*/ 04349 04350 #if defined(QUADSPI) 04351 #define IS_RCC_QSPICLK(__SOURCE__) \ 04352 (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \ 04353 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \ 04354 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \ 04355 ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP)) 04356 #endif /*QUADSPI*/ 04357 04358 #if defined(OCTOSPI1) || defined(OCTOSPI1) 04359 #define IS_RCC_OSPICLK(__SOURCE__) \ 04360 (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK) || \ 04361 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL) || \ 04362 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2) || \ 04363 ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP)) 04364 #endif /*OCTOSPI1 || OCTOSPI1*/ 04365 04366 #if defined(DSI) 04367 #define IS_RCC_DSICLK(__SOURCE__) \ 04368 (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \ 04369 ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2)) 04370 #endif /*DSI*/ 04371 04372 #define IS_RCC_FMCCLK(__SOURCE__) \ 04373 (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \ 04374 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \ 04375 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \ 04376 ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP)) 04377 04378 #if defined(FDCAN1) || defined(FDCAN2) 04379 #define IS_RCC_FDCANCLK(__SOURCE__) \ 04380 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ 04381 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ 04382 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2)) 04383 #endif /*FDCAN1 || FDCAN2*/ 04384 04385 #define IS_RCC_SDMMC(__SOURCE__) \ 04386 (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \ 04387 ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2)) 04388 04389 #define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \ 04390 ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \ 04391 ((SOURCE) == RCC_ADCCLKSOURCE_CLKP)) 04392 04393 #define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \ 04394 ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI)) 04395 04396 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \ 04397 ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS)) 04398 04399 #if defined(DFSDM2_BASE) 04400 #define IS_RCC_DFSDM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \ 04401 ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS)) 04402 #endif /*DFSDM2*/ 04403 04404 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \ 04405 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \ 04406 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \ 04407 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI)) 04408 04409 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \ 04410 ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \ 04411 ((SOURCE) == RCC_CECCLKSOURCE_CSI)) 04412 04413 #define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \ 04414 ((SOURCE) == RCC_CLKPSOURCE_CSI) || \ 04415 ((SOURCE) == RCC_CLKPSOURCE_HSE)) 04416 #define IS_RCC_TIMPRES(VALUE) \ 04417 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ 04418 ((VALUE) == RCC_TIMPRES_ACTIVATED)) 04419 04420 #if defined(DUAL_CORE) 04421 #define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \ 04422 ((CORE) == RCC_BOOT_C2)) 04423 #endif /*DUAL_CORE*/ 04424 04425 #if defined(DUAL_CORE) 04426 #define IS_RCC_SCOPE_WWDG(WWDG) (((WWDG) == RCC_WWDG1) || \ 04427 ((WWDG) == RCC_WWDG2)) 04428 #else 04429 #define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1) 04430 04431 #endif /*DUAL_CORE*/ 04432 04433 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \ 04434 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 04435 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \ 04436 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN)) 04437 04438 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 04439 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 04440 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 04441 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 04442 04443 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 04444 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 04445 04446 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 04447 04448 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 04449 04450 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 04451 04452 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 04453 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 04454 /** 04455 * @} 04456 */ 04457 04458 /** 04459 * @} 04460 */ 04461 04462 /** 04463 * @} 04464 */ 04465 04466 /** 04467 * @} 04468 */ 04469 04470 #ifdef __cplusplus 04471 } 04472 #endif 04473 04474 #endif /* STM32H7xx_HAL_RCC_EX_H */ 04475
1.7.6.1