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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_hsem.h 00004 * @author MCD Application Team 00005 * @brief Header file of HSEM LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_LL_HSEM_H 00021 #define STM32H7xx_LL_HSEM_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx.h" 00029 00030 /** @addtogroup STM32H7xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined(HSEM) 00035 00036 /** @defgroup HSEM_LL HSEM 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 /* Private constants ---------------------------------------------------------*/ 00043 /* Private macros ------------------------------------------------------------*/ 00044 00045 /* Exported types ------------------------------------------------------------*/ 00046 /* Exported constants --------------------------------------------------------*/ 00047 00048 /** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants 00049 * @{ 00050 */ 00051 00052 /** @defgroup HSEM_LL_EC_COREID COREID Defines 00053 * @{ 00054 */ 00055 #define LL_HSEM_COREID_NONE 0U 00056 #define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1 00057 #if defined(DUAL_CORE) 00058 #define LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2 00059 #endif /* DUAL_CORE */ 00060 #define LL_HSEM_COREID HSEM_CR_COREID_CURRENT 00061 /** 00062 * @} 00063 */ 00064 00065 00066 /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines 00067 * @brief Flags defines which can be used with LL_HSEM_ReadReg function 00068 * @{ 00069 */ 00070 00071 #define LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0 00072 #define LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1 00073 #define LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2 00074 #define LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3 00075 #define LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4 00076 #define LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5 00077 #define LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6 00078 #define LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7 00079 #define LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8 00080 #define LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9 00081 #define LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10 00082 #define LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11 00083 #define LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12 00084 #define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13 00085 #define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14 00086 #define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15 00087 #if (HSEM_SEMID_MAX == 15) 00088 #define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU 00089 #else /* HSEM_SEMID_MAX == 31 */ 00090 #define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16 00091 #define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17 00092 #define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18 00093 #define LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19 00094 #define LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20 00095 #define LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21 00096 #define LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22 00097 #define LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23 00098 #define LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24 00099 #define LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25 00100 #define LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26 00101 #define LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27 00102 #define LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28 00103 #define LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29 00104 #define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30 00105 #define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31 00106 #define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU 00107 #endif /* HSEM_SEMID_MAX == 15 */ 00108 /** 00109 * @} 00110 */ 00111 00112 /** 00113 * @} 00114 */ 00115 00116 /* Exported macro ------------------------------------------------------------*/ 00117 /** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros 00118 * @{ 00119 */ 00120 00121 /** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros 00122 * @{ 00123 */ 00124 00125 /** 00126 * @brief Write a value in HSEM register 00127 * @param __INSTANCE__ HSEM Instance 00128 * @param __REG__ Register to be written 00129 * @param __VALUE__ Value to be written in the register 00130 * @retval None 00131 */ 00132 #define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00133 00134 /** 00135 * @brief Read a value in HSEM register 00136 * @param __INSTANCE__ HSEM Instance 00137 * @param __REG__ Register to be read 00138 * @retval Register value 00139 */ 00140 #define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00141 /** 00142 * @} 00143 */ 00144 00145 /** 00146 * @} 00147 */ 00148 00149 /* Exported functions --------------------------------------------------------*/ 00150 /** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions 00151 * @{ 00152 */ 00153 00154 /** @defgroup HSEM_LL_EF_Data_Management Data_Management 00155 * @{ 00156 */ 00157 00158 00159 /** 00160 * @brief Return 1 if the semaphore is locked, else return 0. 00161 * @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked 00162 * @param HSEMx HSEM Instance. 00163 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 00164 * @retval State of bit (1 or 0). 00165 */ 00166 __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore) 00167 { 00168 return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL); 00169 } 00170 00171 /** 00172 * @brief Get core id. 00173 * @rmtoll R COREID LL_HSEM_GetCoreId 00174 * @param HSEMx HSEM Instance. 00175 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 00176 * @retval Returned value can be one of the following values: 00177 * @arg @ref LL_HSEM_COREID_NONE 00178 * @arg @ref LL_HSEM_COREID_CPU1 00179 * @arg @ref LL_HSEM_COREID_CPU2 00180 */ 00181 __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) 00182 { 00183 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk)); 00184 } 00185 00186 /** 00187 * @brief Get process id. 00188 * @rmtoll R PROCID LL_HSEM_GetProcessId 00189 * @param HSEMx HSEM Instance. 00190 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 00191 * @retval Process number. Value between Min_Data=0 and Max_Data=255 00192 */ 00193 __STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) 00194 { 00195 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk)); 00196 } 00197 00198 /** 00199 * @brief Get the lock by writing in R register. 00200 * @note The R register has to be read to determined if the lock is taken. 00201 * @rmtoll R LOCK LL_HSEM_SetLock 00202 * @rmtoll R COREID LL_HSEM_SetLock 00203 * @rmtoll R PROCID LL_HSEM_SetLock 00204 * @param HSEMx HSEM Instance. 00205 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 00206 * @param process Process id. Value between Min_Data=0 and Max_Data=255 00207 * @retval None 00208 */ 00209 __STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) 00210 { 00211 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process)); 00212 } 00213 00214 /** 00215 * @brief Get the lock with 2-step lock. 00216 * @rmtoll R LOCK LL_HSEM_2StepLock 00217 * @rmtoll R COREID LL_HSEM_2StepLock 00218 * @rmtoll R PROCID LL_HSEM_2StepLock 00219 * @param HSEMx HSEM Instance. 00220 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 00221 * @param process Process id. Value between Min_Data=0 and Max_Data=255 00222 * @retval 1 lock fail, 0 lock successful or already locked by same process and core 00223 */ 00224 __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) 00225 { 00226 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process)); 00227 return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL); 00228 } 00229 00230 /** 00231 * @brief Get the lock with 1-step lock. 00232 * @rmtoll RLR LOCK LL_HSEM_1StepLock 00233 * @rmtoll RLR COREID LL_HSEM_1StepLock 00234 * @rmtoll RLR PROCID LL_HSEM_1StepLock 00235 * @param HSEMx HSEM Instance. 00236 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 00237 * @retval 1 lock fail, 0 lock successful or already locked by same core 00238 */ 00239 __STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore) 00240 { 00241 return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); 00242 } 00243 00244 /** 00245 * @brief Release the lock of the semaphore. 00246 * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0. 00247 * @rmtoll R LOCK LL_HSEM_ReleaseLock 00248 * @param HSEMx HSEM Instance. 00249 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 00250 * @param process Process number. Value between Min_Data=0 and Max_Data=255 00251 * @retval None 00252 */ 00253 __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) 00254 { 00255 WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process)); 00256 } 00257 00258 /** 00259 * @brief Get the lock status of the semaphore. 00260 * @rmtoll R LOCK LL_HSEM_GetStatus 00261 * @param HSEMx HSEM Instance. 00262 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 00263 * @retval 0 semaphore is free, 1 semaphore is locked */ 00264 __STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore) 00265 { 00266 return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL); 00267 } 00268 00269 /** 00270 * @brief Set the key. 00271 * @rmtoll KEYR KEY LL_HSEM_SetKey 00272 * @param HSEMx HSEM Instance. 00273 * @param key Key value. 00274 * @retval None 00275 */ 00276 __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key) 00277 { 00278 WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos); 00279 } 00280 00281 /** 00282 * @brief Get the key. 00283 * @rmtoll KEYR KEY LL_HSEM_GetKey 00284 * @param HSEMx HSEM Instance. 00285 * @retval key to unlock all semaphore from the same core 00286 */ 00287 __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx) 00288 { 00289 return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos); 00290 } 00291 00292 /** 00293 * @brief Release all semaphore with the same core id. 00294 * @rmtoll CR KEY LL_HSEM_ResetAllLock 00295 * @rmtoll CR SEC LL_HSEM_ResetAllLock 00296 * @rmtoll CR PRIV LL_HSEM_ResetAllLock 00297 * @param HSEMx HSEM Instance. 00298 * @param key Key value. 00299 * @param core This parameter can be one of the following values: 00300 * @arg @ref LL_HSEM_COREID_CPU1 00301 * @arg @ref LL_HSEM_COREID_CPU2 00302 * @retval None 00303 */ 00304 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core) 00305 { 00306 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core); 00307 } 00308 00309 /** 00310 * @} 00311 */ 00312 00313 /** @defgroup HSEM_LL_EF_IT_Management IT_Management 00314 * @{ 00315 */ 00316 00317 /** 00318 * @brief Enable interrupt. 00319 * @rmtoll C1IER ISEM LL_HSEM_EnableIT_C1IER 00320 * @param HSEMx HSEM Instance. 00321 * @param SemaphoreMask This parameter can be a combination of the following values: 00322 * @arg @ref LL_HSEM_SEMAPHORE_0 00323 * @arg @ref LL_HSEM_SEMAPHORE_1 00324 * @arg @ref LL_HSEM_SEMAPHORE_2 00325 * @arg @ref LL_HSEM_SEMAPHORE_3 00326 * @arg @ref LL_HSEM_SEMAPHORE_4 00327 * @arg @ref LL_HSEM_SEMAPHORE_5 00328 * @arg @ref LL_HSEM_SEMAPHORE_6 00329 * @arg @ref LL_HSEM_SEMAPHORE_7 00330 * @arg @ref LL_HSEM_SEMAPHORE_8 00331 * @arg @ref LL_HSEM_SEMAPHORE_9 00332 * @arg @ref LL_HSEM_SEMAPHORE_10 00333 * @arg @ref LL_HSEM_SEMAPHORE_11 00334 * @arg @ref LL_HSEM_SEMAPHORE_12 00335 * @arg @ref LL_HSEM_SEMAPHORE_13 00336 * @arg @ref LL_HSEM_SEMAPHORE_14 00337 * @arg @ref LL_HSEM_SEMAPHORE_15 00338 * @arg @ref LL_HSEM_SEMAPHORE_16 00339 * @arg @ref LL_HSEM_SEMAPHORE_17 00340 * @arg @ref LL_HSEM_SEMAPHORE_18 00341 * @arg @ref LL_HSEM_SEMAPHORE_19 00342 * @arg @ref LL_HSEM_SEMAPHORE_20 00343 * @arg @ref LL_HSEM_SEMAPHORE_21 00344 * @arg @ref LL_HSEM_SEMAPHORE_22 00345 * @arg @ref LL_HSEM_SEMAPHORE_23 00346 * @arg @ref LL_HSEM_SEMAPHORE_24 00347 * @arg @ref LL_HSEM_SEMAPHORE_25 00348 * @arg @ref LL_HSEM_SEMAPHORE_26 00349 * @arg @ref LL_HSEM_SEMAPHORE_27 00350 * @arg @ref LL_HSEM_SEMAPHORE_28 00351 * @arg @ref LL_HSEM_SEMAPHORE_29 00352 * @arg @ref LL_HSEM_SEMAPHORE_30 00353 * @arg @ref LL_HSEM_SEMAPHORE_31 00354 * @arg @ref LL_HSEM_SEMAPHORE_ALL 00355 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 00356 * depends on devices. 00357 * @retval None 00358 */ 00359 __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 00360 { 00361 SET_BIT(HSEMx->C1IER, SemaphoreMask); 00362 } 00363 00364 /** 00365 * @brief Disable interrupt. 00366 * @rmtoll C1IER ISEM LL_HSEM_DisableIT_C1IER 00367 * @param HSEMx HSEM Instance. 00368 * @param SemaphoreMask This parameter can be a combination of the following values: 00369 * @arg @ref LL_HSEM_SEMAPHORE_0 00370 * @arg @ref LL_HSEM_SEMAPHORE_1 00371 * @arg @ref LL_HSEM_SEMAPHORE_2 00372 * @arg @ref LL_HSEM_SEMAPHORE_3 00373 * @arg @ref LL_HSEM_SEMAPHORE_4 00374 * @arg @ref LL_HSEM_SEMAPHORE_5 00375 * @arg @ref LL_HSEM_SEMAPHORE_6 00376 * @arg @ref LL_HSEM_SEMAPHORE_7 00377 * @arg @ref LL_HSEM_SEMAPHORE_8 00378 * @arg @ref LL_HSEM_SEMAPHORE_9 00379 * @arg @ref LL_HSEM_SEMAPHORE_10 00380 * @arg @ref LL_HSEM_SEMAPHORE_11 00381 * @arg @ref LL_HSEM_SEMAPHORE_12 00382 * @arg @ref LL_HSEM_SEMAPHORE_13 00383 * @arg @ref LL_HSEM_SEMAPHORE_14 00384 * @arg @ref LL_HSEM_SEMAPHORE_15 00385 * @arg @ref LL_HSEM_SEMAPHORE_16 00386 * @arg @ref LL_HSEM_SEMAPHORE_17 00387 * @arg @ref LL_HSEM_SEMAPHORE_18 00388 * @arg @ref LL_HSEM_SEMAPHORE_19 00389 * @arg @ref LL_HSEM_SEMAPHORE_20 00390 * @arg @ref LL_HSEM_SEMAPHORE_21 00391 * @arg @ref LL_HSEM_SEMAPHORE_22 00392 * @arg @ref LL_HSEM_SEMAPHORE_23 00393 * @arg @ref LL_HSEM_SEMAPHORE_24 00394 * @arg @ref LL_HSEM_SEMAPHORE_25 00395 * @arg @ref LL_HSEM_SEMAPHORE_26 00396 * @arg @ref LL_HSEM_SEMAPHORE_27 00397 * @arg @ref LL_HSEM_SEMAPHORE_28 00398 * @arg @ref LL_HSEM_SEMAPHORE_29 00399 * @arg @ref LL_HSEM_SEMAPHORE_30 00400 * @arg @ref LL_HSEM_SEMAPHORE_31 00401 * @arg @ref LL_HSEM_SEMAPHORE_ALL 00402 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 00403 * depends on devices. 00404 * @retval None 00405 */ 00406 __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 00407 { 00408 CLEAR_BIT(HSEMx->C1IER, SemaphoreMask); 00409 } 00410 00411 /** 00412 * @brief Check if interrupt is enabled. 00413 * @rmtoll C1IER ISEM LL_HSEM_IsEnabledIT_C1IER 00414 * @param HSEMx HSEM Instance. 00415 * @param SemaphoreMask This parameter can be a combination of the following values: 00416 * @arg @ref LL_HSEM_SEMAPHORE_0 00417 * @arg @ref LL_HSEM_SEMAPHORE_1 00418 * @arg @ref LL_HSEM_SEMAPHORE_2 00419 * @arg @ref LL_HSEM_SEMAPHORE_3 00420 * @arg @ref LL_HSEM_SEMAPHORE_4 00421 * @arg @ref LL_HSEM_SEMAPHORE_5 00422 * @arg @ref LL_HSEM_SEMAPHORE_6 00423 * @arg @ref LL_HSEM_SEMAPHORE_7 00424 * @arg @ref LL_HSEM_SEMAPHORE_8 00425 * @arg @ref LL_HSEM_SEMAPHORE_9 00426 * @arg @ref LL_HSEM_SEMAPHORE_10 00427 * @arg @ref LL_HSEM_SEMAPHORE_11 00428 * @arg @ref LL_HSEM_SEMAPHORE_12 00429 * @arg @ref LL_HSEM_SEMAPHORE_13 00430 * @arg @ref LL_HSEM_SEMAPHORE_14 00431 * @arg @ref LL_HSEM_SEMAPHORE_15 00432 * @arg @ref LL_HSEM_SEMAPHORE_16 00433 * @arg @ref LL_HSEM_SEMAPHORE_17 00434 * @arg @ref LL_HSEM_SEMAPHORE_18 00435 * @arg @ref LL_HSEM_SEMAPHORE_19 00436 * @arg @ref LL_HSEM_SEMAPHORE_20 00437 * @arg @ref LL_HSEM_SEMAPHORE_21 00438 * @arg @ref LL_HSEM_SEMAPHORE_22 00439 * @arg @ref LL_HSEM_SEMAPHORE_23 00440 * @arg @ref LL_HSEM_SEMAPHORE_24 00441 * @arg @ref LL_HSEM_SEMAPHORE_25 00442 * @arg @ref LL_HSEM_SEMAPHORE_26 00443 * @arg @ref LL_HSEM_SEMAPHORE_27 00444 * @arg @ref LL_HSEM_SEMAPHORE_28 00445 * @arg @ref LL_HSEM_SEMAPHORE_29 00446 * @arg @ref LL_HSEM_SEMAPHORE_30 00447 * @arg @ref LL_HSEM_SEMAPHORE_31 00448 * @arg @ref LL_HSEM_SEMAPHORE_ALL 00449 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 00450 * depends on devices. 00451 * @retval State of bit (1 or 0). 00452 */ 00453 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 00454 { 00455 return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); 00456 } 00457 00458 #if defined(DUAL_CORE) 00459 /** 00460 * @brief Enable interrupt. 00461 * @rmtoll C2IER ISEM LL_HSEM_EnableIT_C2IER 00462 * @param HSEMx HSEM Instance. 00463 * @param SemaphoreMask This parameter can be a combination of the following values: 00464 * @arg @ref LL_HSEM_SEMAPHORE_0 00465 * @arg @ref LL_HSEM_SEMAPHORE_1 00466 * @arg @ref LL_HSEM_SEMAPHORE_2 00467 * @arg @ref LL_HSEM_SEMAPHORE_3 00468 * @arg @ref LL_HSEM_SEMAPHORE_4 00469 * @arg @ref LL_HSEM_SEMAPHORE_5 00470 * @arg @ref LL_HSEM_SEMAPHORE_6 00471 * @arg @ref LL_HSEM_SEMAPHORE_7 00472 * @arg @ref LL_HSEM_SEMAPHORE_8 00473 * @arg @ref LL_HSEM_SEMAPHORE_9 00474 * @arg @ref LL_HSEM_SEMAPHORE_10 00475 * @arg @ref LL_HSEM_SEMAPHORE_11 00476 * @arg @ref LL_HSEM_SEMAPHORE_12 00477 * @arg @ref LL_HSEM_SEMAPHORE_13 00478 * @arg @ref LL_HSEM_SEMAPHORE_14 00479 * @arg @ref LL_HSEM_SEMAPHORE_15 00480 * @arg @ref LL_HSEM_SEMAPHORE_16 00481 * @arg @ref LL_HSEM_SEMAPHORE_17 00482 * @arg @ref LL_HSEM_SEMAPHORE_18 00483 * @arg @ref LL_HSEM_SEMAPHORE_19 00484 * @arg @ref LL_HSEM_SEMAPHORE_20 00485 * @arg @ref LL_HSEM_SEMAPHORE_21 00486 * @arg @ref LL_HSEM_SEMAPHORE_22 00487 * @arg @ref LL_HSEM_SEMAPHORE_23 00488 * @arg @ref LL_HSEM_SEMAPHORE_24 00489 * @arg @ref LL_HSEM_SEMAPHORE_25 00490 * @arg @ref LL_HSEM_SEMAPHORE_26 00491 * @arg @ref LL_HSEM_SEMAPHORE_27 00492 * @arg @ref LL_HSEM_SEMAPHORE_28 00493 * @arg @ref LL_HSEM_SEMAPHORE_29 00494 * @arg @ref LL_HSEM_SEMAPHORE_30 00495 * @arg @ref LL_HSEM_SEMAPHORE_31 00496 * @arg @ref LL_HSEM_SEMAPHORE_ALL 00497 * @retval None 00498 */ 00499 __STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 00500 { 00501 SET_BIT(HSEMx->C2IER, SemaphoreMask); 00502 } 00503 00504 /** 00505 * @brief Disable interrupt. 00506 * @rmtoll C2IER ISEM LL_HSEM_DisableIT_C2IER 00507 * @param HSEMx HSEM Instance. 00508 * @param SemaphoreMask This parameter can be a combination of the following values: 00509 * @arg @ref LL_HSEM_SEMAPHORE_0 00510 * @arg @ref LL_HSEM_SEMAPHORE_1 00511 * @arg @ref LL_HSEM_SEMAPHORE_2 00512 * @arg @ref LL_HSEM_SEMAPHORE_3 00513 * @arg @ref LL_HSEM_SEMAPHORE_4 00514 * @arg @ref LL_HSEM_SEMAPHORE_5 00515 * @arg @ref LL_HSEM_SEMAPHORE_6 00516 * @arg @ref LL_HSEM_SEMAPHORE_7 00517 * @arg @ref LL_HSEM_SEMAPHORE_8 00518 * @arg @ref LL_HSEM_SEMAPHORE_9 00519 * @arg @ref LL_HSEM_SEMAPHORE_10 00520 * @arg @ref LL_HSEM_SEMAPHORE_11 00521 * @arg @ref LL_HSEM_SEMAPHORE_12 00522 * @arg @ref LL_HSEM_SEMAPHORE_13 00523 * @arg @ref LL_HSEM_SEMAPHORE_14 00524 * @arg @ref LL_HSEM_SEMAPHORE_15 00525 * @arg @ref LL_HSEM_SEMAPHORE_16 00526 * @arg @ref LL_HSEM_SEMAPHORE_17 00527 * @arg @ref LL_HSEM_SEMAPHORE_18 00528 * @arg @ref LL_HSEM_SEMAPHORE_19 00529 * @arg @ref LL_HSEM_SEMAPHORE_20 00530 * @arg @ref LL_HSEM_SEMAPHORE_21 00531 * @arg @ref LL_HSEM_SEMAPHORE_22 00532 * @arg @ref LL_HSEM_SEMAPHORE_23 00533 * @arg @ref LL_HSEM_SEMAPHORE_24 00534 * @arg @ref LL_HSEM_SEMAPHORE_25 00535 * @arg @ref LL_HSEM_SEMAPHORE_26 00536 * @arg @ref LL_HSEM_SEMAPHORE_27 00537 * @arg @ref LL_HSEM_SEMAPHORE_28 00538 * @arg @ref LL_HSEM_SEMAPHORE_29 00539 * @arg @ref LL_HSEM_SEMAPHORE_30 00540 * @arg @ref LL_HSEM_SEMAPHORE_31 00541 * @arg @ref LL_HSEM_SEMAPHORE_ALL 00542 * @retval None 00543 */ 00544 __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 00545 { 00546 CLEAR_BIT(HSEMx->C2IER, SemaphoreMask); 00547 } 00548 00549 /** 00550 * @brief Check if interrupt is enabled. 00551 * @rmtoll C2IER ISEM LL_HSEM_IsEnabledIT_C2IER 00552 * @param HSEMx HSEM Instance. 00553 * @param SemaphoreMask This parameter can be a combination of the following values: 00554 * @arg @ref LL_HSEM_SEMAPHORE_0 00555 * @arg @ref LL_HSEM_SEMAPHORE_1 00556 * @arg @ref LL_HSEM_SEMAPHORE_2 00557 * @arg @ref LL_HSEM_SEMAPHORE_3 00558 * @arg @ref LL_HSEM_SEMAPHORE_4 00559 * @arg @ref LL_HSEM_SEMAPHORE_5 00560 * @arg @ref LL_HSEM_SEMAPHORE_6 00561 * @arg @ref LL_HSEM_SEMAPHORE_7 00562 * @arg @ref LL_HSEM_SEMAPHORE_8 00563 * @arg @ref LL_HSEM_SEMAPHORE_9 00564 * @arg @ref LL_HSEM_SEMAPHORE_10 00565 * @arg @ref LL_HSEM_SEMAPHORE_11 00566 * @arg @ref LL_HSEM_SEMAPHORE_12 00567 * @arg @ref LL_HSEM_SEMAPHORE_13 00568 * @arg @ref LL_HSEM_SEMAPHORE_14 00569 * @arg @ref LL_HSEM_SEMAPHORE_15 00570 * @arg @ref LL_HSEM_SEMAPHORE_16 00571 * @arg @ref LL_HSEM_SEMAPHORE_17 00572 * @arg @ref LL_HSEM_SEMAPHORE_18 00573 * @arg @ref LL_HSEM_SEMAPHORE_19 00574 * @arg @ref LL_HSEM_SEMAPHORE_20 00575 * @arg @ref LL_HSEM_SEMAPHORE_21 00576 * @arg @ref LL_HSEM_SEMAPHORE_22 00577 * @arg @ref LL_HSEM_SEMAPHORE_23 00578 * @arg @ref LL_HSEM_SEMAPHORE_24 00579 * @arg @ref LL_HSEM_SEMAPHORE_25 00580 * @arg @ref LL_HSEM_SEMAPHORE_26 00581 * @arg @ref LL_HSEM_SEMAPHORE_27 00582 * @arg @ref LL_HSEM_SEMAPHORE_28 00583 * @arg @ref LL_HSEM_SEMAPHORE_29 00584 * @arg @ref LL_HSEM_SEMAPHORE_30 00585 * @arg @ref LL_HSEM_SEMAPHORE_31 00586 * @arg @ref LL_HSEM_SEMAPHORE_ALL 00587 * @retval State of bit (1 or 0). 00588 */ 00589 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 00590 { 00591 return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); 00592 } 00593 #endif /* DUAL_CORE */ 00594 00595 /** 00596 * @} 00597 */ 00598 00599 /** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management 00600 * @{ 00601 */ 00602 00603 /** 00604 * @brief Clear interrupt status. 00605 * @rmtoll C1ICR ISEM LL_HSEM_ClearFlag_C1ICR 00606 * @param HSEMx HSEM Instance. 00607 * @param SemaphoreMask This parameter can be a combination of the following values: 00608 * @arg @ref LL_HSEM_SEMAPHORE_0 00609 * @arg @ref LL_HSEM_SEMAPHORE_1 00610 * @arg @ref LL_HSEM_SEMAPHORE_2 00611 * @arg @ref LL_HSEM_SEMAPHORE_3 00612 * @arg @ref LL_HSEM_SEMAPHORE_4 00613 * @arg @ref LL_HSEM_SEMAPHORE_5 00614 * @arg @ref LL_HSEM_SEMAPHORE_6 00615 * @arg @ref LL_HSEM_SEMAPHORE_7 00616 * @arg @ref LL_HSEM_SEMAPHORE_8 00617 * @arg @ref LL_HSEM_SEMAPHORE_9 00618 * @arg @ref LL_HSEM_SEMAPHORE_10 00619 * @arg @ref LL_HSEM_SEMAPHORE_11 00620 * @arg @ref LL_HSEM_SEMAPHORE_12 00621 * @arg @ref LL_HSEM_SEMAPHORE_13 00622 * @arg @ref LL_HSEM_SEMAPHORE_14 00623 * @arg @ref LL_HSEM_SEMAPHORE_15 00624 * @arg @ref LL_HSEM_SEMAPHORE_16 00625 * @arg @ref LL_HSEM_SEMAPHORE_17 00626 * @arg @ref LL_HSEM_SEMAPHORE_18 00627 * @arg @ref LL_HSEM_SEMAPHORE_19 00628 * @arg @ref LL_HSEM_SEMAPHORE_20 00629 * @arg @ref LL_HSEM_SEMAPHORE_21 00630 * @arg @ref LL_HSEM_SEMAPHORE_22 00631 * @arg @ref LL_HSEM_SEMAPHORE_23 00632 * @arg @ref LL_HSEM_SEMAPHORE_24 00633 * @arg @ref LL_HSEM_SEMAPHORE_25 00634 * @arg @ref LL_HSEM_SEMAPHORE_26 00635 * @arg @ref LL_HSEM_SEMAPHORE_27 00636 * @arg @ref LL_HSEM_SEMAPHORE_28 00637 * @arg @ref LL_HSEM_SEMAPHORE_29 00638 * @arg @ref LL_HSEM_SEMAPHORE_30 00639 * @arg @ref LL_HSEM_SEMAPHORE_31 00640 * @arg @ref LL_HSEM_SEMAPHORE_ALL 00641 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 00642 * depends on devices. 00643 * @retval None 00644 */ 00645 __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 00646 { 00647 WRITE_REG(HSEMx->C1ICR, SemaphoreMask); 00648 } 00649 00650 /** 00651 * @brief Get interrupt status from ISR register. 00652 * @rmtoll C1ISR ISEM LL_HSEM_IsActiveFlag_C1ISR 00653 * @param HSEMx HSEM Instance. 00654 * @param SemaphoreMask This parameter can be a combination of the following values: 00655 * @arg @ref LL_HSEM_SEMAPHORE_0 00656 * @arg @ref LL_HSEM_SEMAPHORE_1 00657 * @arg @ref LL_HSEM_SEMAPHORE_2 00658 * @arg @ref LL_HSEM_SEMAPHORE_3 00659 * @arg @ref LL_HSEM_SEMAPHORE_4 00660 * @arg @ref LL_HSEM_SEMAPHORE_5 00661 * @arg @ref LL_HSEM_SEMAPHORE_6 00662 * @arg @ref LL_HSEM_SEMAPHORE_7 00663 * @arg @ref LL_HSEM_SEMAPHORE_8 00664 * @arg @ref LL_HSEM_SEMAPHORE_9 00665 * @arg @ref LL_HSEM_SEMAPHORE_10 00666 * @arg @ref LL_HSEM_SEMAPHORE_11 00667 * @arg @ref LL_HSEM_SEMAPHORE_12 00668 * @arg @ref LL_HSEM_SEMAPHORE_13 00669 * @arg @ref LL_HSEM_SEMAPHORE_14 00670 * @arg @ref LL_HSEM_SEMAPHORE_15 00671 * @arg @ref LL_HSEM_SEMAPHORE_16 00672 * @arg @ref LL_HSEM_SEMAPHORE_17 00673 * @arg @ref LL_HSEM_SEMAPHORE_18 00674 * @arg @ref LL_HSEM_SEMAPHORE_19 00675 * @arg @ref LL_HSEM_SEMAPHORE_20 00676 * @arg @ref LL_HSEM_SEMAPHORE_21 00677 * @arg @ref LL_HSEM_SEMAPHORE_22 00678 * @arg @ref LL_HSEM_SEMAPHORE_23 00679 * @arg @ref LL_HSEM_SEMAPHORE_24 00680 * @arg @ref LL_HSEM_SEMAPHORE_25 00681 * @arg @ref LL_HSEM_SEMAPHORE_26 00682 * @arg @ref LL_HSEM_SEMAPHORE_27 00683 * @arg @ref LL_HSEM_SEMAPHORE_28 00684 * @arg @ref LL_HSEM_SEMAPHORE_29 00685 * @arg @ref LL_HSEM_SEMAPHORE_30 00686 * @arg @ref LL_HSEM_SEMAPHORE_31 00687 * @arg @ref LL_HSEM_SEMAPHORE_ALL 00688 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 00689 * depends on devices. 00690 * @retval State of bit (1 or 0). 00691 */ 00692 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 00693 { 00694 return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); 00695 } 00696 00697 /** 00698 * @brief Get interrupt status from MISR register. 00699 * @rmtoll C1MISR ISEM LL_HSEM_IsActiveFlag_C1MISR 00700 * @param HSEMx HSEM Instance. 00701 * @param SemaphoreMask This parameter can be a combination of the following values: 00702 * @arg @ref LL_HSEM_SEMAPHORE_0 00703 * @arg @ref LL_HSEM_SEMAPHORE_1 00704 * @arg @ref LL_HSEM_SEMAPHORE_2 00705 * @arg @ref LL_HSEM_SEMAPHORE_3 00706 * @arg @ref LL_HSEM_SEMAPHORE_4 00707 * @arg @ref LL_HSEM_SEMAPHORE_5 00708 * @arg @ref LL_HSEM_SEMAPHORE_6 00709 * @arg @ref LL_HSEM_SEMAPHORE_7 00710 * @arg @ref LL_HSEM_SEMAPHORE_8 00711 * @arg @ref LL_HSEM_SEMAPHORE_9 00712 * @arg @ref LL_HSEM_SEMAPHORE_10 00713 * @arg @ref LL_HSEM_SEMAPHORE_11 00714 * @arg @ref LL_HSEM_SEMAPHORE_12 00715 * @arg @ref LL_HSEM_SEMAPHORE_13 00716 * @arg @ref LL_HSEM_SEMAPHORE_14 00717 * @arg @ref LL_HSEM_SEMAPHORE_15 00718 * @arg @ref LL_HSEM_SEMAPHORE_16 00719 * @arg @ref LL_HSEM_SEMAPHORE_17 00720 * @arg @ref LL_HSEM_SEMAPHORE_18 00721 * @arg @ref LL_HSEM_SEMAPHORE_19 00722 * @arg @ref LL_HSEM_SEMAPHORE_20 00723 * @arg @ref LL_HSEM_SEMAPHORE_21 00724 * @arg @ref LL_HSEM_SEMAPHORE_22 00725 * @arg @ref LL_HSEM_SEMAPHORE_23 00726 * @arg @ref LL_HSEM_SEMAPHORE_24 00727 * @arg @ref LL_HSEM_SEMAPHORE_25 00728 * @arg @ref LL_HSEM_SEMAPHORE_26 00729 * @arg @ref LL_HSEM_SEMAPHORE_27 00730 * @arg @ref LL_HSEM_SEMAPHORE_28 00731 * @arg @ref LL_HSEM_SEMAPHORE_29 00732 * @arg @ref LL_HSEM_SEMAPHORE_30 00733 * @arg @ref LL_HSEM_SEMAPHORE_31 00734 * @arg @ref LL_HSEM_SEMAPHORE_ALL 00735 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 00736 * depends on devices. 00737 * @retval State of bit (1 or 0). 00738 */ 00739 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 00740 { 00741 return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); 00742 } 00743 00744 #if defined(DUAL_CORE) 00745 /** 00746 * @brief Clear interrupt status. 00747 * @rmtoll C2ICR ISEM LL_HSEM_ClearFlag_C2ICR 00748 * @param HSEMx HSEM Instance. 00749 * @param SemaphoreMask This parameter can be a combination of the following values: 00750 * @arg @ref LL_HSEM_SEMAPHORE_0 00751 * @arg @ref LL_HSEM_SEMAPHORE_1 00752 * @arg @ref LL_HSEM_SEMAPHORE_2 00753 * @arg @ref LL_HSEM_SEMAPHORE_3 00754 * @arg @ref LL_HSEM_SEMAPHORE_4 00755 * @arg @ref LL_HSEM_SEMAPHORE_5 00756 * @arg @ref LL_HSEM_SEMAPHORE_6 00757 * @arg @ref LL_HSEM_SEMAPHORE_7 00758 * @arg @ref LL_HSEM_SEMAPHORE_8 00759 * @arg @ref LL_HSEM_SEMAPHORE_9 00760 * @arg @ref LL_HSEM_SEMAPHORE_10 00761 * @arg @ref LL_HSEM_SEMAPHORE_11 00762 * @arg @ref LL_HSEM_SEMAPHORE_12 00763 * @arg @ref LL_HSEM_SEMAPHORE_13 00764 * @arg @ref LL_HSEM_SEMAPHORE_14 00765 * @arg @ref LL_HSEM_SEMAPHORE_15 00766 * @arg @ref LL_HSEM_SEMAPHORE_16 00767 * @arg @ref LL_HSEM_SEMAPHORE_17 00768 * @arg @ref LL_HSEM_SEMAPHORE_18 00769 * @arg @ref LL_HSEM_SEMAPHORE_19 00770 * @arg @ref LL_HSEM_SEMAPHORE_20 00771 * @arg @ref LL_HSEM_SEMAPHORE_21 00772 * @arg @ref LL_HSEM_SEMAPHORE_22 00773 * @arg @ref LL_HSEM_SEMAPHORE_23 00774 * @arg @ref LL_HSEM_SEMAPHORE_24 00775 * @arg @ref LL_HSEM_SEMAPHORE_25 00776 * @arg @ref LL_HSEM_SEMAPHORE_26 00777 * @arg @ref LL_HSEM_SEMAPHORE_27 00778 * @arg @ref LL_HSEM_SEMAPHORE_28 00779 * @arg @ref LL_HSEM_SEMAPHORE_29 00780 * @arg @ref LL_HSEM_SEMAPHORE_30 00781 * @arg @ref LL_HSEM_SEMAPHORE_31 00782 * @arg @ref LL_HSEM_SEMAPHORE_ALL 00783 * @retval None 00784 */ 00785 __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 00786 { 00787 WRITE_REG(HSEMx->C2ICR, SemaphoreMask); 00788 } 00789 00790 /** 00791 * @brief Get interrupt status from ISR register. 00792 * @rmtoll C2ISR ISEM LL_HSEM_IsActiveFlag_C2ISR 00793 * @param HSEMx HSEM Instance. 00794 * @param SemaphoreMask This parameter can be a combination of the following values: 00795 * @arg @ref LL_HSEM_SEMAPHORE_0 00796 * @arg @ref LL_HSEM_SEMAPHORE_1 00797 * @arg @ref LL_HSEM_SEMAPHORE_2 00798 * @arg @ref LL_HSEM_SEMAPHORE_3 00799 * @arg @ref LL_HSEM_SEMAPHORE_4 00800 * @arg @ref LL_HSEM_SEMAPHORE_5 00801 * @arg @ref LL_HSEM_SEMAPHORE_6 00802 * @arg @ref LL_HSEM_SEMAPHORE_7 00803 * @arg @ref LL_HSEM_SEMAPHORE_8 00804 * @arg @ref LL_HSEM_SEMAPHORE_9 00805 * @arg @ref LL_HSEM_SEMAPHORE_10 00806 * @arg @ref LL_HSEM_SEMAPHORE_11 00807 * @arg @ref LL_HSEM_SEMAPHORE_12 00808 * @arg @ref LL_HSEM_SEMAPHORE_13 00809 * @arg @ref LL_HSEM_SEMAPHORE_14 00810 * @arg @ref LL_HSEM_SEMAPHORE_15 00811 * @arg @ref LL_HSEM_SEMAPHORE_16 00812 * @arg @ref LL_HSEM_SEMAPHORE_17 00813 * @arg @ref LL_HSEM_SEMAPHORE_18 00814 * @arg @ref LL_HSEM_SEMAPHORE_19 00815 * @arg @ref LL_HSEM_SEMAPHORE_20 00816 * @arg @ref LL_HSEM_SEMAPHORE_21 00817 * @arg @ref LL_HSEM_SEMAPHORE_22 00818 * @arg @ref LL_HSEM_SEMAPHORE_23 00819 * @arg @ref LL_HSEM_SEMAPHORE_24 00820 * @arg @ref LL_HSEM_SEMAPHORE_25 00821 * @arg @ref LL_HSEM_SEMAPHORE_26 00822 * @arg @ref LL_HSEM_SEMAPHORE_27 00823 * @arg @ref LL_HSEM_SEMAPHORE_28 00824 * @arg @ref LL_HSEM_SEMAPHORE_29 00825 * @arg @ref LL_HSEM_SEMAPHORE_30 00826 * @arg @ref LL_HSEM_SEMAPHORE_31 00827 * @arg @ref LL_HSEM_SEMAPHORE_ALL 00828 * @retval State of bit (1 or 0). 00829 */ 00830 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 00831 { 00832 return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); 00833 } 00834 00835 /** 00836 * @brief Get interrupt status from MISR register. 00837 * @rmtoll C2MISR ISEM LL_HSEM_IsActiveFlag_C2MISR 00838 * @param HSEMx HSEM Instance. 00839 * @param SemaphoreMask This parameter can be a combination of the following values: 00840 * @arg @ref LL_HSEM_SEMAPHORE_0 00841 * @arg @ref LL_HSEM_SEMAPHORE_1 00842 * @arg @ref LL_HSEM_SEMAPHORE_2 00843 * @arg @ref LL_HSEM_SEMAPHORE_3 00844 * @arg @ref LL_HSEM_SEMAPHORE_4 00845 * @arg @ref LL_HSEM_SEMAPHORE_5 00846 * @arg @ref LL_HSEM_SEMAPHORE_6 00847 * @arg @ref LL_HSEM_SEMAPHORE_7 00848 * @arg @ref LL_HSEM_SEMAPHORE_8 00849 * @arg @ref LL_HSEM_SEMAPHORE_9 00850 * @arg @ref LL_HSEM_SEMAPHORE_10 00851 * @arg @ref LL_HSEM_SEMAPHORE_11 00852 * @arg @ref LL_HSEM_SEMAPHORE_12 00853 * @arg @ref LL_HSEM_SEMAPHORE_13 00854 * @arg @ref LL_HSEM_SEMAPHORE_14 00855 * @arg @ref LL_HSEM_SEMAPHORE_15 00856 * @arg @ref LL_HSEM_SEMAPHORE_16 00857 * @arg @ref LL_HSEM_SEMAPHORE_17 00858 * @arg @ref LL_HSEM_SEMAPHORE_18 00859 * @arg @ref LL_HSEM_SEMAPHORE_19 00860 * @arg @ref LL_HSEM_SEMAPHORE_20 00861 * @arg @ref LL_HSEM_SEMAPHORE_21 00862 * @arg @ref LL_HSEM_SEMAPHORE_22 00863 * @arg @ref LL_HSEM_SEMAPHORE_23 00864 * @arg @ref LL_HSEM_SEMAPHORE_24 00865 * @arg @ref LL_HSEM_SEMAPHORE_25 00866 * @arg @ref LL_HSEM_SEMAPHORE_26 00867 * @arg @ref LL_HSEM_SEMAPHORE_27 00868 * @arg @ref LL_HSEM_SEMAPHORE_28 00869 * @arg @ref LL_HSEM_SEMAPHORE_29 00870 * @arg @ref LL_HSEM_SEMAPHORE_30 00871 * @arg @ref LL_HSEM_SEMAPHORE_31 00872 * @arg @ref LL_HSEM_SEMAPHORE_ALL 00873 * @retval State of bit (1 or 0). 00874 */ 00875 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 00876 { 00877 return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); 00878 } 00879 #endif /* DUAL_CORE */ 00880 /** 00881 * @} 00882 */ 00883 00884 /** 00885 * @} 00886 */ 00887 00888 /** 00889 * @} 00890 */ 00891 00892 #endif /* defined(HSEM) */ 00893 00894 /** 00895 * @} 00896 */ 00897 00898 #ifdef __cplusplus 00899 } 00900 #endif 00901 00902 #endif /* __STM32H7xx_LL_HSEM_H */
1.7.6.1