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STM32H735xx HAL User Manual
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Header file of RCC LL module. More...
#include "stm32h7xx.h"#include <math.h>Go to the source code of this file.
Data Structures | |
| struct | LL_RCC_ClocksTypeDef |
| RCC Clocks Frequency Structure. More... | |
| struct | LL_PLL_ClocksTypeDef |
| PLL Clocks Frequency Structure. More... | |
Defines | |
| #define | D1CCIP 0x0UL |
| #define | D2CCIP1 0x4UL |
| #define | D2CCIP2 0x8UL |
| #define | D3CCIP 0xCUL |
| #define | LL_RCC_REG_SHIFT 0U |
| #define | LL_RCC_POS_SHIFT 8U |
| #define | LL_RCC_CONFIG_SHIFT 16U |
| #define | LL_RCC_MASK_SHIFT 24U |
| #define | LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL) |
| #define | LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) |
| #define | LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) |
| #define | LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL) |
| #define | LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) |
| #define | HSI48_VALUE 48000000U |
| #define | LL_RCC_HSI_DIV1 RCC_CR_HSIDIV_1 |
| #define | LL_RCC_HSI_DIV2 RCC_CR_HSIDIV_2 |
| #define | LL_RCC_HSI_DIV4 RCC_CR_HSIDIV_4 |
| #define | LL_RCC_HSI_DIV8 RCC_CR_HSIDIV_8 |
| #define | LL_RCC_LSEDRIVE_LOW (uint32_t)(0x00000000U) |
| #define | LL_RCC_LSEDRIVE_MEDIUMLOW (uint32_t)(RCC_BDCR_LSEDRV_0) |
| #define | LL_RCC_LSEDRIVE_MEDIUMHIGH (uint32_t)(RCC_BDCR_LSEDRV_1) |
| #define | LL_RCC_LSEDRIVE_HIGH (uint32_t)(RCC_BDCR_LSEDRV) |
| #define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI |
| #define | LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_CSI |
| #define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE |
| #define | LL_RCC_SYS_CLKSOURCE_PLL1 RCC_CFGR_SW_PLL1 |
| #define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI |
| #define | LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI |
| #define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE |
| #define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1 |
| #define | LL_RCC_SYSWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U) |
| #define | LL_RCC_SYSWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPWUCK) |
| #define | LL_RCC_KERWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U) |
| #define | LL_RCC_KERWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPKERWUCK) |
| #define | LL_RCC_SYSCLK_DIV_1 RCC_D1CFGR_D1CPRE_DIV1 |
| #define | LL_RCC_SYSCLK_DIV_2 RCC_D1CFGR_D1CPRE_DIV2 |
| #define | LL_RCC_SYSCLK_DIV_4 RCC_D1CFGR_D1CPRE_DIV4 |
| #define | LL_RCC_SYSCLK_DIV_8 RCC_D1CFGR_D1CPRE_DIV8 |
| #define | LL_RCC_SYSCLK_DIV_16 RCC_D1CFGR_D1CPRE_DIV16 |
| #define | LL_RCC_SYSCLK_DIV_64 RCC_D1CFGR_D1CPRE_DIV64 |
| #define | LL_RCC_SYSCLK_DIV_128 RCC_D1CFGR_D1CPRE_DIV128 |
| #define | LL_RCC_SYSCLK_DIV_256 RCC_D1CFGR_D1CPRE_DIV256 |
| #define | LL_RCC_SYSCLK_DIV_512 RCC_D1CFGR_D1CPRE_DIV512 |
| #define | LL_RCC_AHB_DIV_1 RCC_D1CFGR_HPRE_DIV1 |
| #define | LL_RCC_AHB_DIV_2 RCC_D1CFGR_HPRE_DIV2 |
| #define | LL_RCC_AHB_DIV_4 RCC_D1CFGR_HPRE_DIV4 |
| #define | LL_RCC_AHB_DIV_8 RCC_D1CFGR_HPRE_DIV8 |
| #define | LL_RCC_AHB_DIV_16 RCC_D1CFGR_HPRE_DIV16 |
| #define | LL_RCC_AHB_DIV_64 RCC_D1CFGR_HPRE_DIV64 |
| #define | LL_RCC_AHB_DIV_128 RCC_D1CFGR_HPRE_DIV128 |
| #define | LL_RCC_AHB_DIV_256 RCC_D1CFGR_HPRE_DIV256 |
| #define | LL_RCC_AHB_DIV_512 RCC_D1CFGR_HPRE_DIV512 |
| #define | LL_RCC_APB1_DIV_1 RCC_D2CFGR_D2PPRE1_DIV1 |
| #define | LL_RCC_APB1_DIV_2 RCC_D2CFGR_D2PPRE1_DIV2 |
| #define | LL_RCC_APB1_DIV_4 RCC_D2CFGR_D2PPRE1_DIV4 |
| #define | LL_RCC_APB1_DIV_8 RCC_D2CFGR_D2PPRE1_DIV8 |
| #define | LL_RCC_APB1_DIV_16 RCC_D2CFGR_D2PPRE1_DIV16 |
| #define | LL_RCC_APB2_DIV_1 RCC_D2CFGR_D2PPRE2_DIV1 |
| #define | LL_RCC_APB2_DIV_2 RCC_D2CFGR_D2PPRE2_DIV2 |
| #define | LL_RCC_APB2_DIV_4 RCC_D2CFGR_D2PPRE2_DIV4 |
| #define | LL_RCC_APB2_DIV_8 RCC_D2CFGR_D2PPRE2_DIV8 |
| #define | LL_RCC_APB2_DIV_16 RCC_D2CFGR_D2PPRE2_DIV16 |
| #define | LL_RCC_APB3_DIV_1 RCC_D1CFGR_D1PPRE_DIV1 |
| #define | LL_RCC_APB3_DIV_2 RCC_D1CFGR_D1PPRE_DIV2 |
| #define | LL_RCC_APB3_DIV_4 RCC_D1CFGR_D1PPRE_DIV4 |
| #define | LL_RCC_APB3_DIV_8 RCC_D1CFGR_D1PPRE_DIV8 |
| #define | LL_RCC_APB3_DIV_16 RCC_D1CFGR_D1PPRE_DIV16 |
| #define | LL_RCC_APB4_DIV_1 RCC_D3CFGR_D3PPRE_DIV1 |
| #define | LL_RCC_APB4_DIV_2 RCC_D3CFGR_D3PPRE_DIV2 |
| #define | LL_RCC_APB4_DIV_4 RCC_D3CFGR_D3PPRE_DIV4 |
| #define | LL_RCC_APB4_DIV_8 RCC_D3CFGR_D3PPRE_DIV8 |
| #define | LL_RCC_APB4_DIV_16 RCC_D3CFGR_D3PPRE_DIV16 |
| #define | LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U) |
| #define | LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0) |
| #define | LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1) |
| #define | LL_RCC_MCO1SOURCE_PLL1QCLK (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) |
| #define | LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2) |
| #define | LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U) |
| #define | LL_RCC_MCO2SOURCE_PLL2PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0) |
| #define | LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1) |
| #define | LL_RCC_MCO2SOURCE_PLL1PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) |
| #define | LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2) |
| #define | LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0) |
| #define | LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0) |
| #define | LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1) |
| #define | LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1) |
| #define | LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2) |
| #define | LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) |
| #define | LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) |
| #define | LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) |
| #define | LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3) |
| #define | LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3) |
| #define | LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) |
| #define | LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) |
| #define | LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) |
| #define | LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) |
| #define | LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) |
| #define | LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE) |
| #define | LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0) |
| #define | LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1) |
| #define | LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1) |
| #define | LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2) |
| #define | LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2) |
| #define | LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2) |
| #define | LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2) |
| #define | LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3) |
| #define | LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3) |
| #define | LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3) |
| #define | LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3) |
| #define | LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) |
| #define | LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) |
| #define | LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) |
| #define | LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE) |
| #define | LL_RCC_RTC_NOCLOCK (uint32_t)(0x00000000U) |
| #define | LL_RCC_RTC_HSE_DIV_2 (uint32_t)(RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_3 (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_4 (uint32_t)(RCC_CFGR_RTCPRE_2) |
| #define | LL_RCC_RTC_HSE_DIV_5 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_6 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_7 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_8 (uint32_t)(RCC_CFGR_RTCPRE_3) |
| #define | LL_RCC_RTC_HSE_DIV_9 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_10 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_11 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_12 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) |
| #define | LL_RCC_RTC_HSE_DIV_13 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_14 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_15 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_16 (uint32_t)(RCC_CFGR_RTCPRE_4) |
| #define | LL_RCC_RTC_HSE_DIV_17 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_18 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_19 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_20 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) |
| #define | LL_RCC_RTC_HSE_DIV_21 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_22 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_23 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_24 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) |
| #define | LL_RCC_RTC_HSE_DIV_25 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_26 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_27 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_28 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) |
| #define | LL_RCC_RTC_HSE_DIV_29 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_30 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_31 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_32 (uint32_t)(RCC_CFGR_RTCPRE_5) |
| #define | LL_RCC_RTC_HSE_DIV_33 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_34 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_35 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_36 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2) |
| #define | LL_RCC_RTC_HSE_DIV_37 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_38 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_39 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_40 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3) |
| #define | LL_RCC_RTC_HSE_DIV_41 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_42 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_43 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_44 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) |
| #define | LL_RCC_RTC_HSE_DIV_45 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_46 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_47 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_48 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4) |
| #define | LL_RCC_RTC_HSE_DIV_49 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_50 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_51 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_52 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) |
| #define | LL_RCC_RTC_HSE_DIV_53 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_54 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_55 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_56 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) |
| #define | LL_RCC_RTC_HSE_DIV_57 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_58 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_59 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_60 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) |
| #define | LL_RCC_RTC_HSE_DIV_61 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_RTC_HSE_DIV_62 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) |
| #define | LL_RCC_RTC_HSE_DIV_63 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
| #define | LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U) |
| #define | LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0) |
| #define | LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_1) |
| #define | LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1) |
| #define | LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_2) |
| #define | LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2) |
| #define | LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2 |
| #define | LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q |
| #define | LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q |
| #define | LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI |
| #define | LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI |
| #define | LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE |
| #define | LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U) |
| #define | LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0) |
| #define | LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1) |
| #define | LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1) |
| #define | LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2) |
| #define | LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2) |
| #define | LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U) |
| #define | LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_D3CCIPR_LPUART1SEL_0) |
| #define | LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_D3CCIPR_LPUART1SEL_1) |
| #define | LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1) |
| #define | LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_D3CCIPR_LPUART1SEL_2) |
| #define | LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2) |
| #define | LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U) |
| #define | LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0) |
| #define | LL_RCC_I2C1235_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_1) |
| #define | LL_RCC_I2C1235_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1) |
| #define | LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_RCC_I2C1235_CLKSOURCE_PCLK1 |
| #define | LL_RCC_I2C123_CLKSOURCE_PLL3R LL_RCC_I2C1235_CLKSOURCE_PLL3R |
| #define | LL_RCC_I2C123_CLKSOURCE_HSI LL_RCC_I2C1235_CLKSOURCE_HSI |
| #define | LL_RCC_I2C123_CLKSOURCE_CSI LL_RCC_I2C1235_CLKSOURCE_CSI |
| #define | LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U) |
| #define | LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0) |
| #define | LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_1) |
| #define | LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1) |
| #define | LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U) |
| #define | LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0) |
| #define | LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_1) |
| #define | LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1) |
| #define | LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_2) |
| #define | LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2) |
| #define | LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U) |
| #define | LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0) |
| #define | LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_1) |
| #define | LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1) |
| #define | LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_2) |
| #define | LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2) |
| #define | LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U) |
| #define | LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0) |
| #define | LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1) |
| #define | LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1) |
| #define | LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2) |
| #define | LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2) |
| #define | LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U) |
| #define | LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0) |
| #define | LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_1) |
| #define | LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1) |
| #define | LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_2) |
| #define | LL_RCC_SAI4A_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U) |
| #define | LL_RCC_SAI4A_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0) |
| #define | LL_RCC_SAI4A_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_1) |
| #define | LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1) |
| #define | LL_RCC_SAI4A_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2) |
| #define | LL_RCC_SAI4A_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0) |
| #define | LL_RCC_SAI4B_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U) |
| #define | LL_RCC_SAI4B_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0) |
| #define | LL_RCC_SAI4B_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_1) |
| #define | LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1) |
| #define | LL_RCC_SAI4B_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2) |
| #define | LL_RCC_SAI4B_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0) |
| #define | LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U) |
| #define | LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_SDMMCSEL) |
| #define | LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U) |
| #define | LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_RNGSEL_0) |
| #define | LL_RCC_RNG_CLKSOURCE_LSE (RCC_D2CCIP2R_RNGSEL_1) |
| #define | LL_RCC_RNG_CLKSOURCE_LSI (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0) |
| #define | LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U) |
| #define | LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_USBSEL_0) |
| #define | LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_D2CCIP2R_USBSEL_1) |
| #define | LL_RCC_USB_CLKSOURCE_HSI48 (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0) |
| #define | LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U) |
| #define | LL_RCC_CEC_CLKSOURCE_LSI (RCC_D2CCIP2R_CECSEL_0) |
| #define | LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_D2CCIP2R_CECSEL_1) |
| #define | LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U) |
| #define | LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_D2CCIP1R_DFSDM1SEL) |
| #define | LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U) |
| #define | LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_D1CCIPR_FMCSEL_0) |
| #define | LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_FMCSEL_1) |
| #define | LL_RCC_FMC_CLKSOURCE_CLKP (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1) |
| #define | LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U) |
| #define | LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_OCTOSPISEL_0) |
| #define | LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_OCTOSPISEL_1) |
| #define | LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_OCTOSPISEL_0 | RCC_D1CCIPR_OCTOSPISEL_1) |
| #define | LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U) |
| #define | LL_RCC_CLKP_CLKSOURCE_CSI (RCC_D1CCIPR_CKPERSEL_0) |
| #define | LL_RCC_CLKP_CLKSOURCE_HSE (RCC_D1CCIPR_CKPERSEL_1) |
| #define | LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U) |
| #define | LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0) |
| #define | LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1) |
| #define | LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1) |
| #define | LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2) |
| #define | LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U) |
| #define | LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0) |
| #define | LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_1) |
| #define | LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1) |
| #define | LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_2) |
| #define | LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2) |
| #define | LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U) |
| #define | LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0) |
| #define | LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_1) |
| #define | LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1) |
| #define | LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_2) |
| #define | LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2) |
| #define | LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U) |
| #define | LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_D2CCIP1R_SPDIFSEL_0) |
| #define | LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_D2CCIP1R_SPDIFSEL_1) |
| #define | LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1) |
| #define | LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U) |
| #define | LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_D2CCIP1R_FDCANSEL_0) |
| #define | LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_D2CCIP1R_FDCANSEL_1) |
| #define | LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U) |
| #define | LL_RCC_SWP_CLKSOURCE_HSI (RCC_D2CCIP1R_SWPSEL) |
| #define | LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U) |
| #define | LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_D3CCIPR_ADCSEL_0) |
| #define | LL_RCC_ADC_CLKSOURCE_CLKP (RCC_D3CCIPR_ADCSEL_1) |
| #define | LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U) |
| #define | LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE |
| #define | LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U) |
| #define | LL_RCC_LPUART1_CLKSOURCE RCC_D3CCIPR_LPUART1SEL |
| #define | LL_RCC_I2C1235_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U) |
| #define | LL_RCC_I2C123_CLKSOURCE LL_RCC_I2C1235_CLKSOURCE |
| #define | LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U) |
| #define | LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U) |
| #define | LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U) |
| #define | LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U) |
| #define | LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U) |
| #define | LL_RCC_SAI4A_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U) |
| #define | LL_RCC_SAI4B_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U) |
| #define | LL_RCC_SDMMC_CLKSOURCE RCC_D1CCIPR_SDMMCSEL |
| #define | LL_RCC_RNG_CLKSOURCE RCC_D2CCIP2R_RNGSEL |
| #define | LL_RCC_USB_CLKSOURCE RCC_D2CCIP2R_USBSEL |
| #define | LL_RCC_CEC_CLKSOURCE RCC_D2CCIP2R_CECSEL |
| #define | LL_RCC_DFSDM1_CLKSOURCE RCC_D2CCIP1R_DFSDM1SEL |
| #define | LL_RCC_FMC_CLKSOURCE RCC_D1CCIPR_FMCSEL |
| #define | LL_RCC_OSPI_CLKSOURCE RCC_D1CCIPR_OCTOSPISEL |
| #define | LL_RCC_CLKP_CLKSOURCE RCC_D1CCIPR_CKPERSEL |
| #define | LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U) |
| #define | LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U) |
| #define | LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U) |
| #define | LL_RCC_SPDIF_CLKSOURCE RCC_D2CCIP1R_SPDIFSEL |
| #define | LL_RCC_FDCAN_CLKSOURCE RCC_D2CCIP1R_FDCANSEL |
| #define | LL_RCC_SWP_CLKSOURCE RCC_D2CCIP1R_SWPSEL |
| #define | LL_RCC_ADC_CLKSOURCE RCC_D3CCIPR_ADCSEL |
| #define | LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000U) |
| #define | LL_RCC_RTC_CLKSOURCE_LSE (uint32_t)(RCC_BDCR_RTCSEL_0) |
| #define | LL_RCC_RTC_CLKSOURCE_LSI (uint32_t)(RCC_BDCR_RTCSEL_1) |
| #define | LL_RCC_RTC_CLKSOURCE_HSE (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1) |
| #define | LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U) |
| #define | LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR_TIMPRE) |
| #define | LL_RCC_PLLSOURCE_HSI RCC_PLLCKSELR_PLLSRC_HSI |
| #define | LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_CSI |
| #define | LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_HSE |
| #define | LL_RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC_NONE |
| #define | LL_RCC_PLLINPUTRANGE_1_2 (uint32_t)(0x00000000U) |
| #define | LL_RCC_PLLINPUTRANGE_2_4 (uint32_t)(0x00000001) |
| #define | LL_RCC_PLLINPUTRANGE_4_8 (uint32_t)(0x00000002) |
| #define | LL_RCC_PLLINPUTRANGE_8_16 (uint32_t)(0x00000003) |
| #define | LL_RCC_PLLVCORANGE_WIDE (uint32_t)(0x00000000U) /* VCO output range: 192 to 836 MHz OR 128 to 544 MHz (*) */ |
| #define | LL_RCC_PLLVCORANGE_MEDIUM (uint32_t)(0x00000001) /* VCO output range: 150 to 420 MHz */ |
| #define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) |
| Write a value in RCC register. | |
| #define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) |
| Read a value in RCC register. | |
| #define | LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU)) |
| Helper macro to calculate the SYSCLK frequency. | |
| #define | LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)) |
| Helper macro to calculate the HCLK frequency. | |
| #define | LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)) |
| Helper macro to calculate the PCLK1 frequency (ABP1) | |
| #define | LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)) |
| Helper macro to calculate the PCLK2 frequency (ABP2) | |
| #define | LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU)) |
| Helper macro to calculate the PCLK3 frequency (APB3) | |
| #define | LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU)) |
| Helper macro to calculate the PCLK4 frequency (ABP4) | |
| #define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U |
| #define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU |
Functions | |
| __STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void) |
| Enable the Clock Security System. | |
| __STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void) |
| Enable HSE external oscillator (HSE Bypass) | |
| __STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void) |
| Disable HSE external oscillator (HSE Bypass) | |
| __STATIC_INLINE void | LL_RCC_HSE_Enable (void) |
| Enable HSE crystal oscillator (HSE ON) | |
| __STATIC_INLINE void | LL_RCC_HSE_Disable (void) |
| Disable HSE crystal oscillator (HSE ON) | |
| __STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void) |
| Check if HSE oscillator Ready. | |
| __STATIC_INLINE void | LL_RCC_HSI_Enable (void) |
| Enable HSI oscillator. | |
| __STATIC_INLINE void | LL_RCC_HSI_Disable (void) |
| Disable HSI oscillator. | |
| __STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void) |
| Check if HSI clock is ready. | |
| __STATIC_INLINE uint32_t | LL_RCC_HSI_IsDividerReady (void) |
| Check if HSI new divider applied and ready. | |
| __STATIC_INLINE void | LL_RCC_HSI_SetDivider (uint32_t Divider) |
| Set HSI divider. | |
| __STATIC_INLINE uint32_t | LL_RCC_HSI_GetDivider (void) |
| Get HSI divider. | |
| __STATIC_INLINE void | LL_RCC_HSI_EnableStopMode (void) |
| Enable HSI oscillator in Stop mode. | |
| __STATIC_INLINE void | LL_RCC_HSI_DisableStopMode (void) |
| Disable HSI oscillator in Stop mode. | |
| __STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void) |
| Get HSI Calibration value. | |
| __STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value) |
| Set HSI Calibration trimming. | |
| __STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void) |
| Get HSI Calibration trimming. | |
| __STATIC_INLINE void | LL_RCC_CSI_Enable (void) |
| Enable CSI oscillator. | |
| __STATIC_INLINE void | LL_RCC_CSI_Disable (void) |
| Disable CSI oscillator. | |
| __STATIC_INLINE uint32_t | LL_RCC_CSI_IsReady (void) |
| Check if CSI clock is ready. | |
| __STATIC_INLINE void | LL_RCC_CSI_EnableStopMode (void) |
| Enable CSI oscillator in Stop mode. | |
| __STATIC_INLINE void | LL_RCC_CSI_DisableStopMode (void) |
| Disable CSI oscillator in Stop mode. | |
| __STATIC_INLINE uint32_t | LL_RCC_CSI_GetCalibration (void) |
| Get CSI Calibration value. | |
| __STATIC_INLINE void | LL_RCC_CSI_SetCalibTrimming (uint32_t Value) |
| Set CSI Calibration trimming. | |
| __STATIC_INLINE uint32_t | LL_RCC_CSI_GetCalibTrimming (void) |
| Get CSI Calibration trimming. | |
| __STATIC_INLINE void | LL_RCC_HSI48_Enable (void) |
| Enable HSI48 oscillator. | |
| __STATIC_INLINE void | LL_RCC_HSI48_Disable (void) |
| Disable HSI48 oscillator. | |
| __STATIC_INLINE uint32_t | LL_RCC_HSI48_IsReady (void) |
| Check if HSI48 clock is ready. | |
| __STATIC_INLINE uint32_t | LL_RCC_HSI48_GetCalibration (void) |
| Get HSI48 Calibration value. | |
| __STATIC_INLINE uint32_t | LL_RCC_D1CK_IsReady (void) |
| Check if D1 clock is ready. | |
| __STATIC_INLINE uint32_t | LL_RCC_D2CK_IsReady (void) |
| Check if D2 clock is ready. | |
| __STATIC_INLINE void | LL_RCC_WWDG1_EnableSystemReset (void) |
| Enable system wide reset for Window Watch Dog 1. | |
| __STATIC_INLINE uint32_t | LL_RCC_WWDG1_IsSystemReset (void) |
| Check if Window Watch Dog 1 reset is system wide. | |
| __STATIC_INLINE void | LL_RCC_LSE_EnableCSS (void) |
| Enable the Clock Security System on LSE. | |
| __STATIC_INLINE uint32_t | LL_RCC_LSE_IsFailureDetected (void) |
| Check if LSE failure is detected by Clock Security System. | |
| __STATIC_INLINE void | LL_RCC_LSE_Enable (void) |
| Enable Low Speed External (LSE) crystal. | |
| __STATIC_INLINE void | LL_RCC_LSE_Disable (void) |
| Disable Low Speed External (LSE) crystal. | |
| __STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void) |
| Enable external clock source (LSE bypass). | |
| __STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void) |
| Disable external clock source (LSE bypass). | |
| __STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive) |
| Set LSE oscillator drive capability. | |
| __STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void) |
| Get LSE oscillator drive capability. | |
| __STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void) |
| Check if LSE oscillator Ready. | |
| __STATIC_INLINE void | LL_RCC_LSI_Enable (void) |
| Enable LSI Oscillator. | |
| __STATIC_INLINE void | LL_RCC_LSI_Disable (void) |
| Disable LSI Oscillator. | |
| __STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void) |
| Check if LSI is Ready. | |
| __STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source) |
| Configure the system clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void) |
| Get the system clock source. | |
| __STATIC_INLINE void | LL_RCC_SetSysWakeUpClkSource (uint32_t Source) |
| Configure the system wakeup clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetSysWakeUpClkSource (void) |
| Get the system wakeup clock source. | |
| __STATIC_INLINE void | LL_RCC_SetKerWakeUpClkSource (uint32_t Source) |
| Configure the kernel wakeup clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetKerWakeUpClkSource (void) |
| Get the kernel wakeup clock source. | |
| __STATIC_INLINE void | LL_RCC_SetSysPrescaler (uint32_t Prescaler) |
| Set System prescaler. | |
| __STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler) |
| Set AHB prescaler. | |
| __STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler) |
| Set APB1 prescaler. | |
| __STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler) |
| Set APB2 prescaler. | |
| __STATIC_INLINE void | LL_RCC_SetAPB3Prescaler (uint32_t Prescaler) |
| Set APB3 prescaler. | |
| __STATIC_INLINE void | LL_RCC_SetAPB4Prescaler (uint32_t Prescaler) |
| Set APB4 prescaler. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetSysPrescaler (void) |
| Get System prescaler. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void) |
| Get AHB prescaler. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void) |
| Get APB1 prescaler. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void) |
| Get APB2 prescaler. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetAPB3Prescaler (void) |
| Get APB3 prescaler. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetAPB4Prescaler (void) |
| Get APB4 prescaler. | |
| __STATIC_INLINE void | LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler) |
| Configure MCOx. | |
| __STATIC_INLINE void | LL_RCC_SetClockSource (uint32_t ClkSource) |
| Configure periph clock source. | |
| __STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t ClkSource) |
| Configure USARTx clock source. | |
| __STATIC_INLINE void | LL_RCC_SetLPUARTClockSource (uint32_t ClkSource) |
| Configure LPUARTx clock source. | |
| __STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t ClkSource) |
| Configure I2Cx clock source. | |
| __STATIC_INLINE void | LL_RCC_SetLPTIMClockSource (uint32_t ClkSource) |
| Configure LPTIMx clock source. | |
| __STATIC_INLINE void | LL_RCC_SetSAIClockSource (uint32_t ClkSource) |
| Configure SAIx clock source. | |
| __STATIC_INLINE void | LL_RCC_SetSDMMCClockSource (uint32_t ClkSource) |
| Configure SDMMCx clock source. | |
| __STATIC_INLINE void | LL_RCC_SetRNGClockSource (uint32_t ClkSource) |
| Configure RNGx clock source. | |
| __STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t ClkSource) |
| Configure USBx clock source. | |
| __STATIC_INLINE void | LL_RCC_SetCECClockSource (uint32_t ClkSource) |
| Configure CECx clock source. | |
| __STATIC_INLINE void | LL_RCC_SetDFSDMClockSource (uint32_t ClkSource) |
| Configure DFSDMx Kernel clock source. | |
| __STATIC_INLINE void | LL_RCC_SetFMCClockSource (uint32_t ClkSource) |
| Configure FMCx Kernel clock source. | |
| __STATIC_INLINE void | LL_RCC_SetOSPIClockSource (uint32_t ClkSource) |
| Configure OSPIx Kernel clock source. | |
| __STATIC_INLINE void | LL_RCC_SetCLKPClockSource (uint32_t ClkSource) |
| Configure CLKP Kernel clock source. | |
| __STATIC_INLINE void | LL_RCC_SetSPIClockSource (uint32_t ClkSource) |
| Configure SPIx Kernel clock source. | |
| __STATIC_INLINE void | LL_RCC_SetSPDIFClockSource (uint32_t ClkSource) |
| Configure SPDIFx Kernel clock source. | |
| __STATIC_INLINE void | LL_RCC_SetFDCANClockSource (uint32_t ClkSource) |
| Configure FDCANx Kernel clock source. | |
| __STATIC_INLINE void | LL_RCC_SetSWPClockSource (uint32_t ClkSource) |
| Configure SWPx Kernel clock source. | |
| __STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ClkSource) |
| Configure ADCx Kernel clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetClockSource (uint32_t Periph) |
| Get periph clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t Periph) |
| Get USARTx clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetLPUARTClockSource (uint32_t Periph) |
| Get LPUART clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t Periph) |
| Get I2Cx clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetLPTIMClockSource (uint32_t Periph) |
| Get LPTIM clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetSAIClockSource (uint32_t Periph) |
| Get SAIx clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetSDMMCClockSource (uint32_t Periph) |
| Get SDMMC clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetRNGClockSource (uint32_t Periph) |
| Get RNG clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t Periph) |
| Get USB clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetCECClockSource (uint32_t Periph) |
| Get CEC clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetDFSDMClockSource (uint32_t Periph) |
| Get DFSDM Kernel clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetFMCClockSource (uint32_t Periph) |
| Get FMC Kernel clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetOSPIClockSource (uint32_t Periph) |
| Get OSPI Kernel clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetCLKPClockSource (uint32_t Periph) |
| Get CLKP Kernel clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetSPIClockSource (uint32_t Periph) |
| Get SPIx Kernel clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetSPDIFClockSource (uint32_t Periph) |
| Get SPDIF Kernel clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetFDCANClockSource (uint32_t Periph) |
| Get FDCAN Kernel clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetSWPClockSource (uint32_t Periph) |
| Get SWP Kernel clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t Periph) |
| Get ADC Kernel clock source. | |
| __STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source) |
| Set RTC Clock Source. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void) |
| Get RTC Clock Source. | |
| __STATIC_INLINE void | LL_RCC_EnableRTC (void) |
| Enable RTC. | |
| __STATIC_INLINE void | LL_RCC_DisableRTC (void) |
| Disable RTC. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void) |
| Check if RTC has been enabled or not. | |
| __STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void) |
| Force the Backup domain reset. | |
| __STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void) |
| Release the Backup domain reset. | |
| __STATIC_INLINE void | LL_RCC_SetRTC_HSEPrescaler (uint32_t Prescaler) |
| Set HSE Prescalers for RTC Clock. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetRTC_HSEPrescaler (void) |
| Get HSE Prescalers for RTC Clock. | |
| __STATIC_INLINE void | LL_RCC_SetTIMPrescaler (uint32_t Prescaler) |
| Set Timers Clock Prescalers. | |
| __STATIC_INLINE uint32_t | LL_RCC_GetTIMPrescaler (void) |
| Get Timers Clock Prescalers. | |
| __STATIC_INLINE void | LL_RCC_PLL_SetSource (uint32_t PLLSource) |
| Set the oscillator used as PLL clock source. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL_GetSource (void) |
| Get the oscillator used as PLL clock source. | |
| __STATIC_INLINE void | LL_RCC_PLL1_Enable (void) |
| Enable PLL1. | |
| __STATIC_INLINE void | LL_RCC_PLL1_Disable (void) |
| Disable PLL1. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL1_IsReady (void) |
| Check if PLL1 Ready. | |
| __STATIC_INLINE void | LL_RCC_PLL1P_Enable (void) |
| Enable PLL1P. | |
| __STATIC_INLINE void | LL_RCC_PLL1Q_Enable (void) |
| Enable PLL1Q. | |
| __STATIC_INLINE void | LL_RCC_PLL1R_Enable (void) |
| Enable PLL1R. | |
| __STATIC_INLINE void | LL_RCC_PLL1FRACN_Enable (void) |
| Enable PLL1 FRACN. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL1P_IsEnabled (void) |
| Check if PLL1 P is enabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL1Q_IsEnabled (void) |
| Check if PLL1 Q is enabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL1R_IsEnabled (void) |
| Check if PLL1 R is enabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL1FRACN_IsEnabled (void) |
| Check if PLL1 FRACN is enabled. | |
| __STATIC_INLINE void | LL_RCC_PLL1P_Disable (void) |
| Disable PLL1P. | |
| __STATIC_INLINE void | LL_RCC_PLL1Q_Disable (void) |
| Disable PLL1Q. | |
| __STATIC_INLINE void | LL_RCC_PLL1R_Disable (void) |
| Disable PLL1R. | |
| __STATIC_INLINE void | LL_RCC_PLL1FRACN_Disable (void) |
| Disable PLL1 FRACN. | |
| __STATIC_INLINE void | LL_RCC_PLL1_SetVCOOutputRange (uint32_t VCORange) |
| Set PLL1 VCO OutputRange. | |
| __STATIC_INLINE void | LL_RCC_PLL1_SetVCOInputRange (uint32_t InputRange) |
| Set PLL1 VCO Input Range. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL1_GetN (void) |
| Get PLL1 N Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL1_GetM (void) |
| Get PLL1 M Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL1_GetP (void) |
| Get PLL1 P Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL1_GetQ (void) |
| Get PLL1 Q Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL1_GetR (void) |
| Get PLL1 R Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL1_GetFRACN (void) |
| Get PLL1 FRACN Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL1_SetN (uint32_t N) |
| Set PLL1 N Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL1_SetM (uint32_t M) |
| Set PLL1 M Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL1_SetP (uint32_t P) |
| Set PLL1 P Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL1_SetQ (uint32_t Q) |
| Set PLL1 Q Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL1_SetR (uint32_t R) |
| Set PLL1 R Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL1_SetFRACN (uint32_t FRACN) |
| Set PLL1 FRACN Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL2_Enable (void) |
| Enable PLL2. | |
| __STATIC_INLINE void | LL_RCC_PLL2_Disable (void) |
| Disable PLL2. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL2_IsReady (void) |
| Check if PLL2 Ready. | |
| __STATIC_INLINE void | LL_RCC_PLL2P_Enable (void) |
| Enable PLL2P. | |
| __STATIC_INLINE void | LL_RCC_PLL2Q_Enable (void) |
| Enable PLL2Q. | |
| __STATIC_INLINE void | LL_RCC_PLL2R_Enable (void) |
| Enable PLL2R. | |
| __STATIC_INLINE void | LL_RCC_PLL2FRACN_Enable (void) |
| Enable PLL2 FRACN. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL2P_IsEnabled (void) |
| Check if PLL2 P is enabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL2Q_IsEnabled (void) |
| Check if PLL2 Q is enabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL2R_IsEnabled (void) |
| Check if PLL2 R is enabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL2FRACN_IsEnabled (void) |
| Check if PLL2 FRACN is enabled. | |
| __STATIC_INLINE void | LL_RCC_PLL2P_Disable (void) |
| Disable PLL2P. | |
| __STATIC_INLINE void | LL_RCC_PLL2Q_Disable (void) |
| Disable PLL2Q. | |
| __STATIC_INLINE void | LL_RCC_PLL2R_Disable (void) |
| Disable PLL2R. | |
| __STATIC_INLINE void | LL_RCC_PLL2FRACN_Disable (void) |
| Disable PLL2 FRACN. | |
| __STATIC_INLINE void | LL_RCC_PLL2_SetVCOOutputRange (uint32_t VCORange) |
| Set PLL2 VCO OutputRange. | |
| __STATIC_INLINE void | LL_RCC_PLL2_SetVCOInputRange (uint32_t InputRange) |
| Set PLL2 VCO Input Range. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL2_GetN (void) |
| Get PLL2 N Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL2_GetM (void) |
| Get PLL2 M Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL2_GetP (void) |
| Get PLL2 P Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL2_GetQ (void) |
| Get PLL2 Q Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL2_GetR (void) |
| Get PLL2 R Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL2_GetFRACN (void) |
| Get PLL2 FRACN Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL2_SetN (uint32_t N) |
| Set PLL2 N Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL2_SetM (uint32_t M) |
| Set PLL2 M Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL2_SetP (uint32_t P) |
| Set PLL2 P Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL2_SetQ (uint32_t Q) |
| Set PLL2 Q Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL2_SetR (uint32_t R) |
| Set PLL2 R Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL2_SetFRACN (uint32_t FRACN) |
| Set PLL2 FRACN Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL3_Enable (void) |
| Enable PLL3. | |
| __STATIC_INLINE void | LL_RCC_PLL3_Disable (void) |
| Disable PLL3. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL3_IsReady (void) |
| Check if PLL3 Ready. | |
| __STATIC_INLINE void | LL_RCC_PLL3P_Enable (void) |
| Enable PLL3P. | |
| __STATIC_INLINE void | LL_RCC_PLL3Q_Enable (void) |
| Enable PLL3Q. | |
| __STATIC_INLINE void | LL_RCC_PLL3R_Enable (void) |
| Enable PLL3R. | |
| __STATIC_INLINE void | LL_RCC_PLL3FRACN_Enable (void) |
| Enable PLL3 FRACN. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL3P_IsEnabled (void) |
| Check if PLL3 P is enabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL3Q_IsEnabled (void) |
| Check if PLL3 Q is enabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL3R_IsEnabled (void) |
| Check if PLL3 R is enabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL3FRACN_IsEnabled (void) |
| Check if PLL3 FRACN is enabled. | |
| __STATIC_INLINE void | LL_RCC_PLL3P_Disable (void) |
| Disable PLL3P. | |
| __STATIC_INLINE void | LL_RCC_PLL3Q_Disable (void) |
| Disable PLL3Q. | |
| __STATIC_INLINE void | LL_RCC_PLL3R_Disable (void) |
| Disable PLL3R. | |
| __STATIC_INLINE void | LL_RCC_PLL3FRACN_Disable (void) |
| Disable PLL3 FRACN. | |
| __STATIC_INLINE void | LL_RCC_PLL3_SetVCOOutputRange (uint32_t VCORange) |
| Set PLL3 VCO OutputRange. | |
| __STATIC_INLINE void | LL_RCC_PLL3_SetVCOInputRange (uint32_t InputRange) |
| Set PLL3 VCO Input Range. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL3_GetN (void) |
| Get PLL3 N Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL3_GetM (void) |
| Get PLL3 M Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL3_GetP (void) |
| Get PLL3 P Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL3_GetQ (void) |
| Get PLL3 Q Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL3_GetR (void) |
| Get PLL3 R Coefficient. | |
| __STATIC_INLINE uint32_t | LL_RCC_PLL3_GetFRACN (void) |
| Get PLL3 FRACN Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL3_SetN (uint32_t N) |
| Set PLL3 N Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL3_SetM (uint32_t M) |
| Set PLL3 M Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL3_SetP (uint32_t P) |
| Set PLL3 P Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL3_SetQ (uint32_t Q) |
| Set PLL3 Q Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL3_SetR (uint32_t R) |
| Set PLL3 R Coefficient. | |
| __STATIC_INLINE void | LL_RCC_PLL3_SetFRACN (uint32_t FRACN) |
| Set PLL3 FRACN Coefficient. | |
| __STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void) |
| Clear LSI ready interrupt flag. | |
| __STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void) |
| Clear LSE ready interrupt flag. | |
| __STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void) |
| Clear HSI ready interrupt flag. | |
| __STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void) |
| Clear HSE ready interrupt flag. | |
| __STATIC_INLINE void | LL_RCC_ClearFlag_CSIRDY (void) |
| Clear CSI ready interrupt flag. | |
| __STATIC_INLINE void | LL_RCC_ClearFlag_HSI48RDY (void) |
| Clear HSI48 ready interrupt flag. | |
| __STATIC_INLINE void | LL_RCC_ClearFlag_PLL1RDY (void) |
| Clear PLL1 ready interrupt flag. | |
| __STATIC_INLINE void | LL_RCC_ClearFlag_PLL2RDY (void) |
| Clear PLL2 ready interrupt flag. | |
| __STATIC_INLINE void | LL_RCC_ClearFlag_PLL3RDY (void) |
| Clear PLL3 ready interrupt flag. | |
| __STATIC_INLINE void | LL_RCC_ClearFlag_LSECSS (void) |
| Clear LSE Clock security system interrupt flag. | |
| __STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void) |
| Clear HSE Clock security system interrupt flag. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void) |
| Check if LSI ready interrupt occurred or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void) |
| Check if LSE ready interrupt occurred or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void) |
| Check if HSI ready interrupt occurred or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void) |
| Check if HSE ready interrupt occurred or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_CSIRDY (void) |
| Check if CSI ready interrupt occurred or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSI48RDY (void) |
| Check if HSI48 ready interrupt occurred or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLL1RDY (void) |
| Check if PLL1 ready interrupt occurred or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLL2RDY (void) |
| Check if PLL2 ready interrupt occurred or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLL3RDY (void) |
| Check if PLL3 ready interrupt occurred or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSECSS (void) |
| Check if LSE Clock security system interrupt occurred or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void) |
| Check if HSE Clock security system interrupt occurred or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void) |
| Check if RCC flag Low Power D1 reset is set or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDG1RST (void) |
| Check if RCC flag Window Watchdog 1 reset is set or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDG1RST (void) |
| Check if RCC flag Independent Watchdog 1 reset is set or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void) |
| Check if RCC flag Software reset is set or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PORRST (void) |
| Check if RCC flag POR/PDR reset is set or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void) |
| Check if RCC flag Pin reset is set or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_BORRST (void) |
| Check if RCC flag BOR reset is set or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_D1RST (void) |
| Check if RCC flag D1 reset is set or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_D2RST (void) |
| Check if RCC flag D2 reset is set or not. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_CPURST (void) |
| Check if RCC flag CPU reset is set or not. | |
| __STATIC_INLINE void | LL_RCC_ClearResetFlags (void) |
| Set RMVF bit to clear all reset flags. | |
| __STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void) |
| Enable LSI ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void) |
| Enable LSE ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void) |
| Enable HSI ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void) |
| Enable HSE ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_EnableIT_CSIRDY (void) |
| Enable CSI ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_EnableIT_HSI48RDY (void) |
| Enable HSI48 ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_EnableIT_PLL1RDY (void) |
| Enable PLL1 ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_EnableIT_PLL2RDY (void) |
| Enable PLL2 ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_EnableIT_PLL3RDY (void) |
| Enable PLL3 ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_EnableIT_LSECSS (void) |
| Enable LSECSS interrupt. | |
| __STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void) |
| Disable LSI ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void) |
| Disable LSE ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void) |
| Disable HSI ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void) |
| Disable HSE ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_DisableIT_CSIRDY (void) |
| Disable CSI ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_DisableIT_HSI48RDY (void) |
| Disable HSI48 ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_DisableIT_PLL1RDY (void) |
| Disable PLL1 ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_DisableIT_PLL2RDY (void) |
| Disable PLL2 ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_DisableIT_PLL3RDY (void) |
| Disable PLL3 ready interrupt. | |
| __STATIC_INLINE void | LL_RCC_DisableIT_LSECSS (void) |
| Disable LSECSS interrupt. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_LSIRDY (void) |
| Checks if LSI ready interrupt source is enabled or disabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_LSERDY (void) |
| Checks if LSE ready interrupt source is enabled or disabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_HSIRDY (void) |
| Checks if HSI ready interrupt source is enabled or disabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_HSERDY (void) |
| Checks if HSE ready interrupt source is enabled or disabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_CSIRDY (void) |
| Checks if CSI ready interrupt source is enabled or disabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_HSI48RDY (void) |
| Checks if HSI48 ready interrupt source is enabled or disabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_PLL1RDY (void) |
| Checks if PLL1 ready interrupt source is enabled or disabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_PLL2RDY (void) |
| Checks if PLL2 ready interrupt source is enabled or disabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_PLL3RDY (void) |
| Checks if PLL3 ready interrupt source is enabled or disabled. | |
| __STATIC_INLINE uint32_t | LL_RCC_IsEnableIT_LSECSS (void) |
| Checks if LSECSS interrupt source is enabled or disabled. | |
| void | LL_RCC_DeInit (void) |
| Resets the RCC clock configuration to the default reset state. | |
| uint32_t | LL_RCC_CalcPLLClockFreq (uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR) |
| Helper function to calculate the PLL frequency output. | |
| void | LL_RCC_GetPLL1ClockFreq (LL_PLL_ClocksTypeDef *PLL_Clocks) |
| Return PLL1 clocks frequencies. | |
| void | LL_RCC_GetPLL2ClockFreq (LL_PLL_ClocksTypeDef *PLL_Clocks) |
| Return PLL2 clocks frequencies. | |
| void | LL_RCC_GetPLL3ClockFreq (LL_PLL_ClocksTypeDef *PLL_Clocks) |
| Return PLL3 clocks frequencies. | |
| void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks) |
| Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks. | |
| uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource) |
| Return USARTx clock frequency. | |
| uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource) |
| Return LPUART clock frequency. | |
| uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource) |
| Return I2Cx clock frequency. | |
| uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource) |
| Return LPTIMx clock frequency. | |
| uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource) |
| Return SAIx clock frequency. | |
| uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource) |
| Return ADC clock frequency. | |
| uint32_t | LL_RCC_GetSDMMCClockFreq (uint32_t SDMMCxSource) |
| Return SDMMC clock frequency. | |
| uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource) |
| Return RNG clock frequency. | |
| uint32_t | LL_RCC_GetCECClockFreq (uint32_t CECxSource) |
| Return CEC clock frequency. | |
| uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource) |
| Return USB clock frequency. | |
| uint32_t | LL_RCC_GetDFSDMClockFreq (uint32_t DFSDMxSource) |
| Return DFSDM clock frequency. | |
| uint32_t | LL_RCC_GetSPDIFClockFreq (uint32_t SPDIFxSource) |
| Return SPDIF clock frequency. | |
| uint32_t | LL_RCC_GetSPIClockFreq (uint32_t SPIxSource) |
| Return SPIx clock frequency. | |
| uint32_t | LL_RCC_GetSWPClockFreq (uint32_t SWPxSource) |
| Return SWP clock frequency. | |
| uint32_t | LL_RCC_GetFDCANClockFreq (uint32_t FDCANxSource) |
| Return FDCAN clock frequency. | |
| uint32_t | LL_RCC_GetFMCClockFreq (uint32_t FMCxSource) |
| Return FMC clock frequency. | |
| uint32_t | LL_RCC_GetOSPIClockFreq (uint32_t OSPIxSource) |
| Return OSPI clock frequency. | |
| uint32_t | LL_RCC_GetCLKPClockFreq (uint32_t CLKPxSource) |
| Return CLKP clock frequency. | |
Variables | |
| const uint8_t | LL_RCC_PrescTable [16] |
Header file of RCC LL module.
Copyright (c) 2017 STMicroelectronics. All rights reserved.
This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.
Definition in file stm32h7xx_ll_rcc.h.
1.7.6.1