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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_rcc.h 00004 * @author MCD Application Team 00005 * @version $VERSION$ 00006 * @date $DATE$ 00007 * @brief Header file of RCC LL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * Copyright (c) 2017 STMicroelectronics. 00012 * All rights reserved. 00013 * 00014 * This software is licensed under terms that can be found in the LICENSE file in 00015 * the root directory of this software component. 00016 * If no LICENSE file comes with this software, it is provided AS-IS. 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32H7xx_LL_RCC_H 00022 #define STM32H7xx_LL_RCC_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32h7xx.h" 00030 #include <math.h> 00031 00032 /** @addtogroup STM32H7xx_LL_Driver 00033 * @{ 00034 */ 00035 00036 #if defined(RCC) 00037 00038 /** @defgroup RCC_LL RCC 00039 * @{ 00040 */ 00041 00042 /* Private types -------------------------------------------------------------*/ 00043 /* Private variables ---------------------------------------------------------*/ 00044 /** @defgroup RCC_LL_Private_Variables RCC Private Variables 00045 * @{ 00046 */ 00047 extern const uint8_t LL_RCC_PrescTable[16]; 00048 00049 /** 00050 * @} 00051 */ 00052 /* Private constants ---------------------------------------------------------*/ 00053 /* Private macros ------------------------------------------------------------*/ 00054 #if !defined(UNUSED) 00055 #define UNUSED(x) ((void)(x)) 00056 #endif 00057 00058 /* 32 24 16 8 0 00059 -------------------------------------------------------- 00060 | Mask | ClkSource | Bit | Register | 00061 | | Config | Position | Offset | 00062 --------------------------------------------------------*/ 00063 00064 #if defined(RCC_VER_2_0) 00065 /* Clock source register offset Vs CDCCIPR register */ 00066 #define CDCCIP 0x0UL 00067 #define CDCCIP1 0x4UL 00068 #define CDCCIP2 0x8UL 00069 #define SRDCCIP 0xCUL 00070 #else 00071 /* Clock source register offset Vs D1CCIPR register */ 00072 #define D1CCIP 0x0UL 00073 #define D2CCIP1 0x4UL 00074 #define D2CCIP2 0x8UL 00075 #define D3CCIP 0xCUL 00076 #endif /* RCC_VER_2_0 */ 00077 00078 #define LL_RCC_REG_SHIFT 0U 00079 #define LL_RCC_POS_SHIFT 8U 00080 #define LL_RCC_CONFIG_SHIFT 16U 00081 #define LL_RCC_MASK_SHIFT 24U 00082 00083 #define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL) 00084 00085 #define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) 00086 00087 #define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) 00088 00089 #define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL) 00090 00091 #define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \ 00092 (( __POS__ ) << LL_RCC_POS_SHIFT) | \ 00093 (( __REG__ ) << LL_RCC_REG_SHIFT) | \ 00094 (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT))) 00095 00096 #if defined(USE_FULL_LL_DRIVER) 00097 /** @defgroup RCC_LL_Private_Macros RCC Private Macros 00098 * @{ 00099 */ 00100 /** 00101 * @} 00102 */ 00103 #endif /*USE_FULL_LL_DRIVER*/ 00104 /* Exported types ------------------------------------------------------------*/ 00105 #if defined(USE_FULL_LL_DRIVER) 00106 /** @defgroup RCC_LL_Exported_Types RCC Exported Types 00107 * @{ 00108 */ 00109 00110 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure 00111 * @{ 00112 */ 00113 00114 /** 00115 * @brief RCC Clocks Frequency Structure 00116 */ 00117 typedef struct 00118 { 00119 uint32_t SYSCLK_Frequency; 00120 uint32_t CPUCLK_Frequency; 00121 uint32_t HCLK_Frequency; 00122 uint32_t PCLK1_Frequency; 00123 uint32_t PCLK2_Frequency; 00124 uint32_t PCLK3_Frequency; 00125 uint32_t PCLK4_Frequency; 00126 } LL_RCC_ClocksTypeDef; 00127 00128 /** 00129 * @} 00130 */ 00131 00132 /** 00133 * @brief PLL Clocks Frequency Structure 00134 */ 00135 typedef struct 00136 { 00137 uint32_t PLL_P_Frequency; 00138 uint32_t PLL_Q_Frequency; 00139 uint32_t PLL_R_Frequency; 00140 } LL_PLL_ClocksTypeDef; 00141 00142 /** 00143 * @} 00144 */ 00145 00146 #endif /* USE_FULL_LL_DRIVER */ 00147 00148 /* Exported constants --------------------------------------------------------*/ 00149 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants 00150 * @{ 00151 */ 00152 00153 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation 00154 * @brief Defines used to adapt values of different oscillators 00155 * @note These values could be modified in the user environment according to 00156 * HW set-up. 00157 * @{ 00158 */ 00159 #if !defined (HSE_VALUE) 00160 #if defined(RCC_VER_X) || defined(RCC_VER_3_0) 00161 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ 00162 #else 00163 #define HSE_VALUE 24000000U /*!< Value of the HSE oscillator in Hz */ 00164 #endif /* RCC_VER_X || RCC_VER_3_0 */ 00165 #endif /* HSE_VALUE */ 00166 00167 #if !defined (HSI_VALUE) 00168 #define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */ 00169 #endif /* HSI_VALUE */ 00170 00171 #if !defined (CSI_VALUE) 00172 #define CSI_VALUE 4000000U /*!< Value of the CSI oscillator in Hz */ 00173 #endif /* CSI_VALUE */ 00174 00175 #if !defined (LSE_VALUE) 00176 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ 00177 #endif /* LSE_VALUE */ 00178 00179 #if !defined (LSI_VALUE) 00180 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ 00181 #endif /* LSI_VALUE */ 00182 00183 #if !defined (EXTERNAL_CLOCK_VALUE) 00184 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ 00185 #endif /* EXTERNAL_CLOCK_VALUE */ 00186 00187 #if !defined (HSI48_VALUE) 00188 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ 00189 #endif /* HSI48_VALUE */ 00190 00191 /** 00192 * @} 00193 */ 00194 00195 /** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider 00196 * @{ 00197 */ 00198 #define LL_RCC_HSI_DIV1 RCC_CR_HSIDIV_1 00199 #define LL_RCC_HSI_DIV2 RCC_CR_HSIDIV_2 00200 #define LL_RCC_HSI_DIV4 RCC_CR_HSIDIV_4 00201 #define LL_RCC_HSI_DIV8 RCC_CR_HSIDIV_8 00202 /** 00203 * @} 00204 */ 00205 00206 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability 00207 * @{ 00208 */ 00209 #define LL_RCC_LSEDRIVE_LOW (uint32_t)(0x00000000U) 00210 #define LL_RCC_LSEDRIVE_MEDIUMLOW (uint32_t)(RCC_BDCR_LSEDRV_0) 00211 #define LL_RCC_LSEDRIVE_MEDIUMHIGH (uint32_t)(RCC_BDCR_LSEDRV_1) 00212 #define LL_RCC_LSEDRIVE_HIGH (uint32_t)(RCC_BDCR_LSEDRV) 00213 /** 00214 * @} 00215 */ 00216 00217 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch 00218 * @{ 00219 */ 00220 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI 00221 #define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_CSI 00222 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE 00223 #define LL_RCC_SYS_CLKSOURCE_PLL1 RCC_CFGR_SW_PLL1 00224 /** 00225 * @} 00226 */ 00227 00228 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status 00229 * @{ 00230 */ 00231 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00232 #define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */ 00233 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00234 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */ 00235 /** 00236 * @} 00237 */ 00238 00239 /** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup clock source 00240 * @{ 00241 */ 00242 #define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U) 00243 #define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPWUCK) 00244 /** 00245 * @} 00246 */ 00247 00248 /** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup clock source 00249 * @{ 00250 */ 00251 #define LL_RCC_KERWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U) 00252 #define LL_RCC_KERWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPKERWUCK) 00253 /** 00254 * @} 00255 */ 00256 00257 /** @defgroup RCC_LL_EC_SYSCLK_DIV System prescaler 00258 * @{ 00259 */ 00260 #if defined(RCC_D1CFGR_D1CPRE_DIV1) 00261 #define LL_RCC_SYSCLK_DIV_1 RCC_D1CFGR_D1CPRE_DIV1 00262 #define LL_RCC_SYSCLK_DIV_2 RCC_D1CFGR_D1CPRE_DIV2 00263 #define LL_RCC_SYSCLK_DIV_4 RCC_D1CFGR_D1CPRE_DIV4 00264 #define LL_RCC_SYSCLK_DIV_8 RCC_D1CFGR_D1CPRE_DIV8 00265 #define LL_RCC_SYSCLK_DIV_16 RCC_D1CFGR_D1CPRE_DIV16 00266 #define LL_RCC_SYSCLK_DIV_64 RCC_D1CFGR_D1CPRE_DIV64 00267 #define LL_RCC_SYSCLK_DIV_128 RCC_D1CFGR_D1CPRE_DIV128 00268 #define LL_RCC_SYSCLK_DIV_256 RCC_D1CFGR_D1CPRE_DIV256 00269 #define LL_RCC_SYSCLK_DIV_512 RCC_D1CFGR_D1CPRE_DIV512 00270 #else 00271 #define LL_RCC_SYSCLK_DIV_1 RCC_CDCFGR1_CDCPRE_DIV1 00272 #define LL_RCC_SYSCLK_DIV_2 RCC_CDCFGR1_CDCPRE_DIV2 00273 #define LL_RCC_SYSCLK_DIV_4 RCC_CDCFGR1_CDCPRE_DIV4 00274 #define LL_RCC_SYSCLK_DIV_8 RCC_CDCFGR1_CDCPRE_DIV8 00275 #define LL_RCC_SYSCLK_DIV_16 RCC_CDCFGR1_CDCPRE_DIV16 00276 #define LL_RCC_SYSCLK_DIV_64 RCC_CDCFGR1_CDCPRE_DIV64 00277 #define LL_RCC_SYSCLK_DIV_128 RCC_CDCFGR1_CDCPRE_DIV128 00278 #define LL_RCC_SYSCLK_DIV_256 RCC_CDCFGR1_CDCPRE_DIV256 00279 #define LL_RCC_SYSCLK_DIV_512 RCC_CDCFGR1_CDCPRE_DIV512 00280 #endif /* RCC_D1CFGR_D1CPRE_DIV1 */ 00281 /** 00282 * @} 00283 */ 00284 00285 /** @defgroup RCC_LL_EC_AHB_DIV AHB prescaler 00286 * @{ 00287 */ 00288 #if defined(RCC_D1CFGR_HPRE_DIV1) 00289 #define LL_RCC_AHB_DIV_1 RCC_D1CFGR_HPRE_DIV1 00290 #define LL_RCC_AHB_DIV_2 RCC_D1CFGR_HPRE_DIV2 00291 #define LL_RCC_AHB_DIV_4 RCC_D1CFGR_HPRE_DIV4 00292 #define LL_RCC_AHB_DIV_8 RCC_D1CFGR_HPRE_DIV8 00293 #define LL_RCC_AHB_DIV_16 RCC_D1CFGR_HPRE_DIV16 00294 #define LL_RCC_AHB_DIV_64 RCC_D1CFGR_HPRE_DIV64 00295 #define LL_RCC_AHB_DIV_128 RCC_D1CFGR_HPRE_DIV128 00296 #define LL_RCC_AHB_DIV_256 RCC_D1CFGR_HPRE_DIV256 00297 #define LL_RCC_AHB_DIV_512 RCC_D1CFGR_HPRE_DIV512 00298 #else 00299 #define LL_RCC_AHB_DIV_1 RCC_CDCFGR1_HPRE_DIV1 00300 #define LL_RCC_AHB_DIV_2 RCC_CDCFGR1_HPRE_DIV2 00301 #define LL_RCC_AHB_DIV_4 RCC_CDCFGR1_HPRE_DIV4 00302 #define LL_RCC_AHB_DIV_8 RCC_CDCFGR1_HPRE_DIV8 00303 #define LL_RCC_AHB_DIV_16 RCC_CDCFGR1_HPRE_DIV16 00304 #define LL_RCC_AHB_DIV_64 RCC_CDCFGR1_HPRE_DIV64 00305 #define LL_RCC_AHB_DIV_128 RCC_CDCFGR1_HPRE_DIV128 00306 #define LL_RCC_AHB_DIV_256 RCC_CDCFGR1_HPRE_DIV256 00307 #define LL_RCC_AHB_DIV_512 RCC_CDCFGR1_HPRE_DIV512 00308 #endif /* RCC_D1CFGR_HPRE_DIV1 */ 00309 /** 00310 * @} 00311 */ 00312 00313 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) 00314 * @{ 00315 */ 00316 #if defined(RCC_D2CFGR_D2PPRE1_DIV1) 00317 #define LL_RCC_APB1_DIV_1 RCC_D2CFGR_D2PPRE1_DIV1 00318 #define LL_RCC_APB1_DIV_2 RCC_D2CFGR_D2PPRE1_DIV2 00319 #define LL_RCC_APB1_DIV_4 RCC_D2CFGR_D2PPRE1_DIV4 00320 #define LL_RCC_APB1_DIV_8 RCC_D2CFGR_D2PPRE1_DIV8 00321 #define LL_RCC_APB1_DIV_16 RCC_D2CFGR_D2PPRE1_DIV16 00322 #else 00323 #define LL_RCC_APB1_DIV_1 RCC_CDCFGR2_CDPPRE1_DIV1 00324 #define LL_RCC_APB1_DIV_2 RCC_CDCFGR2_CDPPRE1_DIV2 00325 #define LL_RCC_APB1_DIV_4 RCC_CDCFGR2_CDPPRE1_DIV4 00326 #define LL_RCC_APB1_DIV_8 RCC_CDCFGR2_CDPPRE1_DIV8 00327 #define LL_RCC_APB1_DIV_16 RCC_CDCFGR2_CDPPRE1_DIV16 00328 #endif /* RCC_D2CFGR_D2PPRE1_DIV1 */ 00329 /** 00330 * @} 00331 */ 00332 00333 /** @defgroup RCC_LL_EC_APB2_DIV APB low-speed prescaler (APB2) 00334 * @{ 00335 */ 00336 #if defined(RCC_D2CFGR_D2PPRE2_DIV1) 00337 #define LL_RCC_APB2_DIV_1 RCC_D2CFGR_D2PPRE2_DIV1 00338 #define LL_RCC_APB2_DIV_2 RCC_D2CFGR_D2PPRE2_DIV2 00339 #define LL_RCC_APB2_DIV_4 RCC_D2CFGR_D2PPRE2_DIV4 00340 #define LL_RCC_APB2_DIV_8 RCC_D2CFGR_D2PPRE2_DIV8 00341 #define LL_RCC_APB2_DIV_16 RCC_D2CFGR_D2PPRE2_DIV16 00342 #else 00343 #define LL_RCC_APB2_DIV_1 RCC_CDCFGR2_CDPPRE2_DIV1 00344 #define LL_RCC_APB2_DIV_2 RCC_CDCFGR2_CDPPRE2_DIV2 00345 #define LL_RCC_APB2_DIV_4 RCC_CDCFGR2_CDPPRE2_DIV4 00346 #define LL_RCC_APB2_DIV_8 RCC_CDCFGR2_CDPPRE2_DIV8 00347 #define LL_RCC_APB2_DIV_16 RCC_CDCFGR2_CDPPRE2_DIV16 00348 #endif /* RCC_D2CFGR_D2PPRE2_DIV1 */ 00349 /** 00350 * @} 00351 */ 00352 00353 /** @defgroup RCC_LL_EC_APB3_DIV APB low-speed prescaler (APB3) 00354 * @{ 00355 */ 00356 #if defined(RCC_D1CFGR_D1PPRE_DIV1) 00357 #define LL_RCC_APB3_DIV_1 RCC_D1CFGR_D1PPRE_DIV1 00358 #define LL_RCC_APB3_DIV_2 RCC_D1CFGR_D1PPRE_DIV2 00359 #define LL_RCC_APB3_DIV_4 RCC_D1CFGR_D1PPRE_DIV4 00360 #define LL_RCC_APB3_DIV_8 RCC_D1CFGR_D1PPRE_DIV8 00361 #define LL_RCC_APB3_DIV_16 RCC_D1CFGR_D1PPRE_DIV16 00362 #else 00363 #define LL_RCC_APB3_DIV_1 RCC_CDCFGR1_CDPPRE_DIV1 00364 #define LL_RCC_APB3_DIV_2 RCC_CDCFGR1_CDPPRE_DIV2 00365 #define LL_RCC_APB3_DIV_4 RCC_CDCFGR1_CDPPRE_DIV4 00366 #define LL_RCC_APB3_DIV_8 RCC_CDCFGR1_CDPPRE_DIV8 00367 #define LL_RCC_APB3_DIV_16 RCC_CDCFGR1_CDPPRE_DIV16 00368 #endif /* RCC_D1CFGR_D1PPRE_DIV1 */ 00369 /** 00370 * @} 00371 */ 00372 00373 /** @defgroup RCC_LL_EC_APB4_DIV APB low-speed prescaler (APB4) 00374 * @{ 00375 */ 00376 #if defined(RCC_D3CFGR_D3PPRE_DIV1) 00377 #define LL_RCC_APB4_DIV_1 RCC_D3CFGR_D3PPRE_DIV1 00378 #define LL_RCC_APB4_DIV_2 RCC_D3CFGR_D3PPRE_DIV2 00379 #define LL_RCC_APB4_DIV_4 RCC_D3CFGR_D3PPRE_DIV4 00380 #define LL_RCC_APB4_DIV_8 RCC_D3CFGR_D3PPRE_DIV8 00381 #define LL_RCC_APB4_DIV_16 RCC_D3CFGR_D3PPRE_DIV16 00382 #else 00383 #define LL_RCC_APB4_DIV_1 RCC_SRDCFGR_SRDPPRE_DIV1 00384 #define LL_RCC_APB4_DIV_2 RCC_SRDCFGR_SRDPPRE_DIV2 00385 #define LL_RCC_APB4_DIV_4 RCC_SRDCFGR_SRDPPRE_DIV4 00386 #define LL_RCC_APB4_DIV_8 RCC_SRDCFGR_SRDPPRE_DIV8 00387 #define LL_RCC_APB4_DIV_16 RCC_SRDCFGR_SRDPPRE_DIV16 00388 #endif /* RCC_D3CFGR_D3PPRE_DIV1 */ 00389 /** 00390 * @} 00391 */ 00392 00393 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection 00394 * @{ 00395 */ 00396 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U) 00397 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0) 00398 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1) 00399 #define LL_RCC_MCO1SOURCE_PLL1QCLK (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) 00400 #define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2) 00401 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U) 00402 #define LL_RCC_MCO2SOURCE_PLL2PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0) 00403 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1) 00404 #define LL_RCC_MCO2SOURCE_PLL1PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) 00405 #define LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2) 00406 #define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0) 00407 /** 00408 * @} 00409 */ 00410 00411 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler 00412 * @{ 00413 */ 00414 #define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0) 00415 #define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1) 00416 #define LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1) 00417 #define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2) 00418 #define LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) 00419 #define LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) 00420 #define LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) 00421 #define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3) 00422 #define LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3) 00423 #define LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) 00424 #define LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) 00425 #define LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) 00426 #define LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) 00427 #define LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) 00428 #define LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE) 00429 #define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0) 00430 #define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1) 00431 #define LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1) 00432 #define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2) 00433 #define LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2) 00434 #define LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2) 00435 #define LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2) 00436 #define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3) 00437 #define LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3) 00438 #define LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3) 00439 #define LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3) 00440 #define LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) 00441 #define LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) 00442 #define LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) 00443 #define LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE) 00444 00445 /** 00446 * @} 00447 */ 00448 00449 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock 00450 * @{ 00451 */ 00452 #define LL_RCC_RTC_NOCLOCK (uint32_t)(0x00000000U) 00453 #define LL_RCC_RTC_HSE_DIV_2 (uint32_t)(RCC_CFGR_RTCPRE_1) 00454 #define LL_RCC_RTC_HSE_DIV_3 (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00455 #define LL_RCC_RTC_HSE_DIV_4 (uint32_t)(RCC_CFGR_RTCPRE_2) 00456 #define LL_RCC_RTC_HSE_DIV_5 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) 00457 #define LL_RCC_RTC_HSE_DIV_6 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) 00458 #define LL_RCC_RTC_HSE_DIV_7 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00459 #define LL_RCC_RTC_HSE_DIV_8 (uint32_t)(RCC_CFGR_RTCPRE_3) 00460 #define LL_RCC_RTC_HSE_DIV_9 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) 00461 #define LL_RCC_RTC_HSE_DIV_10 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) 00462 #define LL_RCC_RTC_HSE_DIV_11 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00463 #define LL_RCC_RTC_HSE_DIV_12 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) 00464 #define LL_RCC_RTC_HSE_DIV_13 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) 00465 #define LL_RCC_RTC_HSE_DIV_14 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) 00466 #define LL_RCC_RTC_HSE_DIV_15 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00467 #define LL_RCC_RTC_HSE_DIV_16 (uint32_t)(RCC_CFGR_RTCPRE_4) 00468 #define LL_RCC_RTC_HSE_DIV_17 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) 00469 #define LL_RCC_RTC_HSE_DIV_18 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) 00470 #define LL_RCC_RTC_HSE_DIV_19 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00471 #define LL_RCC_RTC_HSE_DIV_20 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) 00472 #define LL_RCC_RTC_HSE_DIV_21 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) 00473 #define LL_RCC_RTC_HSE_DIV_22 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) 00474 #define LL_RCC_RTC_HSE_DIV_23 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00475 #define LL_RCC_RTC_HSE_DIV_24 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) 00476 #define LL_RCC_RTC_HSE_DIV_25 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) 00477 #define LL_RCC_RTC_HSE_DIV_26 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) 00478 #define LL_RCC_RTC_HSE_DIV_27 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00479 #define LL_RCC_RTC_HSE_DIV_28 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) 00480 #define LL_RCC_RTC_HSE_DIV_29 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) 00481 #define LL_RCC_RTC_HSE_DIV_30 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) 00482 #define LL_RCC_RTC_HSE_DIV_31 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00483 #define LL_RCC_RTC_HSE_DIV_32 (uint32_t)(RCC_CFGR_RTCPRE_5) 00484 #define LL_RCC_RTC_HSE_DIV_33 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0) 00485 #define LL_RCC_RTC_HSE_DIV_34 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1) 00486 #define LL_RCC_RTC_HSE_DIV_35 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00487 #define LL_RCC_RTC_HSE_DIV_36 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2) 00488 #define LL_RCC_RTC_HSE_DIV_37 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) 00489 #define LL_RCC_RTC_HSE_DIV_38 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) 00490 #define LL_RCC_RTC_HSE_DIV_39 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00491 #define LL_RCC_RTC_HSE_DIV_40 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3) 00492 #define LL_RCC_RTC_HSE_DIV_41 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) 00493 #define LL_RCC_RTC_HSE_DIV_42 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) 00494 #define LL_RCC_RTC_HSE_DIV_43 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00495 #define LL_RCC_RTC_HSE_DIV_44 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) 00496 #define LL_RCC_RTC_HSE_DIV_45 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) 00497 #define LL_RCC_RTC_HSE_DIV_46 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) 00498 #define LL_RCC_RTC_HSE_DIV_47 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00499 #define LL_RCC_RTC_HSE_DIV_48 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4) 00500 #define LL_RCC_RTC_HSE_DIV_49 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) 00501 #define LL_RCC_RTC_HSE_DIV_50 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) 00502 #define LL_RCC_RTC_HSE_DIV_51 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00503 #define LL_RCC_RTC_HSE_DIV_52 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) 00504 #define LL_RCC_RTC_HSE_DIV_53 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) 00505 #define LL_RCC_RTC_HSE_DIV_54 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) 00506 #define LL_RCC_RTC_HSE_DIV_55 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00507 #define LL_RCC_RTC_HSE_DIV_56 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) 00508 #define LL_RCC_RTC_HSE_DIV_57 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) 00509 #define LL_RCC_RTC_HSE_DIV_58 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) 00510 #define LL_RCC_RTC_HSE_DIV_59 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00511 #define LL_RCC_RTC_HSE_DIV_60 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) 00512 #define LL_RCC_RTC_HSE_DIV_61 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) 00513 #define LL_RCC_RTC_HSE_DIV_62 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) 00514 #define LL_RCC_RTC_HSE_DIV_63 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) 00515 /** 00516 * @} 00517 */ 00518 00519 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection 00520 * @{ 00521 */ 00522 #if defined(RCC_D2CCIP2R_USART16SEL) 00523 #define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U) 00524 #define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0) 00525 #define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1) 00526 #define LL_RCC_USART16_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1) 00527 #define LL_RCC_USART16_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2) 00528 #define LL_RCC_USART16_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2) 00529 /* Aliases */ 00530 #define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_RCC_USART16_CLKSOURCE_PCLK2 00531 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_RCC_USART16_CLKSOURCE_PLL2Q 00532 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_RCC_USART16_CLKSOURCE_PLL3Q 00533 #define LL_RCC_USART16910_CLKSOURCE_HSI LL_RCC_USART16_CLKSOURCE_HSI 00534 #define LL_RCC_USART16910_CLKSOURCE_CSI LL_RCC_USART16_CLKSOURCE_CSI 00535 #define LL_RCC_USART16910_CLKSOURCE_LSE LL_RCC_USART16_CLKSOURCE_LSE 00536 00537 #elif defined(RCC_D2CCIP2R_USART16910SEL) 00538 #define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U) 00539 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0) 00540 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_1) 00541 #define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1) 00542 #define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_2) 00543 #define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2) 00544 /* Aliases */ 00545 #define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2 00546 #define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q 00547 #define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q 00548 #define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI 00549 #define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI 00550 #define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE 00551 00552 #else 00553 #define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U) 00554 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0) 00555 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1) 00556 #define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1) 00557 #define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2) 00558 #define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2) 00559 /* Aliases */ 00560 #define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2 00561 #define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q 00562 #define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q 00563 #define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI 00564 #define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI 00565 #define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE 00566 #endif /* RCC_D2CCIP2R_USART16SEL */ 00567 #if defined(RCC_D2CCIP2R_USART28SEL) 00568 #define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U) 00569 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0) 00570 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1) 00571 #define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1) 00572 #define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2) 00573 #define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2) 00574 #else 00575 #define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U) 00576 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0) 00577 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1) 00578 #define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1) 00579 #define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2) 00580 #define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2) 00581 #endif /* RCC_D2CCIP2R_USART28SEL */ 00582 /** 00583 * @} 00584 */ 00585 00586 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection 00587 * @{ 00588 */ 00589 #if defined(RCC_D3CCIPR_LPUART1SEL) 00590 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U) 00591 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_D3CCIPR_LPUART1SEL_0) 00592 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_D3CCIPR_LPUART1SEL_1) 00593 #define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1) 00594 #define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_D3CCIPR_LPUART1SEL_2) 00595 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2) 00596 #else 00597 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U) 00598 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_SRDCCIPR_LPUART1SEL_0) 00599 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_SRDCCIPR_LPUART1SEL_1) 00600 #define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1) 00601 #define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_SRDCCIPR_LPUART1SEL_2) 00602 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2) 00603 #endif /* RCC_D3CCIPR_LPUART1SEL */ 00604 /** 00605 * @} 00606 */ 00607 00608 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection 00609 * @{ 00610 */ 00611 #if defined (RCC_D2CCIP2R_I2C123SEL) 00612 #define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U) 00613 #define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0) 00614 #define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1) 00615 #define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1) 00616 /* Aliases */ 00617 #define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_RCC_I2C123_CLKSOURCE_PCLK1 00618 #define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_RCC_I2C123_CLKSOURCE_PLL3R 00619 #define LL_RCC_I2C1235_CLKSOURCE_HSI LL_RCC_I2C123_CLKSOURCE_HSI 00620 #define LL_RCC_I2C1235_CLKSOURCE_CSI LL_RCC_I2C123_CLKSOURCE_CSI 00621 00622 #elif defined (RCC_D2CCIP2R_I2C1235SEL) 00623 #define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U) 00624 #define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0) 00625 #define LL_RCC_I2C1235_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_1) 00626 #define LL_RCC_I2C1235_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1) 00627 /* Aliases */ 00628 #define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_RCC_I2C1235_CLKSOURCE_PCLK1 00629 #define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_RCC_I2C1235_CLKSOURCE_PLL3R 00630 #define LL_RCC_I2C123_CLKSOURCE_HSI LL_RCC_I2C1235_CLKSOURCE_HSI 00631 #define LL_RCC_I2C123_CLKSOURCE_CSI LL_RCC_I2C1235_CLKSOURCE_CSI 00632 00633 #else 00634 #define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U) 00635 #define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0) 00636 #define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1) 00637 #define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1) 00638 #endif /* RCC_D2CCIP2R_I2C123SEL */ 00639 #if defined (RCC_D3CCIPR_I2C4SEL) 00640 #define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U) 00641 #define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0) 00642 #define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_1) 00643 #define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1) 00644 #else 00645 #define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U) 00646 #define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0) 00647 #define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_1) 00648 #define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1) 00649 #endif /* RCC_D3CCIPR_I2C4SEL */ 00650 /** 00651 * @} 00652 */ 00653 00654 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection 00655 * @{ 00656 */ 00657 #if defined(RCC_D2CCIP2R_LPTIM1SEL) 00658 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U) 00659 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0) 00660 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_1) 00661 #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1) 00662 #define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_2) 00663 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2) 00664 #else 00665 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U) 00666 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0) 00667 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_1) 00668 #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1) 00669 #define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_2) 00670 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2) 00671 #endif /* RCC_D2CCIP2R_LPTIM1SEL */ 00672 #if defined(RCC_D3CCIPR_LPTIM2SEL) 00673 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U) 00674 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0) 00675 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_1) 00676 #define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1) 00677 #define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_2) 00678 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2) 00679 #else 00680 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U) 00681 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0) 00682 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_1) 00683 #define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1) 00684 #define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_2) 00685 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2) 00686 #endif /* RCC_D3CCIPR_LPTIM2SEL */ 00687 #if defined(RCC_D3CCIPR_LPTIM345SEL) 00688 #define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U) 00689 #define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0) 00690 #define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1) 00691 #define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1) 00692 #define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2) 00693 #define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2) 00694 #else 00695 #define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U) 00696 #define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0) 00697 #define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1) 00698 #define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1) 00699 #define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2) 00700 #define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2) 00701 /* aliases*/ 00702 #define LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_RCC_LPTIM345_CLKSOURCE_PCLK4 00703 #define LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_RCC_LPTIM345_CLKSOURCE_PLL2P 00704 #define LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_RCC_LPTIM345_CLKSOURCE_PLL3R 00705 #define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_RCC_LPTIM345_CLKSOURCE_LSE 00706 #define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_RCC_LPTIM345_CLKSOURCE_LSI 00707 #define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_RCC_LPTIM345_CLKSOURCE_CLKP 00708 #endif /* RCC_D3CCIPR_LPTIM345SEL */ 00709 /** 00710 * @} 00711 */ 00712 00713 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection 00714 * @{ 00715 */ 00716 #if defined(RCC_D2CCIP1R_SAI1SEL) 00717 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U) 00718 #define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0) 00719 #define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_1) 00720 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1) 00721 #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_2) 00722 #else 00723 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U) 00724 #define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0) 00725 #define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_1) 00726 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1) 00727 #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_2) 00728 #endif 00729 #if defined(SAI3) 00730 #define LL_RCC_SAI23_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U) 00731 #define LL_RCC_SAI23_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0) 00732 #define LL_RCC_SAI23_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1) 00733 #define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1) 00734 #define LL_RCC_SAI23_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2) 00735 #endif /* SAI3 */ 00736 #if defined(RCC_CDCCIP1R_SAI2ASEL) 00737 #define LL_RCC_SAI2A_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U) 00738 #define LL_RCC_SAI2A_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0) 00739 #define LL_RCC_SAI2A_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_1) 00740 #define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1) 00741 #define LL_RCC_SAI2A_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_2) 00742 #define LL_RCC_SAI2A_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2) 00743 #endif /* RCC_CDCCIP1R_SAI2ASEL */ 00744 #if defined(RCC_CDCCIP1R_SAI2BSEL) 00745 #define LL_RCC_SAI2B_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U) 00746 #define LL_RCC_SAI2B_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0) 00747 #define LL_RCC_SAI2B_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_1) 00748 #define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1) 00749 #define LL_RCC_SAI2B_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_2) 00750 #define LL_RCC_SAI2B_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2) 00751 #endif /* RCC_CDCCIP1R_SAI2BSEL */ 00752 #if defined(SAI4_Block_A) 00753 #define LL_RCC_SAI4A_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U) 00754 #define LL_RCC_SAI4A_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0) 00755 #define LL_RCC_SAI4A_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_1) 00756 #define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1) 00757 #define LL_RCC_SAI4A_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2) 00758 #if defined(RCC_VER_3_0) 00759 #define LL_RCC_SAI4A_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0) 00760 #endif /* RCC_VER_3_0 */ 00761 #endif /* SAI4_Block_A */ 00762 #if defined(SAI4_Block_B) 00763 #define LL_RCC_SAI4B_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U) 00764 #define LL_RCC_SAI4B_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0) 00765 #define LL_RCC_SAI4B_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_1) 00766 #define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1) 00767 #define LL_RCC_SAI4B_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2) 00768 #if defined(RCC_VER_3_0) 00769 #define LL_RCC_SAI4B_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0) 00770 #endif /* RCC_VER_3_0 */ 00771 #endif /* SAI4_Block_B */ 00772 /** 00773 * @} 00774 */ 00775 00776 /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection 00777 * @{ 00778 */ 00779 #if defined(RCC_D1CCIPR_SDMMCSEL) 00780 #define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U) 00781 #define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_SDMMCSEL) 00782 #else 00783 #define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U) 00784 #define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_SDMMCSEL) 00785 #endif /* RCC_D1CCIPR_SDMMCSEL */ 00786 /** 00787 * @} 00788 */ 00789 00790 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection 00791 * @{ 00792 */ 00793 #if defined(RCC_D2CCIP2R_RNGSEL) 00794 #define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U) 00795 #define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_RNGSEL_0) 00796 #define LL_RCC_RNG_CLKSOURCE_LSE (RCC_D2CCIP2R_RNGSEL_1) 00797 #define LL_RCC_RNG_CLKSOURCE_LSI (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0) 00798 #else 00799 #define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U) 00800 #define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_RNGSEL_0) 00801 #define LL_RCC_RNG_CLKSOURCE_LSE (RCC_CDCCIP2R_RNGSEL_1) 00802 #define LL_RCC_RNG_CLKSOURCE_LSI (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0) 00803 #endif /* RCC_D2CCIP2R_RNGSEL */ 00804 /** 00805 * @} 00806 */ 00807 00808 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection 00809 * @{ 00810 */ 00811 #if defined(RCC_D2CCIP2R_USBSEL) 00812 #define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U) 00813 #define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_USBSEL_0) 00814 #define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_D2CCIP2R_USBSEL_1) 00815 #define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0) 00816 #else 00817 #define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U) 00818 #define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_USBSEL_0) 00819 #define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_CDCCIP2R_USBSEL_1) 00820 #define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0) 00821 #endif /* RCC_D2CCIP2R_USBSEL */ 00822 /** 00823 * @} 00824 */ 00825 00826 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection 00827 * @{ 00828 */ 00829 #if defined(RCC_D2CCIP2R_CECSEL) 00830 #define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U) 00831 #define LL_RCC_CEC_CLKSOURCE_LSI (RCC_D2CCIP2R_CECSEL_0) 00832 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_D2CCIP2R_CECSEL_1) 00833 #else 00834 #define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U) 00835 #define LL_RCC_CEC_CLKSOURCE_LSI (RCC_CDCCIP2R_CECSEL_0) 00836 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_CDCCIP2R_CECSEL_1) 00837 #endif 00838 /** 00839 * @} 00840 */ 00841 00842 #if defined(DSI) 00843 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection 00844 * @{ 00845 */ 00846 #define LL_RCC_DSI_CLKSOURCE_PHY (0x00000000U) 00847 #define LL_RCC_DSI_CLKSOURCE_PLL2Q (RCC_D1CCIPR_DSISEL) 00848 /** 00849 * @} 00850 */ 00851 #endif /* DSI */ 00852 00853 /** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM clock source selection 00854 * @{ 00855 */ 00856 #if defined(RCC_D2CCIP1R_DFSDM1SEL) 00857 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U) 00858 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_D2CCIP1R_DFSDM1SEL) 00859 #else 00860 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U) 00861 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_CDCCIP1R_DFSDM1SEL) 00862 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 00863 /** 00864 * @} 00865 */ 00866 00867 #if defined(DFSDM2_BASE) 00868 /** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE Peripheral DFSDM2 clock source selection 00869 * @{ 00870 */ 00871 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK4 (0x00000000U) 00872 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (RCC_SRDCCIPR_DFSDM2SEL) 00873 /** 00874 * @} 00875 */ 00876 #endif /* DFSDM2_BASE */ 00877 00878 /** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection 00879 * @{ 00880 */ 00881 #if defined(RCC_D1CCIPR_FMCSEL) 00882 #define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U) 00883 #define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_D1CCIPR_FMCSEL_0) 00884 #define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_FMCSEL_1) 00885 #define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1) 00886 #else 00887 #define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U) 00888 #define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_CDCCIPR_FMCSEL_0) 00889 #define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_FMCSEL_1) 00890 #define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1) 00891 #endif /* RCC_D1CCIPR_FMCSEL */ 00892 /** 00893 * @} 00894 */ 00895 00896 #if defined(QUADSPI) 00897 /** @defgroup RCC_LL_EC_QSPI_CLKSOURCE Peripheral QSPI clock source selection 00898 * @{ 00899 */ 00900 #define LL_RCC_QSPI_CLKSOURCE_HCLK (0x00000000U) 00901 #define LL_RCC_QSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_QSPISEL_0) 00902 #define LL_RCC_QSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_QSPISEL_1) 00903 #define LL_RCC_QSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1) 00904 /** 00905 * @} 00906 */ 00907 #endif /* QUADSPI */ 00908 00909 00910 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00911 /** @defgroup RCC_LL_EC_OSPI_CLKSOURCE Peripheral OSPI clock source selection 00912 * @{ 00913 */ 00914 #if defined(RCC_D1CCIPR_OCTOSPISEL) 00915 #define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U) 00916 #define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_OCTOSPISEL_0) 00917 #define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_OCTOSPISEL_1) 00918 #define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_OCTOSPISEL_0 | RCC_D1CCIPR_OCTOSPISEL_1) 00919 #else 00920 #define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U) 00921 #define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_CDCCIPR_OCTOSPISEL_0) 00922 #define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_CDCCIPR_OCTOSPISEL_1) 00923 #define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1) 00924 #endif /* RCC_D1CCIPR_OCTOSPISEL */ 00925 /** 00926 * @} 00927 */ 00928 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ 00929 00930 00931 /** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection 00932 * @{ 00933 */ 00934 #if defined(RCC_D1CCIPR_CKPERSEL) 00935 #define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U) 00936 #define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_D1CCIPR_CKPERSEL_0) 00937 #define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_D1CCIPR_CKPERSEL_1) 00938 #else 00939 #define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U) 00940 #define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_CDCCIPR_CKPERSEL_0) 00941 #define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_CDCCIPR_CKPERSEL_1) 00942 #endif /* RCC_D1CCIPR_CKPERSEL */ 00943 /** 00944 * @} 00945 */ 00946 00947 /** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI clock source selection 00948 * @{ 00949 */ 00950 #if defined(RCC_D2CCIP1R_SPI123SEL) 00951 #define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U) 00952 #define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0) 00953 #define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1) 00954 #define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1) 00955 #define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2) 00956 #else 00957 #define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U) 00958 #define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0) 00959 #define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1) 00960 #define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1) 00961 #define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2) 00962 #endif /* RCC_D2CCIP1R_SPI123SEL */ 00963 #if defined(RCC_D2CCIP1R_SPI45SEL) 00964 #define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U) 00965 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0) 00966 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_1) 00967 #define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1) 00968 #define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_2) 00969 #define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2) 00970 #else 00971 #define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U) 00972 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0) 00973 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_1) 00974 #define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1) 00975 #define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_2) 00976 #define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2) 00977 #endif /* (RCC_D2CCIP1R_SPI45SEL */ 00978 #if defined(RCC_D3CCIPR_SPI6SEL) 00979 #define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U) 00980 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0) 00981 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_1) 00982 #define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1) 00983 #define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_2) 00984 #define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2) 00985 #else 00986 #define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U) 00987 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0) 00988 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1) 00989 #define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1) 00990 #define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_2) 00991 #define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2) 00992 #define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2) 00993 #endif /* RCC_D3CCIPR_SPI6SEL */ 00994 /** 00995 * @} 00996 */ 00997 00998 /** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE Peripheral SPDIF clock source selection 00999 * @{ 01000 */ 01001 #if defined(RCC_D2CCIP1R_SPDIFSEL) 01002 #define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U) 01003 #define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_D2CCIP1R_SPDIFSEL_0) 01004 #define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_D2CCIP1R_SPDIFSEL_1) 01005 #define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1) 01006 #else 01007 #define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U) 01008 #define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_CDCCIP1R_SPDIFSEL_0) 01009 #define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_CDCCIP1R_SPDIFSEL_1) 01010 #define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1) 01011 #endif /* RCC_D2CCIP1R_SPDIFSEL */ 01012 /** 01013 * @} 01014 */ 01015 01016 #if defined(FDCAN1) || defined(FDCAN2) 01017 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection 01018 * @{ 01019 */ 01020 #if defined(RCC_D2CCIP1R_FDCANSEL) 01021 #define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U) 01022 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_D2CCIP1R_FDCANSEL_0) 01023 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_D2CCIP1R_FDCANSEL_1) 01024 #else 01025 #define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U) 01026 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_CDCCIP1R_FDCANSEL_0) 01027 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_CDCCIP1R_FDCANSEL_1) 01028 #endif /* RCC_D2CCIP1R_FDCANSEL */ 01029 /** 01030 * @} 01031 */ 01032 #endif /*FDCAN1 || FDCAN2*/ 01033 01034 /** @defgroup RCC_LL_EC_SWP_CLKSOURCE Peripheral SWP clock source selection 01035 * @{ 01036 */ 01037 #if defined(RCC_D2CCIP1R_SWPSEL) 01038 #define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U) 01039 #define LL_RCC_SWP_CLKSOURCE_HSI (RCC_D2CCIP1R_SWPSEL) 01040 #else 01041 #define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U) 01042 #define LL_RCC_SWP_CLKSOURCE_HSI (RCC_CDCCIP1R_SWPSEL) 01043 #endif /* RCC_D2CCIP1R_SWPSEL */ 01044 /** 01045 * @} 01046 */ 01047 01048 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection 01049 * @{ 01050 */ 01051 #if defined(RCC_D3CCIPR_ADCSEL) 01052 #define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U) 01053 #define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_D3CCIPR_ADCSEL_0) 01054 #define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_D3CCIPR_ADCSEL_1) 01055 #else 01056 #define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U) 01057 #define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_SRDCCIPR_ADCSEL_0) 01058 #define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_SRDCCIPR_ADCSEL_1) 01059 #endif /* RCC_D3CCIPR_ADCSEL */ 01060 /** 01061 * @} 01062 */ 01063 01064 /** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source 01065 * @{ 01066 */ 01067 #if defined (RCC_D2CCIP2R_USART16SEL) 01068 #define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U) 01069 #elif defined (RCC_D2CCIP2R_USART16910SEL) 01070 #define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U) 01071 /* alias*/ 01072 #define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE 01073 #else 01074 #define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U) 01075 /* alias*/ 01076 #define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE 01077 #endif /* RCC_D2CCIP2R_USART16SEL */ 01078 #if defined (RCC_D2CCIP2R_USART28SEL) 01079 #define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U) 01080 #else 01081 #define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U) 01082 #endif /* RCC_D2CCIP2R_USART28SEL */ 01083 /** 01084 * @} 01085 */ 01086 01087 /** @defgroup RCC_LL_EC_LPUARTx Peripheral LPUART get clock source 01088 * @{ 01089 */ 01090 #if defined(RCC_D3CCIPR_LPUART1SEL) 01091 #define LL_RCC_LPUART1_CLKSOURCE RCC_D3CCIPR_LPUART1SEL 01092 #else 01093 #define LL_RCC_LPUART1_CLKSOURCE RCC_SRDCCIPR_LPUART1SEL 01094 #endif /* RCC_D3CCIPR_LPUART1SEL */ 01095 /** 01096 * @} 01097 */ 01098 01099 /** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source 01100 * @{ 01101 */ 01102 #if defined(RCC_D2CCIP2R_I2C123SEL) 01103 #define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U) 01104 /* alias */ 01105 #define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE 01106 #elif defined(RCC_D2CCIP2R_I2C1235SEL) 01107 #define LL_RCC_I2C1235_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U) 01108 /* alias */ 01109 #define LL_RCC_I2C123_CLKSOURCE LL_RCC_I2C1235_CLKSOURCE 01110 #else 01111 #define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U) 01112 /* alias */ 01113 #define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE 01114 #endif /* RCC_D2CCIP2R_I2C123SEL */ 01115 #if defined(RCC_D3CCIPR_I2C4SEL) 01116 #define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U) 01117 #else 01118 #define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U) 01119 #endif /* RCC_D3CCIPR_I2C4SEL */ 01120 /** 01121 * @} 01122 */ 01123 01124 /** @defgroup RCC_LL_EC_LPTIMx Peripheral LPTIM get clock source 01125 * @{ 01126 */ 01127 #if defined(RCC_D2CCIP2R_LPTIM1SEL) 01128 #define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U) 01129 #else 01130 #define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U) 01131 #endif /* RCC_D2CCIP2R_LPTIM1SEL) */ 01132 #if defined(RCC_D3CCIPR_LPTIM2SEL) 01133 #define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U) 01134 #else 01135 #define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U) 01136 #endif /* RCC_D3CCIPR_LPTIM2SEL */ 01137 #if defined(RCC_D3CCIPR_LPTIM345SEL) 01138 #define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U) 01139 #else 01140 #define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U) 01141 #define LL_RCC_LPTIM3_CLKSOURCE LL_RCC_LPTIM345_CLKSOURCE /* alias */ 01142 #endif /* RCC_D3CCIPR_LPTIM345SEL */ 01143 /** 01144 * @} 01145 */ 01146 01147 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source 01148 * @{ 01149 */ 01150 #if defined(RCC_D2CCIP1R_SAI1SEL) 01151 #define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U) 01152 #else 01153 #define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U) 01154 #endif /* RCC_D2CCIP1R_SAI1SEL */ 01155 #if defined(RCC_D2CCIP1R_SAI23SEL) 01156 #define LL_RCC_SAI23_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U) 01157 #endif /* RCC_D2CCIP1R_SAI23SEL */ 01158 #if defined(RCC_CDCCIP1R_SAI2ASEL) 01159 #define LL_RCC_SAI2A_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U) 01160 #endif /* RCC_CDCCIP1R_SAI2ASEL */ 01161 #if defined(RCC_CDCCIP1R_SAI2BSEL) 01162 #define LL_RCC_SAI2B_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U) 01163 #endif /* RCC_CDCCIP1R_SAI2BSEL */ 01164 #if defined(RCC_D3CCIPR_SAI4ASEL) 01165 #define LL_RCC_SAI4A_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U) 01166 #endif /* RCC_D3CCIPR_SAI4ASEL */ 01167 #if defined(RCC_D3CCIPR_SAI4BSEL) 01168 #define LL_RCC_SAI4B_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U) 01169 #endif /* RCC_D3CCIPR_SAI4BSEL */ 01170 /** 01171 * @} 01172 */ 01173 01174 /** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source 01175 * @{ 01176 */ 01177 #if defined(RCC_D1CCIPR_SDMMCSEL) 01178 #define LL_RCC_SDMMC_CLKSOURCE RCC_D1CCIPR_SDMMCSEL 01179 #else 01180 #define LL_RCC_SDMMC_CLKSOURCE RCC_CDCCIPR_SDMMCSEL 01181 #endif /* RCC_D1CCIPR_SDMMCSEL */ 01182 /** 01183 * @} 01184 */ 01185 01186 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source 01187 * @{ 01188 */ 01189 #if (RCC_D2CCIP2R_RNGSEL) 01190 #define LL_RCC_RNG_CLKSOURCE RCC_D2CCIP2R_RNGSEL 01191 #else 01192 #define LL_RCC_RNG_CLKSOURCE RCC_CDCCIP2R_RNGSEL 01193 #endif /* RCC_D2CCIP2R_RNGSEL */ 01194 /** 01195 * @} 01196 */ 01197 01198 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source 01199 * @{ 01200 */ 01201 #if (RCC_D2CCIP2R_USBSEL) 01202 #define LL_RCC_USB_CLKSOURCE RCC_D2CCIP2R_USBSEL 01203 #else 01204 #define LL_RCC_USB_CLKSOURCE RCC_CDCCIP2R_USBSEL 01205 #endif /* RCC_D2CCIP2R_USBSEL */ 01206 /** 01207 * @} 01208 */ 01209 01210 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source 01211 * @{ 01212 */ 01213 #if (RCC_D2CCIP2R_CECSEL) 01214 #define LL_RCC_CEC_CLKSOURCE RCC_D2CCIP2R_CECSEL 01215 #else 01216 #define LL_RCC_CEC_CLKSOURCE RCC_CDCCIP2R_CECSEL 01217 #endif /* RCC_D2CCIP2R_CECSEL */ 01218 /** 01219 * @} 01220 */ 01221 01222 #if defined(DSI) 01223 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source 01224 * @{ 01225 */ 01226 #define LL_RCC_DSI_CLKSOURCE RCC_D1CCIPR_DSISEL 01227 /** 01228 * @} 01229 */ 01230 #endif /* DSI */ 01231 01232 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source 01233 * @{ 01234 */ 01235 #if defined(RCC_D2CCIP1R_DFSDM1SEL) 01236 #define LL_RCC_DFSDM1_CLKSOURCE RCC_D2CCIP1R_DFSDM1SEL 01237 #else 01238 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CDCCIP1R_DFSDM1SEL 01239 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 01240 /** 01241 * @} 01242 */ 01243 01244 #if defined(DFSDM2_BASE) 01245 /** @defgroup RCC_LL_EC_DFSDM2 Peripheral DFSDM2 get clock source 01246 * @{ 01247 */ 01248 #define LL_RCC_DFSDM2_CLKSOURCE RCC_SRDCCIPR_DFSDM2SEL 01249 /** 01250 * @} 01251 */ 01252 #endif /* DFSDM2_BASE */ 01253 01254 01255 01256 /** @defgroup RCC_LL_EC_FMC Peripheral FMC get clock source 01257 * @{ 01258 */ 01259 #if defined(RCC_D1CCIPR_FMCSEL) 01260 #define LL_RCC_FMC_CLKSOURCE RCC_D1CCIPR_FMCSEL 01261 #else 01262 #define LL_RCC_FMC_CLKSOURCE RCC_CDCCIPR_FMCSEL 01263 #endif 01264 /** 01265 * @} 01266 */ 01267 01268 #if defined(QUADSPI) 01269 /** @defgroup RCC_LL_EC_QSPI Peripheral QSPI get clock source 01270 * @{ 01271 */ 01272 #define LL_RCC_QSPI_CLKSOURCE RCC_D1CCIPR_QSPISEL 01273 /** 01274 * @} 01275 */ 01276 #endif /* QUADSPI */ 01277 01278 #if defined(OCTOSPI1) || defined(OCTOSPI2) 01279 /** @defgroup RCC_LL_EC_OSPI Peripheral OSPI get clock source 01280 * @{ 01281 */ 01282 #if defined(RCC_CDCCIPR_OCTOSPISEL) 01283 #define LL_RCC_OSPI_CLKSOURCE RCC_CDCCIPR_OCTOSPISEL 01284 #else 01285 #define LL_RCC_OSPI_CLKSOURCE RCC_D1CCIPR_OCTOSPISEL 01286 #endif /* RCC_CDCCIPR_OCTOSPISEL */ 01287 /** 01288 * @} 01289 */ 01290 #endif /* OCTOSPI1 || OCTOSPI2 */ 01291 01292 /** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source 01293 * @{ 01294 */ 01295 #if defined(RCC_D1CCIPR_CKPERSEL) 01296 #define LL_RCC_CLKP_CLKSOURCE RCC_D1CCIPR_CKPERSEL 01297 #else 01298 #define LL_RCC_CLKP_CLKSOURCE RCC_CDCCIPR_CKPERSEL 01299 #endif /* RCC_D1CCIPR_CKPERSEL */ 01300 /** 01301 * @} 01302 */ 01303 01304 /** @defgroup RCC_LL_EC_SPIx Peripheral SPI get clock source 01305 * @{ 01306 */ 01307 #if defined(RCC_D2CCIP1R_SPI123SEL) 01308 #define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U) 01309 #else 01310 #define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U) 01311 #endif /* RCC_D2CCIP1R_SPI123SEL */ 01312 #if defined(RCC_D2CCIP1R_SPI45SEL) 01313 #define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U) 01314 #else 01315 #define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U) 01316 #endif /* RCC_D2CCIP1R_SPI45SEL */ 01317 #if defined(RCC_D3CCIPR_SPI6SEL) 01318 #define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U) 01319 #else 01320 #define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U) 01321 #endif /* RCC_D3CCIPR_SPI6SEL */ 01322 /** 01323 * @} 01324 */ 01325 01326 /** @defgroup RCC_LL_EC_SPDIF Peripheral SPDIF get clock source 01327 * @{ 01328 */ 01329 #if defined(RCC_D2CCIP1R_SPDIFSEL) 01330 #define LL_RCC_SPDIF_CLKSOURCE RCC_D2CCIP1R_SPDIFSEL 01331 #else 01332 #define LL_RCC_SPDIF_CLKSOURCE RCC_CDCCIP1R_SPDIFSEL 01333 #endif /* RCC_D2CCIP1R_SPDIFSEL */ 01334 /** 01335 * @} 01336 */ 01337 01338 #if defined(FDCAN1) || defined(FDCAN2) 01339 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source 01340 * @{ 01341 */ 01342 #if defined(RCC_D2CCIP1R_FDCANSEL) 01343 #define LL_RCC_FDCAN_CLKSOURCE RCC_D2CCIP1R_FDCANSEL 01344 #else 01345 #define LL_RCC_FDCAN_CLKSOURCE RCC_CDCCIP1R_FDCANSEL 01346 #endif 01347 /** 01348 * @} 01349 */ 01350 #endif /*FDCAN1 || FDCAN2*/ 01351 01352 /** @defgroup RCC_LL_EC_SWP Peripheral SWP get clock source 01353 * @{ 01354 */ 01355 #if defined(RCC_D2CCIP1R_SWPSEL) 01356 #define LL_RCC_SWP_CLKSOURCE RCC_D2CCIP1R_SWPSEL 01357 #else 01358 #define LL_RCC_SWP_CLKSOURCE RCC_CDCCIP1R_SWPSEL 01359 #endif /* RCC_D2CCIP1R_SWPSEL */ 01360 /** 01361 * @} 01362 */ 01363 01364 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source 01365 * @{ 01366 */ 01367 #if defined(RCC_D3CCIPR_ADCSEL) 01368 #define LL_RCC_ADC_CLKSOURCE RCC_D3CCIPR_ADCSEL 01369 #else 01370 #define LL_RCC_ADC_CLKSOURCE RCC_SRDCCIPR_ADCSEL 01371 #endif /* RCC_D3CCIPR_ADCSEL */ 01372 /** 01373 * @} 01374 */ 01375 01376 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection 01377 * @{ 01378 */ 01379 #define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000U) 01380 #define LL_RCC_RTC_CLKSOURCE_LSE (uint32_t)(RCC_BDCR_RTCSEL_0) 01381 #define LL_RCC_RTC_CLKSOURCE_LSI (uint32_t)(RCC_BDCR_RTCSEL_1) 01382 #define LL_RCC_RTC_CLKSOURCE_HSE (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1) 01383 /** 01384 * @} 01385 */ 01386 01387 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection 01388 * @{ 01389 */ 01390 #define LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U) 01391 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR_TIMPRE) 01392 /** 01393 * @} 01394 */ 01395 01396 #if defined(HRTIM1) 01397 /** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE High Resolution Timers clock selection 01398 * @{ 01399 */ 01400 #define LL_RCC_HRTIM_CLKSOURCE_TIM (uint32_t)(0x00000000U) /* HRTIM Clock source is same as other timers */ 01401 #define LL_RCC_HRTIM_CLKSOURCE_CPU (uint32_t)(RCC_CFGR_HRTIMSEL) /* HRTIM Clock source is the CPU clock */ 01402 /** 01403 * @} 01404 */ 01405 #endif /* HRTIM1 */ 01406 01407 /** @defgroup RCC_LL_EC_PLLSOURCE All PLLs entry clock source 01408 * @{ 01409 */ 01410 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCKSELR_PLLSRC_HSI 01411 #define LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_CSI 01412 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_HSE 01413 #define LL_RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC_NONE 01414 /** 01415 * @} 01416 */ 01417 01418 /** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input range 01419 * @{ 01420 */ 01421 #define LL_RCC_PLLINPUTRANGE_1_2 (uint32_t)(0x00000000U) 01422 #define LL_RCC_PLLINPUTRANGE_2_4 (uint32_t)(0x00000001) 01423 #define LL_RCC_PLLINPUTRANGE_4_8 (uint32_t)(0x00000002) 01424 #define LL_RCC_PLLINPUTRANGE_8_16 (uint32_t)(0x00000003) 01425 /** 01426 * @} 01427 */ 01428 01429 /** @defgroup RCC_LL_EC_PLLVCORANGE All PLLs VCO range 01430 * @{ 01431 */ 01432 #define LL_RCC_PLLVCORANGE_WIDE (uint32_t)(0x00000000U) /* VCO output range: 192 to 836 MHz OR 128 to 544 MHz (*) */ 01433 #define LL_RCC_PLLVCORANGE_MEDIUM (uint32_t)(0x00000001) /* VCO output range: 150 to 420 MHz */ 01434 /** 01435 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 01436 * @} 01437 */ 01438 01439 /** 01440 * @} 01441 */ 01442 01443 /* Exported macro ------------------------------------------------------------*/ 01444 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros 01445 * @{ 01446 */ 01447 01448 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros 01449 * @{ 01450 */ 01451 01452 /** 01453 * @brief Write a value in RCC register 01454 * @param __REG__ Register to be written 01455 * @param __VALUE__ Value to be written in the register 01456 * @retval None 01457 */ 01458 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) 01459 01460 /** 01461 * @brief Read a value in RCC register 01462 * @param __REG__ Register to be read 01463 * @retval Register value 01464 */ 01465 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) 01466 /** 01467 * @} 01468 */ 01469 01470 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies 01471 * @{ 01472 */ 01473 01474 /** 01475 * @brief Helper macro to calculate the SYSCLK frequency 01476 * @param __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P) 01477 * @param __SYSPRESCALER__ This parameter can be one of the following values: 01478 * @arg @ref LL_RCC_SYSCLK_DIV_1 01479 * @arg @ref LL_RCC_SYSCLK_DIV_2 01480 * @arg @ref LL_RCC_SYSCLK_DIV_4 01481 * @arg @ref LL_RCC_SYSCLK_DIV_8 01482 * @arg @ref LL_RCC_SYSCLK_DIV_16 01483 * @arg @ref LL_RCC_SYSCLK_DIV_64 01484 * @arg @ref LL_RCC_SYSCLK_DIV_128 01485 * @arg @ref LL_RCC_SYSCLK_DIV_256 01486 * @arg @ref LL_RCC_SYSCLK_DIV_512 01487 * @retval SYSCLK clock frequency (in Hz) 01488 */ 01489 #if defined(RCC_D1CFGR_D1CPRE) 01490 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU)) 01491 #else 01492 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU)) 01493 #endif /* RCC_D1CFGR_D1CPRE */ 01494 01495 /** 01496 * @brief Helper macro to calculate the HCLK frequency 01497 * @param __SYSCLKFREQ__ SYSCLK frequency. 01498 * @param __HPRESCALER__ This parameter can be one of the following values: 01499 * @arg @ref LL_RCC_AHB_DIV_1 01500 * @arg @ref LL_RCC_AHB_DIV_2 01501 * @arg @ref LL_RCC_AHB_DIV_4 01502 * @arg @ref LL_RCC_AHB_DIV_8 01503 * @arg @ref LL_RCC_AHB_DIV_16 01504 * @arg @ref LL_RCC_AHB_DIV_64 01505 * @arg @ref LL_RCC_AHB_DIV_128 01506 * @arg @ref LL_RCC_AHB_DIV_256 01507 * @arg @ref LL_RCC_AHB_DIV_512 01508 * @retval HCLK clock frequency (in Hz) 01509 */ 01510 #if defined(RCC_D1CFGR_HPRE) 01511 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)) 01512 #else 01513 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)) 01514 #endif /* RCC_D1CFGR_HPRE */ 01515 01516 /** 01517 * @brief Helper macro to calculate the PCLK1 frequency (ABP1) 01518 * @param __HCLKFREQ__ HCLK frequency 01519 * @param __APB1PRESCALER__ This parameter can be one of the following values: 01520 * @arg @ref LL_RCC_APB1_DIV_1 01521 * @arg @ref LL_RCC_APB1_DIV_2 01522 * @arg @ref LL_RCC_APB1_DIV_4 01523 * @arg @ref LL_RCC_APB1_DIV_8 01524 * @arg @ref LL_RCC_APB1_DIV_16 01525 * @retval PCLK1 clock frequency (in Hz) 01526 */ 01527 #if defined(RCC_D2CFGR_D2PPRE1) 01528 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)) 01529 #else 01530 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)) 01531 #endif /* RCC_D2CFGR_D2PPRE1 */ 01532 01533 /** 01534 * @brief Helper macro to calculate the PCLK2 frequency (ABP2) 01535 * @param __HCLKFREQ__ HCLK frequency 01536 * @param __APB2PRESCALER__ This parameter can be one of the following values: 01537 * @arg @ref LL_RCC_APB2_DIV_1 01538 * @arg @ref LL_RCC_APB2_DIV_2 01539 * @arg @ref LL_RCC_APB2_DIV_4 01540 * @arg @ref LL_RCC_APB2_DIV_8 01541 * @arg @ref LL_RCC_APB2_DIV_16 01542 * @retval PCLK2 clock frequency (in Hz) 01543 */ 01544 #if defined(RCC_D2CFGR_D2PPRE2) 01545 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)) 01546 #else 01547 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)) 01548 #endif /* RCC_D2CFGR_D2PPRE2 */ 01549 01550 /** 01551 * @brief Helper macro to calculate the PCLK3 frequency (APB3) 01552 * @param __HCLKFREQ__ HCLK frequency 01553 * @param __APB3PRESCALER__ This parameter can be one of the following values: 01554 * @arg @ref LL_RCC_APB3_DIV_1 01555 * @arg @ref LL_RCC_APB3_DIV_2 01556 * @arg @ref LL_RCC_APB3_DIV_4 01557 * @arg @ref LL_RCC_APB3_DIV_8 01558 * @arg @ref LL_RCC_APB3_DIV_16 01559 * @retval PCLK1 clock frequency (in Hz) 01560 */ 01561 #if defined(RCC_D1CFGR_D1PPRE) 01562 #define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU)) 01563 #else 01564 #define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU)) 01565 #endif /* RCC_D1CFGR_D1PPRE */ 01566 01567 /** 01568 * @brief Helper macro to calculate the PCLK4 frequency (ABP4) 01569 * @param __HCLKFREQ__ HCLK frequency 01570 * @param __APB4PRESCALER__ This parameter can be one of the following values: 01571 * @arg @ref LL_RCC_APB4_DIV_1 01572 * @arg @ref LL_RCC_APB4_DIV_2 01573 * @arg @ref LL_RCC_APB4_DIV_4 01574 * @arg @ref LL_RCC_APB4_DIV_8 01575 * @arg @ref LL_RCC_APB4_DIV_16 01576 * @retval PCLK1 clock frequency (in Hz) 01577 */ 01578 #if defined(RCC_D3CFGR_D3PPRE) 01579 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU)) 01580 #else 01581 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU)) 01582 #endif /* RCC_D3CFGR_D3PPRE */ 01583 01584 /** 01585 * @} 01586 */ 01587 01588 #if defined(USE_FULL_LL_DRIVER) 01589 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency 01590 * @{ 01591 */ 01592 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ 01593 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ 01594 /** 01595 * @} 01596 */ 01597 #endif /* USE_FULL_LL_DRIVER */ 01598 01599 /** 01600 * @} 01601 */ 01602 01603 /* Exported functions --------------------------------------------------------*/ 01604 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions 01605 * @{ 01606 */ 01607 01608 /** @defgroup RCC_LL_EF_HSE HSE 01609 * @{ 01610 */ 01611 01612 /** 01613 * @brief Enable the Clock Security System. 01614 * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless 01615 * a reset occurs or system enter in standby mode. 01616 * @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS 01617 * @retval None 01618 */ 01619 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) 01620 { 01621 SET_BIT(RCC->CR, RCC_CR_CSSHSEON); 01622 } 01623 01624 /** 01625 * @brief Enable HSE external oscillator (HSE Bypass) 01626 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass 01627 * @retval None 01628 */ 01629 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) 01630 { 01631 SET_BIT(RCC->CR, RCC_CR_HSEBYP); 01632 } 01633 01634 /** 01635 * @brief Disable HSE external oscillator (HSE Bypass) 01636 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass 01637 * @retval None 01638 */ 01639 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) 01640 { 01641 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 01642 } 01643 01644 #if defined(RCC_CR_HSEEXT) 01645 /** 01646 * @brief Select the Analog HSE external clock type in Bypass mode 01647 * @rmtoll CR HSEEXT LL_RCC_HSE_SelectAnalogClock 01648 * @retval None 01649 */ 01650 __STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void) 01651 { 01652 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); 01653 } 01654 01655 /** 01656 * @brief Select the Digital HSE external clock type in Bypass mode 01657 * @rmtoll CR HSEEXT LL_RCC_HSE_SelectDigitalClock 01658 * @retval None 01659 */ 01660 __STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void) 01661 { 01662 SET_BIT(RCC->CR, RCC_CR_HSEEXT); 01663 } 01664 #endif /* RCC_CR_HSEEXT */ 01665 01666 /** 01667 * @brief Enable HSE crystal oscillator (HSE ON) 01668 * @rmtoll CR HSEON LL_RCC_HSE_Enable 01669 * @retval None 01670 */ 01671 __STATIC_INLINE void LL_RCC_HSE_Enable(void) 01672 { 01673 SET_BIT(RCC->CR, RCC_CR_HSEON); 01674 } 01675 01676 /** 01677 * @brief Disable HSE crystal oscillator (HSE ON) 01678 * @rmtoll CR HSEON LL_RCC_HSE_Disable 01679 * @retval None 01680 */ 01681 __STATIC_INLINE void LL_RCC_HSE_Disable(void) 01682 { 01683 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); 01684 } 01685 01686 /** 01687 * @brief Check if HSE oscillator Ready 01688 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady 01689 * @retval State of bit (1 or 0). 01690 */ 01691 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) 01692 { 01693 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY))?1UL:0UL); 01694 } 01695 01696 /** 01697 * @} 01698 */ 01699 01700 /** @defgroup RCC_LL_EF_HSI HSI 01701 * @{ 01702 */ 01703 01704 /** 01705 * @brief Enable HSI oscillator 01706 * @rmtoll CR HSION LL_RCC_HSI_Enable 01707 * @retval None 01708 */ 01709 __STATIC_INLINE void LL_RCC_HSI_Enable(void) 01710 { 01711 SET_BIT(RCC->CR, RCC_CR_HSION); 01712 } 01713 01714 /** 01715 * @brief Disable HSI oscillator 01716 * @rmtoll CR HSION LL_RCC_HSI_Disable 01717 * @retval None 01718 */ 01719 __STATIC_INLINE void LL_RCC_HSI_Disable(void) 01720 { 01721 CLEAR_BIT(RCC->CR, RCC_CR_HSION); 01722 } 01723 01724 /** 01725 * @brief Check if HSI clock is ready 01726 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady 01727 * @retval State of bit (1 or 0). 01728 */ 01729 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) 01730 { 01731 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))?1UL:0UL); 01732 } 01733 01734 /** 01735 * @brief Check if HSI new divider applied and ready 01736 * @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady 01737 * @retval State of bit (1 or 0). 01738 */ 01739 __STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void) 01740 { 01741 return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF))?1UL:0UL); 01742 } 01743 01744 /** 01745 * @brief Set HSI divider 01746 * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider 01747 * @param Divider This parameter can be one of the following values: 01748 * @arg @ref LL_RCC_HSI_DIV1 01749 * @arg @ref LL_RCC_HSI_DIV2 01750 * @arg @ref LL_RCC_HSI_DIV4 01751 * @arg @ref LL_RCC_HSI_DIV8 01752 * @retval None. 01753 */ 01754 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider) 01755 { 01756 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider); 01757 } 01758 01759 /** 01760 * @brief Get HSI divider 01761 * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider 01762 * @retval can be one of the following values: 01763 * @arg @ref LL_RCC_HSI_DIV1 01764 * @arg @ref LL_RCC_HSI_DIV2 01765 * @arg @ref LL_RCC_HSI_DIV4 01766 * @arg @ref LL_RCC_HSI_DIV8 01767 */ 01768 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void) 01769 { 01770 return (READ_BIT(RCC->CR, RCC_CR_HSIDIV)); 01771 } 01772 01773 /** 01774 * @brief Enable HSI oscillator in Stop mode 01775 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableStopMode 01776 * @retval None 01777 */ 01778 __STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void) 01779 { 01780 SET_BIT(RCC->CR, RCC_CR_HSIKERON); 01781 } 01782 01783 /** 01784 * @brief Disable HSI oscillator in Stop mode 01785 * @rmtoll CR HSION LL_RCC_HSI_DisableStopMode 01786 * @retval None 01787 */ 01788 __STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void) 01789 { 01790 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); 01791 } 01792 01793 /** 01794 * @brief Get HSI Calibration value 01795 * @note When HSITRIM is written, HSICAL is updated with the sum of 01796 * HSITRIM and the factory trim value 01797 * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration 01798 * @retval A value between 0 and 4095 (0xFFF) 01799 */ 01800 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) 01801 { 01802 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos); 01803 } 01804 01805 /** 01806 * @brief Set HSI Calibration trimming 01807 * @note user-programmable trimming value that is added to the HSICAL 01808 * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value, 01809 * should trim the HSI to 64 MHz +/- 1 % 01810 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming 01811 * @param Value can be a value between 0 and 127 (63 for Cut1.x) 01812 * @retval None 01813 */ 01814 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) 01815 { 01816 #if defined(RCC_VER_X) 01817 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) 01818 { 01819 /* STM32H7 Rev.Y */ 01820 MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U); 01821 } 01822 else 01823 { 01824 /* STM32H7 Rev.V */ 01825 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); 01826 } 01827 #else 01828 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); 01829 #endif /* RCC_VER_X */ 01830 } 01831 01832 /** 01833 * @brief Get HSI Calibration trimming 01834 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_GetCalibTrimming 01835 * @retval A value between 0 and 127 (63 for Cut1.x) 01836 */ 01837 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) 01838 { 01839 #if defined(RCC_VER_X) 01840 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) 01841 { 01842 /* STM32H7 Rev.Y */ 01843 return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U); 01844 } 01845 else 01846 { 01847 /* STM32H7 Rev.V */ 01848 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); 01849 } 01850 #else 01851 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); 01852 #endif /* RCC_VER_X */ 01853 } 01854 01855 /** 01856 * @} 01857 */ 01858 01859 /** @defgroup RCC_LL_EF_CSI CSI 01860 * @{ 01861 */ 01862 01863 /** 01864 * @brief Enable CSI oscillator 01865 * @rmtoll CR CSION LL_RCC_CSI_Enable 01866 * @retval None 01867 */ 01868 __STATIC_INLINE void LL_RCC_CSI_Enable(void) 01869 { 01870 SET_BIT(RCC->CR, RCC_CR_CSION); 01871 } 01872 01873 /** 01874 * @brief Disable CSI oscillator 01875 * @rmtoll CR CSION LL_RCC_CSI_Disable 01876 * @retval None 01877 */ 01878 __STATIC_INLINE void LL_RCC_CSI_Disable(void) 01879 { 01880 CLEAR_BIT(RCC->CR, RCC_CR_CSION); 01881 } 01882 01883 /** 01884 * @brief Check if CSI clock is ready 01885 * @rmtoll CR CSIRDY LL_RCC_CSI_IsReady 01886 * @retval State of bit (1 or 0). 01887 */ 01888 __STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void) 01889 { 01890 return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY))?1UL:0UL); 01891 } 01892 01893 /** 01894 * @brief Enable CSI oscillator in Stop mode 01895 * @rmtoll CR CSIKERON LL_RCC_CSI_EnableStopMode 01896 * @retval None 01897 */ 01898 __STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void) 01899 { 01900 SET_BIT(RCC->CR, RCC_CR_CSIKERON); 01901 } 01902 01903 /** 01904 * @brief Disable CSI oscillator in Stop mode 01905 * @rmtoll CR CSIKERON LL_RCC_CSI_DisableStopMode 01906 * @retval None 01907 */ 01908 __STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void) 01909 { 01910 CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON); 01911 } 01912 01913 /** 01914 * @brief Get CSI Calibration value 01915 * @note When CSITRIM is written, CSICAL is updated with the sum of 01916 * CSITRIM and the factory trim value 01917 * @rmtoll CSICFGR CSICAL LL_RCC_CSI_GetCalibration 01918 * @retval A value between 0 and 255 (0xFF) 01919 */ 01920 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void) 01921 { 01922 #if defined(RCC_VER_X) 01923 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) 01924 { 01925 /* STM32H7 Rev.Y */ 01926 return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U); 01927 } 01928 else 01929 { 01930 /* STM32H7 Rev.V */ 01931 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); 01932 } 01933 #else 01934 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); 01935 #endif /* RCC_VER_X */ 01936 } 01937 01938 /** 01939 * @brief Set CSI Calibration trimming 01940 * @note user-programmable trimming value that is added to the CSICAL 01941 * @note Default value is 16, which, when added to the CSICAL value, 01942 * should trim the CSI to 4 MHz +/- 1 % 01943 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming 01944 * @param Value can be a value between 0 and 31 01945 * @retval None 01946 */ 01947 __STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value) 01948 { 01949 #if defined(RCC_VER_X) 01950 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) 01951 { 01952 /* STM32H7 Rev.Y */ 01953 MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U); 01954 } 01955 else 01956 { 01957 /* STM32H7 Rev.V */ 01958 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); 01959 } 01960 #else 01961 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); 01962 #endif /* RCC_VER_X */ 01963 } 01964 01965 /** 01966 * @brief Get CSI Calibration trimming 01967 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming 01968 * @retval A value between 0 and 31 01969 */ 01970 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void) 01971 { 01972 #if defined(RCC_VER_X) 01973 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) 01974 { 01975 /* STM32H7 Rev.Y */ 01976 return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U); 01977 } 01978 else 01979 { 01980 /* STM32H7 Rev.V */ 01981 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); 01982 } 01983 #else 01984 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); 01985 #endif /* RCC_VER_X */ 01986 } 01987 01988 /** 01989 * @} 01990 */ 01991 01992 /** @defgroup RCC_LL_EF_HSI48 HSI48 01993 * @{ 01994 */ 01995 01996 /** 01997 * @brief Enable HSI48 oscillator 01998 * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable 01999 * @retval None 02000 */ 02001 __STATIC_INLINE void LL_RCC_HSI48_Enable(void) 02002 { 02003 SET_BIT(RCC->CR, RCC_CR_HSI48ON); 02004 } 02005 02006 /** 02007 * @brief Disable HSI48 oscillator 02008 * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable 02009 * @retval None 02010 */ 02011 __STATIC_INLINE void LL_RCC_HSI48_Disable(void) 02012 { 02013 CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); 02014 } 02015 02016 /** 02017 * @brief Check if HSI48 clock is ready 02018 * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady 02019 * @retval State of bit (1 or 0). 02020 */ 02021 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) 02022 { 02023 return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY))?1UL:0UL); 02024 } 02025 02026 /** 02027 * @brief Get HSI48 Calibration value 02028 * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of 02029 * HSI48TRIM and the factory trim value 02030 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration 02031 * @retval A value between 0 and 1023 (0x3FF) 02032 */ 02033 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) 02034 { 02035 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); 02036 } 02037 /** 02038 * @} 02039 */ 02040 02041 #if defined(RCC_CR_D1CKRDY) 02042 02043 /** @defgroup RCC_LL_EF_D1CLK D1CKREADY 02044 * @{ 02045 */ 02046 02047 /** 02048 * @brief Check if D1 clock is ready 02049 * @rmtoll CR D1CKRDY LL_RCC_D1CK_IsReady 02050 * @retval State of bit (1 or 0). 02051 */ 02052 __STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void) 02053 { 02054 return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY))?1UL:0UL); 02055 } 02056 02057 /** 02058 * @} 02059 */ 02060 #else 02061 02062 /** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY 02063 * @{ 02064 */ 02065 02066 /** 02067 * @brief Check if CPU clock is ready 02068 * @rmtoll CR CPUCKRDY LL_RCC_CPUCK_IsReady 02069 * @retval State of bit (1 or 0). 02070 */ 02071 __STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void) 02072 { 02073 return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY))?1UL:0UL); 02074 } 02075 /* alias */ 02076 #define LL_RCC_D1CK_IsReady LL_RCC_CPUCK_IsReady 02077 /** 02078 * @} 02079 */ 02080 #endif /* RCC_CR_D1CKRDY */ 02081 02082 #if defined(RCC_CR_D2CKRDY) 02083 02084 /** @defgroup RCC_LL_EF_D2CLK D2CKREADY 02085 * @{ 02086 */ 02087 02088 /** 02089 * @brief Check if D2 clock is ready 02090 * @rmtoll CR D2CKRDY LL_RCC_D2CK_IsReady 02091 * @retval State of bit (1 or 0). 02092 */ 02093 __STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void) 02094 { 02095 return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY))?1UL:0UL); 02096 } 02097 /** 02098 * @} 02099 */ 02100 #else 02101 02102 /** @defgroup RCC_LL_EF_CDCLK CDCKREADY 02103 * @{ 02104 */ 02105 02106 /** 02107 * @brief Check if CD clock is ready 02108 * @rmtoll CR CDCKRDY LL_RCC_CDCK_IsReady 02109 * @retval State of bit (1 or 0). 02110 */ 02111 __STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void) 02112 { 02113 return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY))?1UL:0UL); 02114 } 02115 #define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady 02116 /** 02117 * @} 02118 */ 02119 #endif /* RCC_CR_D2CKRDY */ 02120 02121 /** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET 02122 * @{ 02123 */ 02124 #if defined(RCC_GCR_WW1RSC) 02125 02126 /** 02127 * @brief Enable system wide reset for Window Watch Dog 1 02128 * @rmtoll GCR WW1RSC LL_RCC_WWDG1_EnableSystemReset 02129 * @retval None. 02130 */ 02131 __STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void) 02132 { 02133 SET_BIT(RCC->GCR, RCC_GCR_WW1RSC); 02134 } 02135 02136 /** 02137 * @brief Check if Window Watch Dog 1 reset is system wide 02138 * @rmtoll GCR WW1RSC LL_RCC_WWDG1_IsSystemReset 02139 * @retval State of bit (1 or 0). 02140 */ 02141 __STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void) 02142 { 02143 return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC)?1UL:0UL); 02144 } 02145 #endif /* RCC_GCR_WW1RSC */ 02146 02147 #if defined(DUAL_CORE) 02148 /** 02149 * @brief Enable system wide reset for Window Watch Dog 2 02150 * @rmtoll GCR WW1RSC LL_RCC_WWDG2_EnableSystemReset 02151 * @retval None. 02152 */ 02153 __STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void) 02154 { 02155 SET_BIT(RCC->GCR, RCC_GCR_WW2RSC); 02156 } 02157 02158 /** 02159 * @brief Check if Window Watch Dog 2 reset is system wide 02160 * @rmtoll GCR WW2RSC LL_RCC_WWDG2_IsSystemReset 02161 * @retval State of bit (1 or 0). 02162 */ 02163 __STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void) 02164 { 02165 return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC)?1UL:0UL); 02166 } 02167 #endif /*DUAL_CORE*/ 02168 /** 02169 * @} 02170 */ 02171 02172 #if defined(DUAL_CORE) 02173 /** @defgroup RCC_LL_EF_BOOT_CPU CPU 02174 * @{ 02175 */ 02176 02177 /** 02178 * @brief Force CM4 boot (if hold by option byte BCM4 = 0) 02179 * @rmtoll GCR BOOT_C2 LL_RCC_ForceCM4Boot 02180 * @retval None. 02181 */ 02182 __STATIC_INLINE void LL_RCC_ForceCM4Boot(void) 02183 { 02184 SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2); 02185 } 02186 02187 /** 02188 * @brief Check if CM4 boot is forced 02189 * @rmtoll GCR BOOT_C2 LL_RCC_IsCM4BootForced 02190 * @retval State of bit (1 or 0). 02191 */ 02192 __STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void) 02193 { 02194 return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2)?1UL:0UL); 02195 } 02196 02197 /** 02198 * @brief Force CM7 boot (if hold by option byte BCM7 = 0) 02199 * @rmtoll GCR BOOT_C1 LL_RCC_ForceCM7Boot 02200 * @retval None. 02201 */ 02202 __STATIC_INLINE void LL_RCC_ForceCM7Boot(void) 02203 { 02204 SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1); 02205 } 02206 02207 /** 02208 * @brief Check if CM7 boot is forced 02209 * @rmtoll GCR BOOT_C1 LL_RCC_IsCM7BootForced 02210 * @retval State of bit (1 or 0). 02211 */ 02212 __STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void) 02213 { 02214 return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1)?1UL:0UL); 02215 } 02216 02217 /** 02218 * @} 02219 */ 02220 #endif /*DUAL_CORE*/ 02221 02222 /** @defgroup RCC_LL_EF_LSE LSE 02223 * @{ 02224 */ 02225 02226 /** 02227 * @brief Enable the Clock Security System on LSE. 02228 * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless 02229 * a clock failure is detected. 02230 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS 02231 * @retval None 02232 */ 02233 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) 02234 { 02235 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); 02236 } 02237 02238 /** 02239 * @brief Check if LSE failure is detected by Clock Security System 02240 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsFailureDetected 02241 * @retval State of bit (1 or 0). 02242 */ 02243 __STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void) 02244 { 02245 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD))?1UL:0UL); 02246 } 02247 02248 /** 02249 * @brief Enable Low Speed External (LSE) crystal. 02250 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable 02251 * @retval None 02252 */ 02253 __STATIC_INLINE void LL_RCC_LSE_Enable(void) 02254 { 02255 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 02256 } 02257 02258 /** 02259 * @brief Disable Low Speed External (LSE) crystal. 02260 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable 02261 * @retval None 02262 */ 02263 __STATIC_INLINE void LL_RCC_LSE_Disable(void) 02264 { 02265 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 02266 } 02267 02268 /** 02269 * @brief Enable external clock source (LSE bypass). 02270 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass 02271 * @retval None 02272 */ 02273 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) 02274 { 02275 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 02276 } 02277 02278 /** 02279 * @brief Disable external clock source (LSE bypass). 02280 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass 02281 * @retval None 02282 */ 02283 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) 02284 { 02285 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 02286 } 02287 02288 #if defined(RCC_BDCR_LSEEXT) 02289 /** 02290 * @brief Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active). 02291 * @note The external clock must be enabled with the LSEON bit, to be used by the device. 02292 * The LSEEXT bit can be written only if the LSE oscillator is disabled. 02293 * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectDigitalClock 02294 * @retval None 02295 */ 02296 __STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void) 02297 { 02298 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); 02299 } 02300 02301 /** 02302 * @brief Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset). 02303 * @note The external clock must be enabled with the LSEON bit, to be used by the device. 02304 * The LSEEXT bit can be written only if the LSE oscillator is disabled. 02305 * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectAnalogClock 02306 * @retval None 02307 */ 02308 __STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void) 02309 { 02310 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); 02311 } 02312 #endif /* RCC_BDCR_LSEEXT */ 02313 02314 /** 02315 * @brief Set LSE oscillator drive capability 02316 * @note The oscillator is in Xtal mode when it is not in bypass mode. 02317 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability 02318 * @param LSEDrive This parameter can be one of the following values: 02319 * @arg @ref LL_RCC_LSEDRIVE_LOW 02320 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW 02321 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH 02322 * @arg @ref LL_RCC_LSEDRIVE_HIGH 02323 * @retval None 02324 */ 02325 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) 02326 { 02327 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); 02328 } 02329 02330 /** 02331 * @brief Get LSE oscillator drive capability 02332 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability 02333 * @retval Returned value can be one of the following values: 02334 * @arg @ref LL_RCC_LSEDRIVE_LOW 02335 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW 02336 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH 02337 * @arg @ref LL_RCC_LSEDRIVE_HIGH 02338 */ 02339 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) 02340 { 02341 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); 02342 } 02343 02344 /** 02345 * @brief Check if LSE oscillator Ready 02346 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady 02347 * @retval State of bit (1 or 0). 02348 */ 02349 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) 02350 { 02351 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY))?1UL:0UL); 02352 } 02353 02354 /** 02355 * @} 02356 */ 02357 02358 /** @defgroup RCC_LL_EF_LSI LSI 02359 * @{ 02360 */ 02361 02362 /** 02363 * @brief Enable LSI Oscillator 02364 * @rmtoll CSR LSION LL_RCC_LSI_Enable 02365 * @retval None 02366 */ 02367 __STATIC_INLINE void LL_RCC_LSI_Enable(void) 02368 { 02369 SET_BIT(RCC->CSR, RCC_CSR_LSION); 02370 } 02371 02372 /** 02373 * @brief Disable LSI Oscillator 02374 * @rmtoll CSR LSION LL_RCC_LSI_Disable 02375 * @retval None 02376 */ 02377 __STATIC_INLINE void LL_RCC_LSI_Disable(void) 02378 { 02379 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); 02380 } 02381 02382 /** 02383 * @brief Check if LSI is Ready 02384 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady 02385 * @retval State of bit (1 or 0). 02386 */ 02387 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) 02388 { 02389 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY))?1UL:0UL); 02390 } 02391 02392 /** 02393 * @} 02394 */ 02395 02396 /** @defgroup RCC_LL_EF_System System 02397 * @{ 02398 */ 02399 02400 /** 02401 * @brief Configure the system clock source 02402 * @rmtoll CFGR SW LL_RCC_SetSysClkSource 02403 * @param Source This parameter can be one of the following values: 02404 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI 02405 * @arg @ref LL_RCC_SYS_CLKSOURCE_CSI 02406 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE 02407 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1 02408 * @retval None 02409 */ 02410 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) 02411 { 02412 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 02413 } 02414 02415 /** 02416 * @brief Get the system clock source 02417 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource 02418 * @retval Returned value can be one of the following values: 02419 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI 02420 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI 02421 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE 02422 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 02423 */ 02424 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) 02425 { 02426 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 02427 } 02428 02429 /** 02430 * @brief Configure the system wakeup clock source 02431 * @rmtoll CFGR STOPWUCK LL_RCC_SetSysWakeUpClkSource 02432 * @param Source This parameter can be one of the following values: 02433 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI 02434 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI 02435 * @retval None 02436 */ 02437 __STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source) 02438 { 02439 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source); 02440 } 02441 02442 /** 02443 * @brief Get the system wakeup clock source 02444 * @rmtoll CFGR STOPWUCK LL_RCC_GetSysWakeUpClkSource 02445 * @retval Returned value can be one of the following values: 02446 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI 02447 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI 02448 */ 02449 __STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void) 02450 { 02451 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); 02452 } 02453 02454 /** 02455 * @brief Configure the kernel wakeup clock source 02456 * @rmtoll CFGR STOPKERWUCK LL_RCC_SetKerWakeUpClkSource 02457 * @param Source This parameter can be one of the following values: 02458 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI 02459 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI 02460 * @retval None 02461 */ 02462 __STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source) 02463 { 02464 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source); 02465 } 02466 02467 /** 02468 * @brief Get the kernel wakeup clock source 02469 * @rmtoll CFGR STOPKERWUCK LL_RCC_GetKerWakeUpClkSource 02470 * @retval Returned value can be one of the following values: 02471 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI 02472 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI 02473 */ 02474 __STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void) 02475 { 02476 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK)); 02477 } 02478 02479 /** 02480 * @brief Set System prescaler 02481 * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_SetSysPrescaler 02482 * @param Prescaler This parameter can be one of the following values: 02483 * @arg @ref LL_RCC_SYSCLK_DIV_1 02484 * @arg @ref LL_RCC_SYSCLK_DIV_2 02485 * @arg @ref LL_RCC_SYSCLK_DIV_4 02486 * @arg @ref LL_RCC_SYSCLK_DIV_8 02487 * @arg @ref LL_RCC_SYSCLK_DIV_16 02488 * @arg @ref LL_RCC_SYSCLK_DIV_64 02489 * @arg @ref LL_RCC_SYSCLK_DIV_128 02490 * @arg @ref LL_RCC_SYSCLK_DIV_256 02491 * @arg @ref LL_RCC_SYSCLK_DIV_512 02492 * @retval None 02493 */ 02494 __STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler) 02495 { 02496 #if defined(RCC_D1CFGR_D1CPRE) 02497 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler); 02498 #else 02499 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler); 02500 #endif /* RCC_D1CFGR_D1CPRE */ 02501 } 02502 02503 /** 02504 * @brief Set AHB prescaler 02505 * @rmtoll D1CFGR/CDCFGR1 HPRE LL_RCC_SetAHBPrescaler 02506 * @param Prescaler This parameter can be one of the following values: 02507 * @arg @ref LL_RCC_AHB_DIV_1 02508 * @arg @ref LL_RCC_AHB_DIV_2 02509 * @arg @ref LL_RCC_AHB_DIV_4 02510 * @arg @ref LL_RCC_AHB_DIV_8 02511 * @arg @ref LL_RCC_AHB_DIV_16 02512 * @arg @ref LL_RCC_AHB_DIV_64 02513 * @arg @ref LL_RCC_AHB_DIV_128 02514 * @arg @ref LL_RCC_AHB_DIV_256 02515 * @arg @ref LL_RCC_AHB_DIV_512 02516 * @retval None 02517 */ 02518 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) 02519 { 02520 #if defined(RCC_D1CFGR_HPRE) 02521 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler); 02522 #else 02523 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler); 02524 #endif /* RCC_D1CFGR_HPRE */ 02525 } 02526 02527 /** 02528 * @brief Set APB1 prescaler 02529 * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_SetAPB1Prescaler 02530 * @param Prescaler This parameter can be one of the following values: 02531 * @arg @ref LL_RCC_APB1_DIV_1 02532 * @arg @ref LL_RCC_APB1_DIV_2 02533 * @arg @ref LL_RCC_APB1_DIV_4 02534 * @arg @ref LL_RCC_APB1_DIV_8 02535 * @arg @ref LL_RCC_APB1_DIV_16 02536 * @retval None 02537 */ 02538 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) 02539 { 02540 #if defined(RCC_D2CFGR_D2PPRE1) 02541 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler); 02542 #else 02543 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler); 02544 #endif /* RCC_D2CFGR_D2PPRE1 */ 02545 } 02546 02547 /** 02548 * @brief Set APB2 prescaler 02549 * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_SetAPB2Prescaler 02550 * @param Prescaler This parameter can be one of the following values: 02551 * @arg @ref LL_RCC_APB2_DIV_1 02552 * @arg @ref LL_RCC_APB2_DIV_2 02553 * @arg @ref LL_RCC_APB2_DIV_4 02554 * @arg @ref LL_RCC_APB2_DIV_8 02555 * @arg @ref LL_RCC_APB2_DIV_16 02556 * @retval None 02557 */ 02558 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) 02559 { 02560 #if defined(RCC_D2CFGR_D2PPRE2) 02561 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler); 02562 #else 02563 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler); 02564 #endif /* RCC_D2CFGR_D2PPRE2 */ 02565 } 02566 02567 /** 02568 * @brief Set APB3 prescaler 02569 * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_SetAPB3Prescaler 02570 * @param Prescaler This parameter can be one of the following values: 02571 * @arg @ref LL_RCC_APB3_DIV_1 02572 * @arg @ref LL_RCC_APB3_DIV_2 02573 * @arg @ref LL_RCC_APB3_DIV_4 02574 * @arg @ref LL_RCC_APB3_DIV_8 02575 * @arg @ref LL_RCC_APB3_DIV_16 02576 * @retval None 02577 */ 02578 __STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler) 02579 { 02580 #if defined(RCC_D1CFGR_D1PPRE) 02581 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler); 02582 #else 02583 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler); 02584 #endif /* RCC_D1CFGR_D1PPRE */ 02585 } 02586 02587 /** 02588 * @brief Set APB4 prescaler 02589 * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_SetAPB4Prescaler 02590 * @param Prescaler This parameter can be one of the following values: 02591 * @arg @ref LL_RCC_APB4_DIV_1 02592 * @arg @ref LL_RCC_APB4_DIV_2 02593 * @arg @ref LL_RCC_APB4_DIV_4 02594 * @arg @ref LL_RCC_APB4_DIV_8 02595 * @arg @ref LL_RCC_APB4_DIV_16 02596 * @retval None 02597 */ 02598 __STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler) 02599 { 02600 #if defined(RCC_D3CFGR_D3PPRE) 02601 MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler); 02602 #else 02603 MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler); 02604 #endif /* RCC_D3CFGR_D3PPRE */ 02605 } 02606 02607 /** 02608 * @brief Get System prescaler 02609 * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_GetSysPrescaler 02610 * @retval Returned value can be one of the following values: 02611 * @arg @ref LL_RCC_SYSCLK_DIV_1 02612 * @arg @ref LL_RCC_SYSCLK_DIV_2 02613 * @arg @ref LL_RCC_SYSCLK_DIV_4 02614 * @arg @ref LL_RCC_SYSCLK_DIV_8 02615 * @arg @ref LL_RCC_SYSCLK_DIV_16 02616 * @arg @ref LL_RCC_SYSCLK_DIV_64 02617 * @arg @ref LL_RCC_SYSCLK_DIV_128 02618 * @arg @ref LL_RCC_SYSCLK_DIV_256 02619 * @arg @ref LL_RCC_SYSCLK_DIV_512 02620 */ 02621 __STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void) 02622 { 02623 #if defined(RCC_D1CFGR_D1CPRE) 02624 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE)); 02625 #else 02626 return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE)); 02627 #endif /* RCC_D1CFGR_D1CPRE */ 02628 } 02629 02630 /** 02631 * @brief Get AHB prescaler 02632 * @rmtoll D1CFGR/ CDCFGR1 HPRE LL_RCC_GetAHBPrescaler 02633 * @retval Returned value can be one of the following values: 02634 * @arg @ref LL_RCC_AHB_DIV_1 02635 * @arg @ref LL_RCC_AHB_DIV_2 02636 * @arg @ref LL_RCC_AHB_DIV_4 02637 * @arg @ref LL_RCC_AHB_DIV_8 02638 * @arg @ref LL_RCC_AHB_DIV_16 02639 * @arg @ref LL_RCC_AHB_DIV_64 02640 * @arg @ref LL_RCC_AHB_DIV_128 02641 * @arg @ref LL_RCC_AHB_DIV_256 02642 * @arg @ref LL_RCC_AHB_DIV_512 02643 */ 02644 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) 02645 { 02646 #if defined(RCC_D1CFGR_HPRE) 02647 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE)); 02648 #else 02649 return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE)); 02650 #endif /* RCC_D1CFGR_HPRE */ 02651 } 02652 02653 /** 02654 * @brief Get APB1 prescaler 02655 * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_GetAPB1Prescaler 02656 * @retval Returned value can be one of the following values: 02657 * @arg @ref LL_RCC_APB1_DIV_1 02658 * @arg @ref LL_RCC_APB1_DIV_2 02659 * @arg @ref LL_RCC_APB1_DIV_4 02660 * @arg @ref LL_RCC_APB1_DIV_8 02661 * @arg @ref LL_RCC_APB1_DIV_16 02662 */ 02663 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) 02664 { 02665 #if defined(RCC_D2CFGR_D2PPRE1) 02666 return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1)); 02667 #else 02668 return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1)); 02669 #endif /* RCC_D2CFGR_D2PPRE1 */ 02670 } 02671 02672 /** 02673 * @brief Get APB2 prescaler 02674 * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_GetAPB2Prescaler 02675 * @retval Returned value can be one of the following values: 02676 * @arg @ref LL_RCC_APB2_DIV_1 02677 * @arg @ref LL_RCC_APB2_DIV_2 02678 * @arg @ref LL_RCC_APB2_DIV_4 02679 * @arg @ref LL_RCC_APB2_DIV_8 02680 * @arg @ref LL_RCC_APB2_DIV_16 02681 */ 02682 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) 02683 { 02684 #if defined(RCC_D2CFGR_D2PPRE2) 02685 return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2)); 02686 #else 02687 return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2)); 02688 #endif /* RCC_D2CFGR_D2PPRE2 */ 02689 } 02690 02691 /** 02692 * @brief Get APB3 prescaler 02693 * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_GetAPB3Prescaler 02694 * @retval Returned value can be one of the following values: 02695 * @arg @ref LL_RCC_APB3_DIV_1 02696 * @arg @ref LL_RCC_APB3_DIV_2 02697 * @arg @ref LL_RCC_APB3_DIV_4 02698 * @arg @ref LL_RCC_APB3_DIV_8 02699 * @arg @ref LL_RCC_APB3_DIV_16 02700 */ 02701 __STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void) 02702 { 02703 #if defined(RCC_D1CFGR_D1PPRE) 02704 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE)); 02705 #else 02706 return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE)); 02707 #endif /* RCC_D1CFGR_D1PPRE */ 02708 } 02709 02710 /** 02711 * @brief Get APB4 prescaler 02712 * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_GetAPB4Prescaler 02713 * @retval Returned value can be one of the following values: 02714 * @arg @ref LL_RCC_APB4_DIV_1 02715 * @arg @ref LL_RCC_APB4_DIV_2 02716 * @arg @ref LL_RCC_APB4_DIV_4 02717 * @arg @ref LL_RCC_APB4_DIV_8 02718 * @arg @ref LL_RCC_APB4_DIV_16 02719 */ 02720 __STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void) 02721 { 02722 #if defined(RCC_D3CFGR_D3PPRE) 02723 return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE)); 02724 #else 02725 return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE)); 02726 #endif /* RCC_D3CFGR_D3PPRE */ 02727 } 02728 02729 /** 02730 * @} 02731 */ 02732 02733 /** @defgroup RCC_LL_EF_MCO MCO 02734 * @{ 02735 */ 02736 02737 /** 02738 * @brief Configure MCOx 02739 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n 02740 * CFGR MCO1PRE LL_RCC_ConfigMCO\n 02741 * CFGR MCO2 LL_RCC_ConfigMCO\n 02742 * CFGR MCO2PRE LL_RCC_ConfigMCO 02743 * @param MCOxSource This parameter can be one of the following values: 02744 * @arg @ref LL_RCC_MCO1SOURCE_HSI 02745 * @arg @ref LL_RCC_MCO1SOURCE_LSE 02746 * @arg @ref LL_RCC_MCO1SOURCE_HSE 02747 * @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK 02748 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 02749 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK 02750 * @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK 02751 * @arg @ref LL_RCC_MCO2SOURCE_HSE 02752 * @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK 02753 * @arg @ref LL_RCC_MCO2SOURCE_CSI 02754 * @arg @ref LL_RCC_MCO2SOURCE_LSI 02755 * @param MCOxPrescaler This parameter can be one of the following values: 02756 * @arg @ref LL_RCC_MCO1_DIV_1 02757 * @arg @ref LL_RCC_MCO1_DIV_2 02758 * @arg @ref LL_RCC_MCO1_DIV_3 02759 * @arg @ref LL_RCC_MCO1_DIV_4 02760 * @arg @ref LL_RCC_MCO1_DIV_5 02761 * @arg @ref LL_RCC_MCO1_DIV_6 02762 * @arg @ref LL_RCC_MCO1_DIV_7 02763 * @arg @ref LL_RCC_MCO1_DIV_8 02764 * @arg @ref LL_RCC_MCO1_DIV_9 02765 * @arg @ref LL_RCC_MCO1_DIV_10 02766 * @arg @ref LL_RCC_MCO1_DIV_11 02767 * @arg @ref LL_RCC_MCO1_DIV_12 02768 * @arg @ref LL_RCC_MCO1_DIV_13 02769 * @arg @ref LL_RCC_MCO1_DIV_14 02770 * @arg @ref LL_RCC_MCO1_DIV_15 02771 * @arg @ref LL_RCC_MCO2_DIV_1 02772 * @arg @ref LL_RCC_MCO2_DIV_2 02773 * @arg @ref LL_RCC_MCO2_DIV_3 02774 * @arg @ref LL_RCC_MCO2_DIV_4 02775 * @arg @ref LL_RCC_MCO2_DIV_5 02776 * @arg @ref LL_RCC_MCO2_DIV_6 02777 * @arg @ref LL_RCC_MCO2_DIV_7 02778 * @arg @ref LL_RCC_MCO2_DIV_8 02779 * @arg @ref LL_RCC_MCO2_DIV_9 02780 * @arg @ref LL_RCC_MCO2_DIV_10 02781 * @arg @ref LL_RCC_MCO2_DIV_11 02782 * @arg @ref LL_RCC_MCO2_DIV_12 02783 * @arg @ref LL_RCC_MCO2_DIV_13 02784 * @arg @ref LL_RCC_MCO2_DIV_14 02785 * @arg @ref LL_RCC_MCO2_DIV_15 02786 * @retval None 02787 */ 02788 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) 02789 { 02790 MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U)); 02791 } 02792 02793 /** 02794 * @} 02795 */ 02796 02797 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source 02798 * @{ 02799 */ 02800 02801 /** 02802 * @brief Configure periph clock source 02803 * @rmtoll D2CCIP1R/CDCCIP1R * LL_RCC_SetClockSource\n 02804 * D2CCIP2R/CDCCIP2R * LL_RCC_SetClockSource\n 02805 * D3CCIPR/SRDCCIPR * LL_RCC_SetClockSource 02806 * @param ClkSource This parameter can be one of the following values: 02807 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 02808 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q 02809 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q 02810 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI 02811 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI 02812 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE 02813 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 02814 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q 02815 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q 02816 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI 02817 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI 02818 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE 02819 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 02820 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R 02821 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI 02822 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI 02823 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 02824 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R 02825 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI 02826 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI 02827 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 02828 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P 02829 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R 02830 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 02831 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 02832 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP 02833 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 02834 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P 02835 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R 02836 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE 02837 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI 02838 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP 02839 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 02840 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P 02841 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R 02842 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE 02843 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI 02844 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP 02845 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q 02846 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P 02847 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P 02848 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN 02849 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP 02850 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) 02851 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) 02852 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) 02853 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) 02854 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) 02855 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) 02856 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) 02857 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) 02858 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) 02859 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*) 02860 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) 02861 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) 02862 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) 02863 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) 02864 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) 02865 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*) 02866 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) 02867 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) 02868 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) 02869 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) 02870 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) 02871 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*) 02872 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) 02873 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) 02874 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) 02875 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) 02876 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) 02877 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) 02878 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q 02879 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P 02880 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P 02881 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN 02882 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP 02883 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 02884 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q 02885 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q 02886 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI 02887 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI 02888 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE 02889 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 02890 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q 02891 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q 02892 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI 02893 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI 02894 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE 02895 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) 02896 * 02897 * (*) value not defined in all devices. 02898 * @retval None 02899 */ 02900 __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource) 02901 { 02902 #if defined(RCC_D1CCIPR_FMCSEL) 02903 uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource)); 02904 #else 02905 uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource)); 02906 #endif /* */ 02907 MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource)); 02908 } 02909 02910 /** 02911 * @brief Configure USARTx clock source 02912 * @rmtoll D2CCIP2R / D2CCIP2R USART16SEL LL_RCC_SetUSARTClockSource\n 02913 * D2CCIP2R / D2CCIP2R USART28SEL LL_RCC_SetUSARTClockSource 02914 * @param ClkSource This parameter can be one of the following values: 02915 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 02916 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q 02917 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q 02918 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI 02919 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI 02920 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE 02921 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 02922 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q 02923 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q 02924 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI 02925 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI 02926 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE 02927 * @retval None 02928 */ 02929 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource) 02930 { 02931 LL_RCC_SetClockSource(ClkSource); 02932 } 02933 02934 /** 02935 * @brief Configure LPUARTx clock source 02936 * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource 02937 * @param ClkSource This parameter can be one of the following values: 02938 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4 02939 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q 02940 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q 02941 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI 02942 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI 02943 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE 02944 * @retval None 02945 */ 02946 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource) 02947 { 02948 #if defined(RCC_D3CCIPR_LPUART1SEL) 02949 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource); 02950 #else 02951 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource); 02952 #endif /* RCC_D3CCIPR_LPUART1SEL */ 02953 } 02954 02955 /** 02956 * @brief Configure I2Cx clock source 02957 * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_SetI2CClockSource\n 02958 * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_SetI2CClockSource 02959 * @param ClkSource This parameter can be one of the following values: 02960 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 02961 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R 02962 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI 02963 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI 02964 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 02965 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R 02966 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI 02967 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI 02968 * @retval None 02969 */ 02970 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource) 02971 { 02972 LL_RCC_SetClockSource(ClkSource); 02973 } 02974 02975 /** 02976 * @brief Configure LPTIMx clock source 02977 * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_SetLPTIMClockSource 02978 * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_SetLPTIMClockSource\n 02979 * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_SetLPTIMClockSource 02980 * @param ClkSource This parameter can be one of the following values: 02981 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 02982 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P 02983 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R 02984 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 02985 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 02986 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP 02987 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 02988 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P 02989 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R 02990 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE 02991 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI 02992 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP 02993 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 02994 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P 02995 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R 02996 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE 02997 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI 02998 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP 02999 * @retval None 03000 */ 03001 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource) 03002 { 03003 LL_RCC_SetClockSource(ClkSource); 03004 } 03005 03006 /** 03007 * @brief Configure SAIx clock source 03008 * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_SetSAIClockSource\n 03009 * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_SetSAIClockSource 03010 * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_SetSAI4xClockSource\n 03011 * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_SetSAI4xClockSource 03012 * @param ClkSource This parameter can be one of the following values: 03013 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q 03014 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P 03015 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P 03016 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN 03017 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP 03018 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) 03019 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) 03020 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) 03021 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) 03022 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) 03023 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) 03024 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) 03025 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) 03026 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) 03027 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*) 03028 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) 03029 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) 03030 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) 03031 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) 03032 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) 03033 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*) 03034 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) 03035 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) 03036 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) 03037 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) 03038 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) 03039 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*) 03040 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) 03041 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) 03042 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) 03043 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) 03044 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) 03045 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) 03046 * 03047 * (*) value not defined in all devices. 03048 * @retval None 03049 */ 03050 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource) 03051 { 03052 LL_RCC_SetClockSource(ClkSource); 03053 } 03054 03055 /** 03056 * @brief Configure SDMMCx clock source 03057 * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_SetSDMMCClockSource 03058 * @param ClkSource This parameter can be one of the following values: 03059 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q 03060 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R 03061 * @retval None 03062 */ 03063 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource) 03064 { 03065 #if defined(RCC_D1CCIPR_SDMMCSEL) 03066 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource); 03067 #else 03068 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource); 03069 #endif /* RCC_D1CCIPR_SDMMCSEL */ 03070 } 03071 03072 /** 03073 * @brief Configure RNGx clock source 03074 * @rmtoll D2CCIP2R / CDCCIP2R RNGSEL LL_RCC_SetRNGClockSource 03075 * @param ClkSource This parameter can be one of the following values: 03076 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 03077 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q 03078 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE 03079 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI 03080 * @retval None 03081 */ 03082 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource) 03083 { 03084 #if defined(RCC_D2CCIP2R_RNGSEL) 03085 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource); 03086 #else 03087 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource); 03088 #endif /* RCC_D2CCIP2R_RNGSEL */ 03089 } 03090 03091 /** 03092 * @brief Configure USBx clock source 03093 * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_SetUSBClockSource 03094 * @param ClkSource This parameter can be one of the following values: 03095 * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE 03096 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q 03097 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q 03098 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 03099 * @retval None 03100 */ 03101 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource) 03102 { 03103 #if defined(RCC_D2CCIP2R_USBSEL) 03104 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource); 03105 #else 03106 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource); 03107 #endif /* RCC_D2CCIP2R_USBSEL */ 03108 } 03109 03110 /** 03111 * @brief Configure CECx clock source 03112 * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_SetCECClockSource 03113 * @param ClkSource This parameter can be one of the following values: 03114 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE 03115 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI 03116 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122 03117 * @retval None 03118 */ 03119 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource) 03120 { 03121 #if defined(RCC_D2CCIP2R_CECSEL) 03122 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource); 03123 #else 03124 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource); 03125 #endif /* RCC_D2CCIP2R_CECSEL */ 03126 } 03127 03128 #if defined(DSI) 03129 /** 03130 * @brief Configure DSIx clock source 03131 * @rmtoll D1CCIPR DSISEL LL_RCC_SetDSIClockSource 03132 * @param ClkSource This parameter can be one of the following values: 03133 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY 03134 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q 03135 * @retval None 03136 */ 03137 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource) 03138 { 03139 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource); 03140 } 03141 #endif /* DSI */ 03142 03143 /** 03144 * @brief Configure DFSDMx Kernel clock source 03145 * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_SetDFSDMClockSource 03146 * @param ClkSource This parameter can be one of the following values: 03147 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 03148 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 03149 * @retval None 03150 */ 03151 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource) 03152 { 03153 #if defined(RCC_D2CCIP1R_DFSDM1SEL) 03154 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource); 03155 #else 03156 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource); 03157 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 03158 } 03159 03160 #if defined(DFSDM2_BASE) 03161 /** 03162 * @brief Configure DFSDMx Kernel clock source 03163 * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_SetDFSDM2ClockSource 03164 * @param ClkSource This parameter can be one of the following values: 03165 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4 03166 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK 03167 * @retval None 03168 */ 03169 __STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource) 03170 { 03171 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource); 03172 } 03173 #endif /* DFSDM2_BASE */ 03174 03175 /** 03176 * @brief Configure FMCx Kernel clock source 03177 * @rmtoll D1CCIPR / CDCCIPR FMCSEL LL_RCC_SetFMCClockSource 03178 * @param ClkSource This parameter can be one of the following values: 03179 * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK 03180 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q 03181 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R 03182 * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP 03183 * @retval None 03184 */ 03185 __STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource) 03186 { 03187 #if defined(RCC_D1CCIPR_FMCSEL) 03188 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource); 03189 #else 03190 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource); 03191 #endif /* RCC_D1CCIPR_FMCSEL */ 03192 } 03193 03194 #if defined(QUADSPI) 03195 /** 03196 * @brief Configure QSPIx Kernel clock source 03197 * @rmtoll D1CCIPR QSPISEL LL_RCC_SetQSPIClockSource 03198 * @param ClkSource This parameter can be one of the following values: 03199 * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK 03200 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q 03201 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R 03202 * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP 03203 * @retval None 03204 */ 03205 __STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource) 03206 { 03207 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource); 03208 } 03209 #endif /* QUADSPI */ 03210 03211 #if defined(OCTOSPI1) || defined(OCTOSPI2) 03212 /** 03213 * @brief Configure OSPIx Kernel clock source 03214 * @rmtoll D1CCIPR OPISEL LL_RCC_SetOSPIClockSource 03215 * @param ClkSource This parameter can be one of the following values: 03216 * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK 03217 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q 03218 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R 03219 * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP 03220 * @retval None 03221 */ 03222 __STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource) 03223 { 03224 #if defined(RCC_D1CCIPR_OCTOSPISEL) 03225 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, ClkSource); 03226 #else 03227 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource); 03228 #endif /* RCC_D1CCIPR_OCTOSPISEL */ 03229 } 03230 #endif /* OCTOSPI1 || OCTOSPI2 */ 03231 03232 /** 03233 * @brief Configure CLKP Kernel clock source 03234 * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_SetCLKPClockSource 03235 * @param ClkSource This parameter can be one of the following values: 03236 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI 03237 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI 03238 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE 03239 * @retval None 03240 */ 03241 __STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource) 03242 { 03243 #if defined(RCC_D1CCIPR_CKPERSEL) 03244 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource); 03245 #else 03246 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource); 03247 #endif /* RCC_D1CCIPR_CKPERSEL */ 03248 } 03249 03250 /** 03251 * @brief Configure SPIx Kernel clock source 03252 * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_SetSPIClockSource\n 03253 * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_SetSPIClockSource\n 03254 * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_SetSPIClockSource 03255 * @param ClkSource This parameter can be one of the following values: 03256 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q 03257 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P 03258 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P 03259 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN 03260 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP 03261 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 03262 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q 03263 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q 03264 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI 03265 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI 03266 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE 03267 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 03268 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q 03269 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q 03270 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI 03271 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI 03272 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE 03273 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) 03274 * 03275 * (*) value not defined in all devices. 03276 * @retval None 03277 */ 03278 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource) 03279 { 03280 LL_RCC_SetClockSource(ClkSource); 03281 } 03282 03283 /** 03284 * @brief Configure SPDIFx Kernel clock source 03285 * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_SetSPDIFClockSource 03286 * @param ClkSource This parameter can be one of the following values: 03287 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q 03288 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R 03289 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R 03290 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI 03291 * @retval None 03292 */ 03293 __STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource) 03294 { 03295 #if defined(RCC_D2CCIP1R_SPDIFSEL) 03296 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource); 03297 #else 03298 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource); 03299 #endif /* RCC_D2CCIP1R_SPDIFSEL */ 03300 } 03301 03302 /** 03303 * @brief Configure FDCANx Kernel clock source 03304 * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_SetFDCANClockSource 03305 * @param ClkSource This parameter can be one of the following values: 03306 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE 03307 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q 03308 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q 03309 * @retval None 03310 */ 03311 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource) 03312 { 03313 #if defined(RCC_D2CCIP1R_FDCANSEL) 03314 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource); 03315 #else 03316 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource); 03317 #endif /* RCC_D2CCIP1R_FDCANSEL */ 03318 } 03319 03320 /** 03321 * @brief Configure SWPx Kernel clock source 03322 * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_SetSWPClockSource 03323 * @param ClkSource This parameter can be one of the following values: 03324 * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1 03325 * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI 03326 * @retval None 03327 */ 03328 __STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource) 03329 { 03330 #if defined(RCC_D2CCIP1R_SWPSEL) 03331 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource); 03332 #else 03333 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource); 03334 #endif /* RCC_D2CCIP1R_SWPSEL */ 03335 } 03336 03337 /** 03338 * @brief Configure ADCx Kernel clock source 03339 * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_SetADCClockSource 03340 * @param ClkSource This parameter can be one of the following values: 03341 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P 03342 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R 03343 * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP 03344 * @retval None 03345 */ 03346 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource) 03347 { 03348 #if defined(RCC_D3CCIPR_ADCSEL) 03349 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource); 03350 #else 03351 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource); 03352 #endif /* RCC_D3CCIPR_ADCSEL */ 03353 } 03354 03355 /** 03356 * @brief Get periph clock source 03357 * @rmtoll D1CCIPR / CDCCIPR * LL_RCC_GetClockSource\n 03358 * D2CCIP1R / CDCCIP1R * LL_RCC_GetClockSource\n 03359 * D2CCIP2R / CDCCIP2R * LL_RCC_GetClockSource\n 03360 * D3CCIPR / SRDCCIPR * LL_RCC_GetClockSource 03361 * @param Periph This parameter can be one of the following values: 03362 * @arg @ref LL_RCC_USART16_CLKSOURCE 03363 * @arg @ref LL_RCC_USART234578_CLKSOURCE 03364 * @arg @ref LL_RCC_I2C123_CLKSOURCE 03365 * @arg @ref LL_RCC_I2C4_CLKSOURCE 03366 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE 03367 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE 03368 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE 03369 * @arg @ref LL_RCC_SAI1_CLKSOURCE 03370 * @arg @ref LL_RCC_SAI23_CLKSOURCE 03371 * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*) 03372 * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*) 03373 * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*) 03374 * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*) 03375 * @arg @ref LL_RCC_SPI123_CLKSOURCE (*) 03376 * @arg @ref LL_RCC_SPI45_CLKSOURCE (*) 03377 * @arg @ref LL_RCC_SPI6_CLKSOURCE (*) 03378 * @retval Returned value can be one of the following values: 03379 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 03380 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q 03381 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q 03382 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI 03383 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI 03384 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE 03385 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 03386 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q 03387 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q 03388 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI 03389 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI 03390 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE 03391 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 03392 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R 03393 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI 03394 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI 03395 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 03396 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R 03397 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI 03398 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI 03399 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 03400 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P 03401 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R 03402 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 03403 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 03404 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP 03405 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 03406 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P 03407 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R 03408 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE 03409 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI 03410 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP 03411 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 03412 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P 03413 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R 03414 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE 03415 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI 03416 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP 03417 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q 03418 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P 03419 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P 03420 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN 03421 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP 03422 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) 03423 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) 03424 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) 03425 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) 03426 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) 03427 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) 03428 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) 03429 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) 03430 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) 03431 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*) 03432 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) 03433 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) 03434 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) 03435 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) 03436 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) 03437 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) 03438 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) 03439 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) 03440 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) 03441 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) 03442 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) 03443 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) 03444 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) 03445 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) 03446 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) 03447 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) 03448 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) 03449 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q 03450 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P 03451 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P 03452 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN 03453 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP 03454 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 03455 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q 03456 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q 03457 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI 03458 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI 03459 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE 03460 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 03461 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q 03462 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q 03463 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI 03464 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI 03465 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE 03466 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) 03467 * 03468 * (*) value not defined in all devices. 03469 * @retval None 03470 */ 03471 __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph) 03472 { 03473 #if defined(RCC_D1CCIPR_FMCSEL) 03474 const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph))); 03475 #else 03476 const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph))); 03477 #endif /* RCC_D1CCIPR_FMCSEL */ 03478 return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) ); 03479 } 03480 03481 /** 03482 * @brief Get USARTx clock source 03483 * @rmtoll D2CCIP2R / CDCCIP2R USART16SEL LL_RCC_GetUSARTClockSource\n 03484 * D2CCIP2R / CDCCIP2R USART28SEL LL_RCC_GetUSARTClockSource 03485 * @param Periph This parameter can be one of the following values: 03486 * @arg @ref LL_RCC_USART16_CLKSOURCE 03487 * @arg @ref LL_RCC_USART234578_CLKSOURCE 03488 * @retval Returned value can be one of the following values: 03489 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 03490 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q 03491 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q 03492 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI 03493 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI 03494 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE 03495 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 03496 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q 03497 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q 03498 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI 03499 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI 03500 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE 03501 */ 03502 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph) 03503 { 03504 return LL_RCC_GetClockSource(Periph); 03505 } 03506 03507 /** 03508 * @brief Get LPUART clock source 03509 * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource 03510 * @param Periph This parameter can be one of the following values: 03511 * @arg @ref LL_RCC_LPUART1_CLKSOURCE 03512 * @retval Returned value can be one of the following values: 03513 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4 03514 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q 03515 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q 03516 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI 03517 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI 03518 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE 03519 */ 03520 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph) 03521 { 03522 UNUSED(Periph); 03523 #if defined(RCC_D3CCIPR_LPUART1SEL) 03524 return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)); 03525 #else 03526 return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)); 03527 #endif /* RCC_D3CCIPR_LPUART1SEL */ 03528 } 03529 03530 /** 03531 * @brief Get I2Cx clock source 03532 * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_GetI2CClockSource\n 03533 * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_GetI2CClockSource 03534 * @param Periph This parameter can be one of the following values: 03535 * @arg @ref LL_RCC_I2C123_CLKSOURCE 03536 * @arg @ref LL_RCC_I2C4_CLKSOURCE 03537 * @retval Returned value can be one of the following values: 03538 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 03539 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R 03540 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI 03541 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI 03542 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 03543 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R 03544 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI 03545 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI 03546 */ 03547 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph) 03548 { 03549 return LL_RCC_GetClockSource(Periph); 03550 } 03551 03552 /** 03553 * @brief Get LPTIM clock source 03554 * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_GetLPTIMClockSource\n 03555 * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource\n 03556 * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_GetLPTIMClockSource 03557 * @param Periph This parameter can be one of the following values: 03558 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE 03559 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE 03560 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE 03561 * @retval Returned value can be one of the following values: 03562 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 03563 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P 03564 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R 03565 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 03566 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 03567 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP 03568 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 03569 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P 03570 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R 03571 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE 03572 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI 03573 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP 03574 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 03575 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P 03576 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R 03577 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE 03578 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI 03579 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP 03580 * @retval None 03581 */ 03582 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph) 03583 { 03584 return LL_RCC_GetClockSource(Periph); 03585 } 03586 03587 /** 03588 * @brief Get SAIx clock source 03589 * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_GetSAIClockSource\n 03590 * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_GetSAIClockSource 03591 * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_GetSAIClockSource\n 03592 * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_GetSAIClockSource 03593 * @param Periph This parameter can be one of the following values: 03594 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) 03595 * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*) 03596 * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*) 03597 * @arg @ref LL_RCC_SAI23_CLKSOURCE (*) 03598 * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*) 03599 * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*) 03600 * @retval Returned value can be one of the following values: 03601 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q 03602 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P 03603 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P 03604 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN 03605 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP 03606 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) 03607 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) 03608 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) 03609 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) 03610 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) 03611 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) 03612 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) 03613 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) 03614 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) 03615 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) 03616 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*) 03617 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) 03618 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) 03619 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) 03620 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) 03621 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) 03622 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) 03623 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) 03624 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) 03625 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) 03626 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) 03627 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*) 03628 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) 03629 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) 03630 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) 03631 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) 03632 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) 03633 * 03634 * (*) value not defined in all devices. 03635 */ 03636 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph) 03637 { 03638 return LL_RCC_GetClockSource(Periph); 03639 } 03640 03641 /** 03642 * @brief Get SDMMC clock source 03643 * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_GetSDMMCClockSource 03644 * @param Periph This parameter can be one of the following values: 03645 * @arg @ref LL_RCC_SDMMC_CLKSOURCE 03646 * @retval Returned value can be one of the following values: 03647 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q 03648 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R 03649 */ 03650 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph) 03651 { 03652 UNUSED(Periph); 03653 #if defined(RCC_D1CCIPR_SDMMCSEL) 03654 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)); 03655 #else 03656 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)); 03657 #endif /* RCC_D1CCIPR_SDMMCSEL */ 03658 } 03659 03660 /** 03661 * @brief Get RNG clock source 03662 * @rmtoll D2CCIP2R RNGSEL LL_RCC_GetRNGClockSource 03663 * @param Periph This parameter can be one of the following values: 03664 * @arg @ref LL_RCC_RNG_CLKSOURCE 03665 * @retval Returned value can be one of the following values: 03666 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 03667 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q 03668 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE 03669 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI 03670 */ 03671 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph) 03672 { 03673 UNUSED(Periph); 03674 #if defined(RCC_D2CCIP2R_RNGSEL) 03675 return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)); 03676 #else 03677 return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)); 03678 #endif /* RCC_D2CCIP2R_RNGSEL */ 03679 } 03680 03681 /** 03682 * @brief Get USB clock source 03683 * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_GetUSBClockSource 03684 * @param Periph This parameter can be one of the following values: 03685 * @arg @ref LL_RCC_USB_CLKSOURCE 03686 * @retval Returned value can be one of the following values: 03687 * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE 03688 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q 03689 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q 03690 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 03691 */ 03692 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph) 03693 { 03694 UNUSED(Periph); 03695 #if defined(RCC_D2CCIP2R_USBSEL) 03696 return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)); 03697 #else 03698 return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)); 03699 #endif /* RCC_D2CCIP2R_USBSEL */ 03700 } 03701 03702 /** 03703 * @brief Get CEC clock source 03704 * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_GetCECClockSource 03705 * @param Periph This parameter can be one of the following values: 03706 * @arg @ref LL_RCC_CEC_CLKSOURCE 03707 * @retval Returned value can be one of the following values: 03708 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE 03709 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI 03710 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122 03711 */ 03712 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph) 03713 { 03714 UNUSED(Periph); 03715 #if defined(RCC_D2CCIP2R_CECSEL) 03716 return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)); 03717 #else 03718 return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)); 03719 #endif /* RCC_D2CCIP2R_CECSEL */ 03720 } 03721 03722 #if defined(DSI) 03723 /** 03724 * @brief Get DSI clock source 03725 * @rmtoll D1CCIPR DSISEL LL_RCC_GetDSIClockSource 03726 * @param Periph This parameter can be one of the following values: 03727 * @arg @ref LL_RCC_DSI_CLKSOURCE 03728 * @retval Returned value can be one of the following values: 03729 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY 03730 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q 03731 */ 03732 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph) 03733 { 03734 UNUSED(Periph); 03735 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)); 03736 } 03737 #endif /* DSI */ 03738 03739 /** 03740 * @brief Get DFSDM Kernel clock source 03741 * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_GetDFSDMClockSource 03742 * @param Periph This parameter can be one of the following values: 03743 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE 03744 * @retval Returned value can be one of the following values: 03745 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 03746 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 03747 */ 03748 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph) 03749 { 03750 UNUSED(Periph); 03751 #if defined(RCC_D2CCIP1R_DFSDM1SEL) 03752 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)); 03753 #else 03754 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)); 03755 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 03756 } 03757 03758 #if defined(DFSDM2_BASE) 03759 /** 03760 * @brief Get DFSDM2 Kernel clock source 03761 * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_GetDFSDM2ClockSource 03762 * @param Periph This parameter can be one of the following values: 03763 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE 03764 * @retval Returned value can be one of the following values: 03765 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4 03766 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK 03767 */ 03768 __STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph) 03769 { 03770 UNUSED(Periph); 03771 return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)); 03772 } 03773 #endif /* DFSDM2_BASE */ 03774 03775 /** 03776 * @brief Get FMC Kernel clock source 03777 * @rmtoll D1CCIPR / D1CCIPR FMCSEL LL_RCC_GetFMCClockSource 03778 * @param Periph This parameter can be one of the following values: 03779 * @arg @ref LL_RCC_FMC_CLKSOURCE 03780 * @retval Returned value can be one of the following values: 03781 * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK 03782 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q 03783 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R 03784 * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP 03785 */ 03786 __STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph) 03787 { 03788 UNUSED(Periph); 03789 #if defined(RCC_D1CCIPR_FMCSEL) 03790 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)); 03791 #else 03792 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)); 03793 #endif /* RCC_D1CCIPR_FMCSEL */ 03794 } 03795 03796 #if defined(QUADSPI) 03797 /** 03798 * @brief Get QSPI Kernel clock source 03799 * @rmtoll D1CCIPR / CDCCIPR QSPISEL LL_RCC_GetQSPIClockSource 03800 * @param Periph This parameter can be one of the following values: 03801 * @arg @ref LL_RCC_QSPI_CLKSOURCE 03802 * @retval Returned value can be one of the following values: 03803 * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK 03804 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q 03805 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R 03806 * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP 03807 */ 03808 __STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph) 03809 { 03810 UNUSED(Periph); 03811 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)); 03812 } 03813 #endif /* QUADSPI */ 03814 03815 #if defined(OCTOSPI1) || defined(OCTOSPI2) 03816 /** 03817 * @brief Get OSPI Kernel clock source 03818 * @rmtoll CDCCIPR OSPISEL LL_RCC_GetOSPIClockSource 03819 * @param Periph This parameter can be one of the following values: 03820 * @arg @ref LL_RCC_OSPI_CLKSOURCE 03821 * @retval Returned value can be one of the following values: 03822 * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK 03823 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q 03824 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R 03825 * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP 03826 */ 03827 __STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph) 03828 { 03829 UNUSED(Periph); 03830 #if defined(RCC_D1CCIPR_OCTOSPISEL) 03831 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL)); 03832 #else 03833 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)); 03834 #endif /* RCC_D1CCIPR_OCTOSPISEL */ 03835 } 03836 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ 03837 03838 /** 03839 * @brief Get CLKP Kernel clock source 03840 * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_GetCLKPClockSource 03841 * @param Periph This parameter can be one of the following values: 03842 * @arg @ref LL_RCC_CLKP_CLKSOURCE 03843 * @retval Returned value can be one of the following values: 03844 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI 03845 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI 03846 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE 03847 */ 03848 __STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph) 03849 { 03850 UNUSED(Periph); 03851 #if defined(RCC_D1CCIPR_CKPERSEL) 03852 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)); 03853 #else 03854 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)); 03855 #endif /* RCC_D1CCIPR_CKPERSEL */ 03856 } 03857 03858 /** 03859 * @brief Get SPIx Kernel clock source 03860 * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_GetSPIClockSource\n 03861 * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_GetSPIClockSource\n 03862 * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_GetSPIClockSource 03863 * @param Periph This parameter can be one of the following values: 03864 * @arg @ref LL_RCC_SPI123_CLKSOURCE 03865 * @arg @ref LL_RCC_SPI45_CLKSOURCE 03866 * @arg @ref LL_RCC_SPI6_CLKSOURCE 03867 * @retval Returned value can be one of the following values: 03868 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q 03869 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P 03870 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P 03871 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN 03872 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP 03873 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 03874 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q 03875 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q 03876 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI 03877 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI 03878 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE 03879 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 03880 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q 03881 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q 03882 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI 03883 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI 03884 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE 03885 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) 03886 * 03887 * (*) value not defined in all stm32h7xx lines. 03888 */ 03889 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph) 03890 { 03891 return LL_RCC_GetClockSource(Periph); 03892 } 03893 03894 /** 03895 * @brief Get SPDIF Kernel clock source 03896 * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_GetSPDIFClockSource 03897 * @param Periph This parameter can be one of the following values: 03898 * @arg @ref LL_RCC_SPDIF_CLKSOURCE 03899 * @retval Returned value can be one of the following values: 03900 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q 03901 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R 03902 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R 03903 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI 03904 */ 03905 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph) 03906 { 03907 UNUSED(Periph); 03908 #if defined(RCC_D2CCIP1R_SPDIFSEL) 03909 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)); 03910 #else 03911 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)); 03912 #endif /* RCC_D2CCIP1R_SPDIFSEL */ 03913 } 03914 03915 /** 03916 * @brief Get FDCAN Kernel clock source 03917 * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_GetFDCANClockSource 03918 * @param Periph This parameter can be one of the following values: 03919 * @arg @ref LL_RCC_FDCAN_CLKSOURCE 03920 * @retval Returned value can be one of the following values: 03921 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE 03922 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q 03923 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q 03924 */ 03925 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph) 03926 { 03927 UNUSED(Periph); 03928 #if defined(RCC_D2CCIP1R_FDCANSEL) 03929 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)); 03930 #else 03931 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)); 03932 #endif /* RCC_D2CCIP1R_FDCANSEL */ 03933 } 03934 03935 /** 03936 * @brief Get SWP Kernel clock source 03937 * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_GetSWPClockSource 03938 * @param Periph This parameter can be one of the following values: 03939 * @arg @ref LL_RCC_SWP_CLKSOURCE 03940 * @retval Returned value can be one of the following values: 03941 * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1 03942 * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI 03943 */ 03944 __STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph) 03945 { 03946 UNUSED(Periph); 03947 #if defined(RCC_D2CCIP1R_SWPSEL) 03948 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)); 03949 #else 03950 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)); 03951 #endif /* RCC_D2CCIP1R_SWPSEL */ 03952 } 03953 03954 /** 03955 * @brief Get ADC Kernel clock source 03956 * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_GetADCClockSource 03957 * @param Periph This parameter can be one of the following values: 03958 * @arg @ref LL_RCC_ADC_CLKSOURCE 03959 * @retval Returned value can be one of the following values: 03960 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P 03961 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R 03962 * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP 03963 */ 03964 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph) 03965 { 03966 UNUSED(Periph); 03967 #if defined (RCC_D3CCIPR_ADCSEL) 03968 return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)); 03969 #else 03970 return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)); 03971 #endif /* RCC_D3CCIPR_ADCSEL */ 03972 } 03973 03974 /** 03975 * @} 03976 */ 03977 03978 /** @defgroup RCC_LL_EF_RTC RTC 03979 * @{ 03980 */ 03981 03982 /** 03983 * @brief Set RTC Clock Source 03984 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless 03985 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is 03986 * set). The BDRST bit can be used to reset them. 03987 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource 03988 * @param Source This parameter can be one of the following values: 03989 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 03990 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 03991 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 03992 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE 03993 * @retval None 03994 */ 03995 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) 03996 { 03997 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); 03998 } 03999 04000 /** 04001 * @brief Get RTC Clock Source 04002 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource 04003 * @retval Returned value can be one of the following values: 04004 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 04005 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 04006 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 04007 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE 04008 */ 04009 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) 04010 { 04011 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); 04012 } 04013 04014 /** 04015 * @brief Enable RTC 04016 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC 04017 * @retval None 04018 */ 04019 __STATIC_INLINE void LL_RCC_EnableRTC(void) 04020 { 04021 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 04022 } 04023 04024 /** 04025 * @brief Disable RTC 04026 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC 04027 * @retval None 04028 */ 04029 __STATIC_INLINE void LL_RCC_DisableRTC(void) 04030 { 04031 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 04032 } 04033 04034 /** 04035 * @brief Check if RTC has been enabled or not 04036 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC 04037 * @retval State of bit (1 or 0). 04038 */ 04039 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) 04040 { 04041 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN))?1UL:0UL); 04042 } 04043 04044 /** 04045 * @brief Force the Backup domain reset 04046 * @rmtoll BDCR BDRST / VSWRST LL_RCC_ForceBackupDomainReset 04047 * @retval None 04048 */ 04049 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) 04050 { 04051 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); 04052 } 04053 04054 /** 04055 * @brief Release the Backup domain reset 04056 * @rmtoll BDCR BDRST / VSWRST LL_RCC_ReleaseBackupDomainReset 04057 * @retval None 04058 */ 04059 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) 04060 { 04061 #if defined(RCC_BDCR_BDRST) 04062 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); 04063 #else 04064 CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST); 04065 #endif /* RCC_BDCR_BDRST */ 04066 } 04067 04068 /** 04069 * @brief Set HSE Prescalers for RTC Clock 04070 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler 04071 * @param Prescaler This parameter can be one of the following values: 04072 * @arg @ref LL_RCC_RTC_NOCLOCK 04073 * @arg @ref LL_RCC_RTC_HSE_DIV_2 04074 * @arg @ref LL_RCC_RTC_HSE_DIV_3 04075 * @arg @ref LL_RCC_RTC_HSE_DIV_4 04076 * @arg @ref LL_RCC_RTC_HSE_DIV_5 04077 * @arg @ref LL_RCC_RTC_HSE_DIV_6 04078 * @arg @ref LL_RCC_RTC_HSE_DIV_7 04079 * @arg @ref LL_RCC_RTC_HSE_DIV_8 04080 * @arg @ref LL_RCC_RTC_HSE_DIV_9 04081 * @arg @ref LL_RCC_RTC_HSE_DIV_10 04082 * @arg @ref LL_RCC_RTC_HSE_DIV_11 04083 * @arg @ref LL_RCC_RTC_HSE_DIV_12 04084 * @arg @ref LL_RCC_RTC_HSE_DIV_13 04085 * @arg @ref LL_RCC_RTC_HSE_DIV_14 04086 * @arg @ref LL_RCC_RTC_HSE_DIV_15 04087 * @arg @ref LL_RCC_RTC_HSE_DIV_16 04088 * @arg @ref LL_RCC_RTC_HSE_DIV_17 04089 * @arg @ref LL_RCC_RTC_HSE_DIV_18 04090 * @arg @ref LL_RCC_RTC_HSE_DIV_19 04091 * @arg @ref LL_RCC_RTC_HSE_DIV_20 04092 * @arg @ref LL_RCC_RTC_HSE_DIV_21 04093 * @arg @ref LL_RCC_RTC_HSE_DIV_22 04094 * @arg @ref LL_RCC_RTC_HSE_DIV_23 04095 * @arg @ref LL_RCC_RTC_HSE_DIV_24 04096 * @arg @ref LL_RCC_RTC_HSE_DIV_25 04097 * @arg @ref LL_RCC_RTC_HSE_DIV_26 04098 * @arg @ref LL_RCC_RTC_HSE_DIV_27 04099 * @arg @ref LL_RCC_RTC_HSE_DIV_28 04100 * @arg @ref LL_RCC_RTC_HSE_DIV_29 04101 * @arg @ref LL_RCC_RTC_HSE_DIV_30 04102 * @arg @ref LL_RCC_RTC_HSE_DIV_31 04103 * @arg @ref LL_RCC_RTC_HSE_DIV_32 04104 * @arg @ref LL_RCC_RTC_HSE_DIV_33 04105 * @arg @ref LL_RCC_RTC_HSE_DIV_34 04106 * @arg @ref LL_RCC_RTC_HSE_DIV_35 04107 * @arg @ref LL_RCC_RTC_HSE_DIV_36 04108 * @arg @ref LL_RCC_RTC_HSE_DIV_37 04109 * @arg @ref LL_RCC_RTC_HSE_DIV_38 04110 * @arg @ref LL_RCC_RTC_HSE_DIV_39 04111 * @arg @ref LL_RCC_RTC_HSE_DIV_40 04112 * @arg @ref LL_RCC_RTC_HSE_DIV_41 04113 * @arg @ref LL_RCC_RTC_HSE_DIV_42 04114 * @arg @ref LL_RCC_RTC_HSE_DIV_43 04115 * @arg @ref LL_RCC_RTC_HSE_DIV_44 04116 * @arg @ref LL_RCC_RTC_HSE_DIV_45 04117 * @arg @ref LL_RCC_RTC_HSE_DIV_46 04118 * @arg @ref LL_RCC_RTC_HSE_DIV_47 04119 * @arg @ref LL_RCC_RTC_HSE_DIV_48 04120 * @arg @ref LL_RCC_RTC_HSE_DIV_49 04121 * @arg @ref LL_RCC_RTC_HSE_DIV_50 04122 * @arg @ref LL_RCC_RTC_HSE_DIV_51 04123 * @arg @ref LL_RCC_RTC_HSE_DIV_52 04124 * @arg @ref LL_RCC_RTC_HSE_DIV_53 04125 * @arg @ref LL_RCC_RTC_HSE_DIV_54 04126 * @arg @ref LL_RCC_RTC_HSE_DIV_55 04127 * @arg @ref LL_RCC_RTC_HSE_DIV_56 04128 * @arg @ref LL_RCC_RTC_HSE_DIV_57 04129 * @arg @ref LL_RCC_RTC_HSE_DIV_58 04130 * @arg @ref LL_RCC_RTC_HSE_DIV_59 04131 * @arg @ref LL_RCC_RTC_HSE_DIV_60 04132 * @arg @ref LL_RCC_RTC_HSE_DIV_61 04133 * @arg @ref LL_RCC_RTC_HSE_DIV_62 04134 * @arg @ref LL_RCC_RTC_HSE_DIV_63 04135 * @retval None 04136 */ 04137 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) 04138 { 04139 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); 04140 } 04141 04142 /** 04143 * @brief Get HSE Prescalers for RTC Clock 04144 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler 04145 * @retval Returned value can be one of the following values: 04146 * @arg @ref LL_RCC_RTC_NOCLOCK 04147 * @arg @ref LL_RCC_RTC_HSE_DIV_2 04148 * @arg @ref LL_RCC_RTC_HSE_DIV_3 04149 * @arg @ref LL_RCC_RTC_HSE_DIV_4 04150 * @arg @ref LL_RCC_RTC_HSE_DIV_5 04151 * @arg @ref LL_RCC_RTC_HSE_DIV_6 04152 * @arg @ref LL_RCC_RTC_HSE_DIV_7 04153 * @arg @ref LL_RCC_RTC_HSE_DIV_8 04154 * @arg @ref LL_RCC_RTC_HSE_DIV_9 04155 * @arg @ref LL_RCC_RTC_HSE_DIV_10 04156 * @arg @ref LL_RCC_RTC_HSE_DIV_11 04157 * @arg @ref LL_RCC_RTC_HSE_DIV_12 04158 * @arg @ref LL_RCC_RTC_HSE_DIV_13 04159 * @arg @ref LL_RCC_RTC_HSE_DIV_14 04160 * @arg @ref LL_RCC_RTC_HSE_DIV_15 04161 * @arg @ref LL_RCC_RTC_HSE_DIV_16 04162 * @arg @ref LL_RCC_RTC_HSE_DIV_17 04163 * @arg @ref LL_RCC_RTC_HSE_DIV_18 04164 * @arg @ref LL_RCC_RTC_HSE_DIV_19 04165 * @arg @ref LL_RCC_RTC_HSE_DIV_20 04166 * @arg @ref LL_RCC_RTC_HSE_DIV_21 04167 * @arg @ref LL_RCC_RTC_HSE_DIV_22 04168 * @arg @ref LL_RCC_RTC_HSE_DIV_23 04169 * @arg @ref LL_RCC_RTC_HSE_DIV_24 04170 * @arg @ref LL_RCC_RTC_HSE_DIV_25 04171 * @arg @ref LL_RCC_RTC_HSE_DIV_26 04172 * @arg @ref LL_RCC_RTC_HSE_DIV_27 04173 * @arg @ref LL_RCC_RTC_HSE_DIV_28 04174 * @arg @ref LL_RCC_RTC_HSE_DIV_29 04175 * @arg @ref LL_RCC_RTC_HSE_DIV_30 04176 * @arg @ref LL_RCC_RTC_HSE_DIV_31 04177 * @arg @ref LL_RCC_RTC_HSE_DIV_32 04178 * @arg @ref LL_RCC_RTC_HSE_DIV_33 04179 * @arg @ref LL_RCC_RTC_HSE_DIV_34 04180 * @arg @ref LL_RCC_RTC_HSE_DIV_35 04181 * @arg @ref LL_RCC_RTC_HSE_DIV_36 04182 * @arg @ref LL_RCC_RTC_HSE_DIV_37 04183 * @arg @ref LL_RCC_RTC_HSE_DIV_38 04184 * @arg @ref LL_RCC_RTC_HSE_DIV_39 04185 * @arg @ref LL_RCC_RTC_HSE_DIV_40 04186 * @arg @ref LL_RCC_RTC_HSE_DIV_41 04187 * @arg @ref LL_RCC_RTC_HSE_DIV_42 04188 * @arg @ref LL_RCC_RTC_HSE_DIV_43 04189 * @arg @ref LL_RCC_RTC_HSE_DIV_44 04190 * @arg @ref LL_RCC_RTC_HSE_DIV_45 04191 * @arg @ref LL_RCC_RTC_HSE_DIV_46 04192 * @arg @ref LL_RCC_RTC_HSE_DIV_47 04193 * @arg @ref LL_RCC_RTC_HSE_DIV_48 04194 * @arg @ref LL_RCC_RTC_HSE_DIV_49 04195 * @arg @ref LL_RCC_RTC_HSE_DIV_50 04196 * @arg @ref LL_RCC_RTC_HSE_DIV_51 04197 * @arg @ref LL_RCC_RTC_HSE_DIV_52 04198 * @arg @ref LL_RCC_RTC_HSE_DIV_53 04199 * @arg @ref LL_RCC_RTC_HSE_DIV_54 04200 * @arg @ref LL_RCC_RTC_HSE_DIV_55 04201 * @arg @ref LL_RCC_RTC_HSE_DIV_56 04202 * @arg @ref LL_RCC_RTC_HSE_DIV_57 04203 * @arg @ref LL_RCC_RTC_HSE_DIV_58 04204 * @arg @ref LL_RCC_RTC_HSE_DIV_59 04205 * @arg @ref LL_RCC_RTC_HSE_DIV_60 04206 * @arg @ref LL_RCC_RTC_HSE_DIV_61 04207 * @arg @ref LL_RCC_RTC_HSE_DIV_62 04208 * @arg @ref LL_RCC_RTC_HSE_DIV_63 04209 */ 04210 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) 04211 { 04212 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); 04213 } 04214 04215 /** 04216 * @} 04217 */ 04218 04219 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM 04220 * @{ 04221 */ 04222 04223 /** 04224 * @brief Set Timers Clock Prescalers 04225 * @rmtoll CFGR TIMPRE LL_RCC_SetTIMPrescaler 04226 * @param Prescaler This parameter can be one of the following values: 04227 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE 04228 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES 04229 * @retval None 04230 */ 04231 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) 04232 { 04233 MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler); 04234 } 04235 04236 /** 04237 * @brief Get Timers Clock Prescalers 04238 * @rmtoll CFGR TIMPRE LL_RCC_GetTIMPrescaler 04239 * @retval Returned value can be one of the following values: 04240 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE 04241 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES 04242 */ 04243 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) 04244 { 04245 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE)); 04246 } 04247 04248 /** 04249 * @} 04250 */ 04251 04252 #if defined(HRTIM1) 04253 /** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM 04254 * @{ 04255 */ 04256 04257 /** 04258 * @brief Set High Resolution Timers Clock Source 04259 * @rmtoll CFGR HRTIMSEL LL_RCC_SetHRTIMClockSource 04260 * @param Prescaler This parameter can be one of the following values: 04261 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM 04262 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU 04263 * @retval None 04264 */ 04265 __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler) 04266 { 04267 MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler); 04268 } 04269 #endif /* HRTIM1 */ 04270 04271 #if defined(HRTIM1) 04272 /** 04273 * @brief Get High Resolution Timers Clock Source 04274 * @rmtoll CFGR HRTIMSEL LL_RCC_GetHRTIMClockSource 04275 * @retval Returned value can be one of the following values: 04276 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM 04277 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU 04278 */ 04279 __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void) 04280 { 04281 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)); 04282 } 04283 /** 04284 * @} 04285 */ 04286 #endif /* HRTIM1 */ 04287 04288 /** @defgroup RCC_LL_EF_PLL PLL 04289 * @{ 04290 */ 04291 04292 /** 04293 * @brief Set the oscillator used as PLL clock source. 04294 * @note PLLSRC can be written only when All PLLs are disabled. 04295 * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_SetSource 04296 * @param PLLSource parameter can be one of the following values: 04297 * @arg @ref LL_RCC_PLLSOURCE_HSI 04298 * @arg @ref LL_RCC_PLLSOURCE_CSI 04299 * @arg @ref LL_RCC_PLLSOURCE_HSE 04300 * @arg @ref LL_RCC_PLLSOURCE_NONE 04301 * @retval None 04302 */ 04303 __STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource) 04304 { 04305 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource); 04306 } 04307 04308 /** 04309 * @brief Get the oscillator used as PLL clock source. 04310 * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_GetSource 04311 * @retval Returned value can be one of the following values: 04312 * @arg @ref LL_RCC_PLLSOURCE_HSI 04313 * @arg @ref LL_RCC_PLLSOURCE_CSI 04314 * @arg @ref LL_RCC_PLLSOURCE_HSE 04315 * @arg @ref LL_RCC_PLLSOURCE_NONE 04316 */ 04317 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void) 04318 { 04319 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC)); 04320 } 04321 04322 /** 04323 * @brief Enable PLL1 04324 * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable 04325 * @retval None 04326 */ 04327 __STATIC_INLINE void LL_RCC_PLL1_Enable(void) 04328 { 04329 SET_BIT(RCC->CR, RCC_CR_PLL1ON); 04330 } 04331 04332 /** 04333 * @brief Disable PLL1 04334 * @note Cannot be disabled if the PLL1 clock is used as the system clock 04335 * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable 04336 * @retval None 04337 */ 04338 __STATIC_INLINE void LL_RCC_PLL1_Disable(void) 04339 { 04340 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); 04341 } 04342 04343 /** 04344 * @brief Check if PLL1 Ready 04345 * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady 04346 * @retval State of bit (1 or 0). 04347 */ 04348 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) 04349 { 04350 return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY))?1UL:0UL); 04351 } 04352 04353 /** 04354 * @brief Enable PLL1P 04355 * @note This API shall be called only when PLL1 is disabled. 04356 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Enable 04357 * @retval None 04358 */ 04359 __STATIC_INLINE void LL_RCC_PLL1P_Enable(void) 04360 { 04361 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN); 04362 } 04363 04364 /** 04365 * @brief Enable PLL1Q 04366 * @note This API shall be called only when PLL1 is disabled. 04367 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Enable 04368 * @retval None 04369 */ 04370 __STATIC_INLINE void LL_RCC_PLL1Q_Enable(void) 04371 { 04372 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN); 04373 } 04374 04375 /** 04376 * @brief Enable PLL1R 04377 * @note This API shall be called only when PLL1 is disabled. 04378 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Enable 04379 * @retval None 04380 */ 04381 __STATIC_INLINE void LL_RCC_PLL1R_Enable(void) 04382 { 04383 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN); 04384 } 04385 04386 /** 04387 * @brief Enable PLL1 FRACN 04388 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable 04389 * @retval None 04390 */ 04391 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void) 04392 { 04393 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN); 04394 } 04395 04396 /** 04397 * @brief Check if PLL1 P is enabled 04398 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_IsEnabled 04399 * @retval State of bit (1 or 0). 04400 */ 04401 __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void) 04402 { 04403 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN)?1UL:0UL); 04404 } 04405 04406 /** 04407 * @brief Check if PLL1 Q is enabled 04408 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_IsEnabled 04409 * @retval State of bit (1 or 0). 04410 */ 04411 __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void) 04412 { 04413 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN)?1UL:0UL); 04414 } 04415 04416 /** 04417 * @brief Check if PLL1 R is enabled 04418 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_IsEnabled 04419 * @retval State of bit (1 or 0). 04420 */ 04421 __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void) 04422 { 04423 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN)?1UL:0UL); 04424 } 04425 04426 /** 04427 * @brief Check if PLL1 FRACN is enabled 04428 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled 04429 * @retval State of bit (1 or 0). 04430 */ 04431 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void) 04432 { 04433 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN)?1UL:0UL); 04434 } 04435 04436 /** 04437 * @brief Disable PLL1P 04438 * @note This API shall be called only when PLL1 is disabled. 04439 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Disable 04440 * @retval None 04441 */ 04442 __STATIC_INLINE void LL_RCC_PLL1P_Disable(void) 04443 { 04444 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN); 04445 } 04446 04447 /** 04448 * @brief Disable PLL1Q 04449 * @note This API shall be called only when PLL1 is disabled. 04450 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Disable 04451 * @retval None 04452 */ 04453 __STATIC_INLINE void LL_RCC_PLL1Q_Disable(void) 04454 { 04455 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN); 04456 } 04457 04458 /** 04459 * @brief Disable PLL1R 04460 * @note This API shall be called only when PLL1 is disabled. 04461 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Disable 04462 * @retval None 04463 */ 04464 __STATIC_INLINE void LL_RCC_PLL1R_Disable(void) 04465 { 04466 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN); 04467 } 04468 04469 /** 04470 * @brief Disable PLL1 FRACN 04471 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable 04472 * @retval None 04473 */ 04474 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void) 04475 { 04476 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN); 04477 } 04478 04479 /** 04480 * @brief Set PLL1 VCO OutputRange 04481 * @note This API shall be called only when PLL1 is disabled. 04482 * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOuputRange 04483 * @param VCORange This parameter can be one of the following values: 04484 * @arg @ref LL_RCC_PLLVCORANGE_WIDE 04485 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM 04486 * @retval None 04487 */ 04488 __STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange) 04489 { 04490 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos); 04491 } 04492 04493 /** 04494 * @brief Set PLL1 VCO Input Range 04495 * @note This API shall be called only when PLL1 is disabled. 04496 * @rmtoll PLLCFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange 04497 * @param InputRange This parameter can be one of the following values: 04498 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 04499 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 04500 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 04501 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 04502 * @retval None 04503 */ 04504 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange) 04505 { 04506 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos); 04507 } 04508 04509 /** 04510 * @brief Get PLL1 N Coefficient 04511 * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_GetN 04512 * @retval A value between 4 and 512 04513 */ 04514 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void) 04515 { 04516 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1UL); 04517 } 04518 04519 /** 04520 * @brief Get PLL1 M Coefficient 04521 * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_GetM 04522 * @retval A value between 0 and 63 04523 */ 04524 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void) 04525 { 04526 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos); 04527 } 04528 04529 /** 04530 * @brief Get PLL1 P Coefficient 04531 * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_GetP 04532 * @retval A value between 2 and 128 04533 */ 04534 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void) 04535 { 04536 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1UL); 04537 } 04538 04539 /** 04540 * @brief Get PLL1 Q Coefficient 04541 * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_GetQ 04542 * @retval A value between 1 and 128 04543 */ 04544 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void) 04545 { 04546 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1UL); 04547 } 04548 04549 /** 04550 * @brief Get PLL1 R Coefficient 04551 * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_GetR 04552 * @retval A value between 1 and 128 04553 */ 04554 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void) 04555 { 04556 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1UL); 04557 } 04558 04559 /** 04560 * @brief Get PLL1 FRACN Coefficient 04561 * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_GetFRACN 04562 * @retval A value between 0 and 8191 (0x1FFF) 04563 */ 04564 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) 04565 { 04566 return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 04567 } 04568 04569 /** 04570 * @brief Set PLL1 N Coefficient 04571 * @note This API shall be called only when PLL1 is disabled. 04572 * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_SetN 04573 * @param N parameter can be a value between 4 and 512 04574 */ 04575 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N) 04576 { 04577 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N-1UL) << RCC_PLL1DIVR_N1_Pos); 04578 } 04579 04580 /** 04581 * @brief Set PLL1 M Coefficient 04582 * @note This API shall be called only when PLL1 is disabled. 04583 * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_SetM 04584 * @param M parameter can be a value between 0 and 63 04585 */ 04586 __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M) 04587 { 04588 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos); 04589 } 04590 04591 /** 04592 * @brief Set PLL1 P Coefficient 04593 * @note This API shall be called only when PLL1 is disabled. 04594 * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_SetP 04595 * @param P parameter can be a value between 2 (or 1*) and 128 (ODD division factor not supported) 04596 * 04597 * (*) : For stm32h72xxx and stm32h73xxx family lines. 04598 */ 04599 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P) 04600 { 04601 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos); 04602 } 04603 04604 /** 04605 * @brief Set PLL1 Q Coefficient 04606 * @note This API shall be called only when PLL1 is disabled. 04607 * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_SetQ 04608 * @param Q parameter can be a value between 1 and 128 04609 */ 04610 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q) 04611 { 04612 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q-1UL) << RCC_PLL1DIVR_Q1_Pos); 04613 } 04614 04615 /** 04616 * @brief Set PLL1 R Coefficient 04617 * @note This API shall be called only when PLL1 is disabled. 04618 * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_SetR 04619 * @param R parameter can be a value between 1 and 128 04620 */ 04621 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R) 04622 { 04623 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R-1UL) << RCC_PLL1DIVR_R1_Pos); 04624 } 04625 04626 /** 04627 * @brief Set PLL1 FRACN Coefficient 04628 * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_SetFRACN 04629 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) 04630 */ 04631 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN) 04632 { 04633 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos); 04634 } 04635 04636 /** 04637 * @brief Enable PLL2 04638 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable 04639 * @retval None 04640 */ 04641 __STATIC_INLINE void LL_RCC_PLL2_Enable(void) 04642 { 04643 SET_BIT(RCC->CR, RCC_CR_PLL2ON); 04644 } 04645 04646 /** 04647 * @brief Disable PLL2 04648 * @note Cannot be disabled if the PLL2 clock is used as the system clock 04649 * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable 04650 * @retval None 04651 */ 04652 __STATIC_INLINE void LL_RCC_PLL2_Disable(void) 04653 { 04654 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 04655 } 04656 04657 /** 04658 * @brief Check if PLL2 Ready 04659 * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady 04660 * @retval State of bit (1 or 0). 04661 */ 04662 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) 04663 { 04664 return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY))?1UL:0UL); 04665 } 04666 04667 /** 04668 * @brief Enable PLL2P 04669 * @note This API shall be called only when PLL2 is disabled. 04670 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Enable 04671 * @retval None 04672 */ 04673 __STATIC_INLINE void LL_RCC_PLL2P_Enable(void) 04674 { 04675 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN); 04676 } 04677 04678 /** 04679 * @brief Enable PLL2Q 04680 * @note This API shall be called only when PLL2 is disabled. 04681 * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Enable 04682 * @retval None 04683 */ 04684 __STATIC_INLINE void LL_RCC_PLL2Q_Enable(void) 04685 { 04686 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN); 04687 } 04688 04689 /** 04690 * @brief Enable PLL2R 04691 * @note This API shall be called only when PLL2 is disabled. 04692 * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Enable 04693 * @retval None 04694 */ 04695 __STATIC_INLINE void LL_RCC_PLL2R_Enable(void) 04696 { 04697 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN); 04698 } 04699 04700 /** 04701 * @brief Enable PLL2 FRACN 04702 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable 04703 * @retval None 04704 */ 04705 __STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void) 04706 { 04707 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN); 04708 } 04709 04710 /** 04711 * @brief Check if PLL2 P is enabled 04712 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_IsEnabled 04713 * @retval State of bit (1 or 0). 04714 */ 04715 __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void) 04716 { 04717 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN)?1UL:0UL); 04718 } 04719 04720 /** 04721 * @brief Check if PLL2 Q is enabled 04722 * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_IsEnabled 04723 * @retval State of bit (1 or 0). 04724 */ 04725 __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void) 04726 { 04727 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN)?1UL:0UL); 04728 } 04729 04730 /** 04731 * @brief Check if PLL2 R is enabled 04732 * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_IsEnabled 04733 * @retval State of bit (1 or 0). 04734 */ 04735 __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void) 04736 { 04737 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN)?1UL:0UL); 04738 } 04739 04740 /** 04741 * @brief Check if PLL2 FRACN is enabled 04742 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled 04743 * @retval State of bit (1 or 0). 04744 */ 04745 __STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void) 04746 { 04747 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN)?1UL:0UL); 04748 } 04749 04750 /** 04751 * @brief Disable PLL2P 04752 * @note This API shall be called only when PLL2 is disabled. 04753 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Disable 04754 * @retval None 04755 */ 04756 __STATIC_INLINE void LL_RCC_PLL2P_Disable(void) 04757 { 04758 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN); 04759 } 04760 04761 /** 04762 * @brief Disable PLL2Q 04763 * @note This API shall be called only when PLL2 is disabled. 04764 * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Disable 04765 * @retval None 04766 */ 04767 __STATIC_INLINE void LL_RCC_PLL2Q_Disable(void) 04768 { 04769 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN); 04770 } 04771 04772 /** 04773 * @brief Disable PLL2R 04774 * @note This API shall be called only when PLL2 is disabled. 04775 * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Disable 04776 * @retval None 04777 */ 04778 __STATIC_INLINE void LL_RCC_PLL2R_Disable(void) 04779 { 04780 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN); 04781 } 04782 04783 /** 04784 * @brief Disable PLL2 FRACN 04785 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable 04786 * @retval None 04787 */ 04788 __STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void) 04789 { 04790 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN); 04791 } 04792 04793 /** 04794 * @brief Set PLL2 VCO OutputRange 04795 * @note This API shall be called only when PLL2 is disabled. 04796 * @rmtoll PLLCFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOuputRange 04797 * @param VCORange This parameter can be one of the following values: 04798 * @arg @ref LL_RCC_PLLVCORANGE_WIDE 04799 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM 04800 * @retval None 04801 */ 04802 __STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange) 04803 { 04804 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos); 04805 } 04806 04807 /** 04808 * @brief Set PLL2 VCO Input Range 04809 * @note This API shall be called only when PLL2 is disabled. 04810 * @rmtoll PLLCFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange 04811 * @param InputRange This parameter can be one of the following values: 04812 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 04813 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 04814 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 04815 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 04816 * @retval None 04817 */ 04818 __STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange) 04819 { 04820 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos); 04821 } 04822 04823 /** 04824 * @brief Get PLL2 N Coefficient 04825 * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_GetN 04826 * @retval A value between 4 and 512 04827 */ 04828 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void) 04829 { 04830 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1UL); 04831 } 04832 04833 /** 04834 * @brief Get PLL2 M Coefficient 04835 * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_GetM 04836 * @retval A value between 0 and 63 04837 */ 04838 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void) 04839 { 04840 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos); 04841 } 04842 04843 /** 04844 * @brief Get PLL2 P Coefficient 04845 * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_GetP 04846 * @retval A value between 1 and 128 04847 */ 04848 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void) 04849 { 04850 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1UL); 04851 } 04852 04853 /** 04854 * @brief Get PLL2 Q Coefficient 04855 * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_GetQ 04856 * @retval A value between 1 and 128 04857 */ 04858 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void) 04859 { 04860 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1UL); 04861 } 04862 04863 /** 04864 * @brief Get PLL2 R Coefficient 04865 * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_GetR 04866 * @retval A value between 1 and 128 04867 */ 04868 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void) 04869 { 04870 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1UL); 04871 } 04872 04873 /** 04874 * @brief Get PLL2 FRACN Coefficient 04875 * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_GetFRACN 04876 * @retval A value between 0 and 8191 (0x1FFF) 04877 */ 04878 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void) 04879 { 04880 return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >> RCC_PLL2FRACR_FRACN2_Pos); 04881 } 04882 04883 /** 04884 * @brief Set PLL2 N Coefficient 04885 * @note This API shall be called only when PLL2 is disabled. 04886 * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_SetN 04887 * @param N parameter can be a value between 4 and 512 04888 */ 04889 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N) 04890 { 04891 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N-1UL) << RCC_PLL2DIVR_N2_Pos); 04892 } 04893 04894 /** 04895 * @brief Set PLL2 M Coefficient 04896 * @note This API shall be called only when PLL2 is disabled. 04897 * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_SetM 04898 * @param M parameter can be a value between 0 and 63 04899 */ 04900 __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M) 04901 { 04902 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos); 04903 } 04904 04905 /** 04906 * @brief Set PLL2 P Coefficient 04907 * @note This API shall be called only when PLL2 is disabled. 04908 * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_SetP 04909 * @param P parameter can be a value between 1 and 128 04910 */ 04911 __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P) 04912 { 04913 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P-1UL) << RCC_PLL2DIVR_P2_Pos); 04914 } 04915 04916 /** 04917 * @brief Set PLL2 Q Coefficient 04918 * @note This API shall be called only when PLL2 is disabled. 04919 * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_SetQ 04920 * @param Q parameter can be a value between 1 and 128 04921 */ 04922 __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q) 04923 { 04924 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q-1UL) << RCC_PLL2DIVR_Q2_Pos); 04925 } 04926 04927 /** 04928 * @brief Set PLL2 R Coefficient 04929 * @note This API shall be called only when PLL2 is disabled. 04930 * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_SetR 04931 * @param R parameter can be a value between 1 and 128 04932 */ 04933 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R) 04934 { 04935 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R-1UL) << RCC_PLL2DIVR_R2_Pos); 04936 } 04937 04938 /** 04939 * @brief Set PLL2 FRACN Coefficient 04940 * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_SetFRACN 04941 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) 04942 */ 04943 __STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN) 04944 { 04945 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos); 04946 } 04947 04948 /** 04949 * @brief Enable PLL3 04950 * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable 04951 * @retval None 04952 */ 04953 __STATIC_INLINE void LL_RCC_PLL3_Enable(void) 04954 { 04955 SET_BIT(RCC->CR, RCC_CR_PLL3ON); 04956 } 04957 04958 /** 04959 * @brief Disable PLL3 04960 * @note Cannot be disabled if the PLL3 clock is used as the system clock 04961 * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable 04962 * @retval None 04963 */ 04964 __STATIC_INLINE void LL_RCC_PLL3_Disable(void) 04965 { 04966 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 04967 } 04968 04969 /** 04970 * @brief Check if PLL3 Ready 04971 * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady 04972 * @retval State of bit (1 or 0). 04973 */ 04974 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void) 04975 { 04976 return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY))?1UL:0UL); 04977 } 04978 04979 /** 04980 * @brief Enable PLL3P 04981 * @note This API shall be called only when PLL3 is disabled. 04982 * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_Enable 04983 * @retval None 04984 */ 04985 __STATIC_INLINE void LL_RCC_PLL3P_Enable(void) 04986 { 04987 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN); 04988 } 04989 04990 /** 04991 * @brief Enable PLL3Q 04992 * @note This API shall be called only when PLL3 is disabled. 04993 * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Enable 04994 * @retval None 04995 */ 04996 __STATIC_INLINE void LL_RCC_PLL3Q_Enable(void) 04997 { 04998 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN); 04999 } 05000 05001 /** 05002 * @brief Enable PLL3R 05003 * @note This API shall be called only when PLL3 is disabled. 05004 * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Enable 05005 * @retval None 05006 */ 05007 __STATIC_INLINE void LL_RCC_PLL3R_Enable(void) 05008 { 05009 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN); 05010 } 05011 05012 /** 05013 * @brief Enable PLL3 FRACN 05014 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable 05015 * @retval None 05016 */ 05017 __STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void) 05018 { 05019 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN); 05020 } 05021 05022 /** 05023 * @brief Check if PLL3 P is enabled 05024 * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_IsEnabled 05025 * @retval State of bit (1 or 0). 05026 */ 05027 __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void) 05028 { 05029 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN)?1UL:0UL); 05030 } 05031 05032 /** 05033 * @brief Check if PLL3 Q is enabled 05034 * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_IsEnabled 05035 * @retval State of bit (1 or 0). 05036 */ 05037 __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void) 05038 { 05039 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN)?1UL:0UL); 05040 } 05041 05042 /** 05043 * @brief Check if PLL3 R is enabled 05044 * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_IsEnabled 05045 * @retval State of bit (1 or 0). 05046 */ 05047 __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void) 05048 { 05049 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN)?1UL:0UL); 05050 } 05051 05052 /** 05053 * @brief Check if PLL3 FRACN is enabled 05054 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled 05055 * @retval State of bit (1 or 0). 05056 */ 05057 __STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void) 05058 { 05059 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN)?1UL:0UL); 05060 } 05061 05062 /** 05063 * @brief Disable PLL3P 05064 * @note This API shall be called only when PLL3 is disabled. 05065 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL3P_Disable 05066 * @retval None 05067 */ 05068 __STATIC_INLINE void LL_RCC_PLL3P_Disable(void) 05069 { 05070 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN); 05071 } 05072 05073 /** 05074 * @brief Disable PLL3Q 05075 * @note This API shall be called only when PLL3 is disabled. 05076 * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Disable 05077 * @retval None 05078 */ 05079 __STATIC_INLINE void LL_RCC_PLL3Q_Disable(void) 05080 { 05081 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN); 05082 } 05083 05084 /** 05085 * @brief Disable PLL3R 05086 * @note This API shall be called only when PLL3 is disabled. 05087 * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Disable 05088 * @retval None 05089 */ 05090 __STATIC_INLINE void LL_RCC_PLL3R_Disable(void) 05091 { 05092 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN); 05093 } 05094 05095 /** 05096 * @brief Disable PLL3 FRACN 05097 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable 05098 * @retval None 05099 */ 05100 __STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void) 05101 { 05102 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN); 05103 } 05104 05105 /** 05106 * @brief Set PLL3 VCO OutputRange 05107 * @note This API shall be called only when PLL3 is disabled. 05108 * @rmtoll PLLCFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOuputRange 05109 * @param VCORange This parameter can be one of the following values: 05110 * @arg @ref LL_RCC_PLLVCORANGE_WIDE 05111 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM 05112 * @retval None 05113 */ 05114 __STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange) 05115 { 05116 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos); 05117 } 05118 05119 /** 05120 * @brief Set PLL3 VCO Input Range 05121 * @note This API shall be called only when PLL3 is disabled. 05122 * @rmtoll PLLCFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange 05123 * @param InputRange This parameter can be one of the following values: 05124 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 05125 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 05126 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 05127 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 05128 * @retval None 05129 */ 05130 __STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange) 05131 { 05132 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos); 05133 } 05134 05135 /** 05136 * @brief Get PLL3 N Coefficient 05137 * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_GetN 05138 * @retval A value between 4 and 512 05139 */ 05140 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void) 05141 { 05142 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1UL); 05143 } 05144 05145 /** 05146 * @brief Get PLL3 M Coefficient 05147 * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_GetM 05148 * @retval A value between 0 and 63 05149 */ 05150 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void) 05151 { 05152 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); 05153 } 05154 05155 /** 05156 * @brief Get PLL3 P Coefficient 05157 * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_GetP 05158 * @retval A value between 1 and 128 05159 */ 05160 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void) 05161 { 05162 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1UL); 05163 } 05164 05165 /** 05166 * @brief Get PLL3 Q Coefficient 05167 * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_GetQ 05168 * @retval A value between 1 and 128 05169 */ 05170 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void) 05171 { 05172 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1UL); 05173 } 05174 05175 /** 05176 * @brief Get PLL3 R Coefficient 05177 * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_GetR 05178 * @retval A value between 1 and 128 05179 */ 05180 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void) 05181 { 05182 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1UL); 05183 } 05184 05185 /** 05186 * @brief Get PLL3 FRACN Coefficient 05187 * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_GetFRACN 05188 * @retval A value between 0 and 8191 (0x1FFF) 05189 */ 05190 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void) 05191 { 05192 return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >> RCC_PLL3FRACR_FRACN3_Pos); 05193 } 05194 05195 /** 05196 * @brief Set PLL3 N Coefficient 05197 * @note This API shall be called only when PLL3 is disabled. 05198 * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_SetN 05199 * @param N parameter can be a value between 4 and 512 05200 */ 05201 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N) 05202 { 05203 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N-1UL) << RCC_PLL3DIVR_N3_Pos); 05204 } 05205 05206 /** 05207 * @brief Set PLL3 M Coefficient 05208 * @note This API shall be called only when PLL3 is disabled. 05209 * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_SetM 05210 * @param M parameter can be a value between 0 and 63 05211 */ 05212 __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M) 05213 { 05214 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos); 05215 } 05216 05217 /** 05218 * @brief Set PLL3 P Coefficient 05219 * @note This API shall be called only when PLL3 is disabled. 05220 * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_SetP 05221 * @param P parameter can be a value between 1 and 128 05222 */ 05223 __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P) 05224 { 05225 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P-1UL) << RCC_PLL3DIVR_P3_Pos); 05226 } 05227 05228 /** 05229 * @brief Set PLL3 Q Coefficient 05230 * @note This API shall be called only when PLL3 is disabled. 05231 * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_SetQ 05232 * @param Q parameter can be a value between 1 and 128 05233 */ 05234 __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q) 05235 { 05236 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q-1UL) << RCC_PLL3DIVR_Q3_Pos); 05237 } 05238 05239 /** 05240 * @brief Set PLL3 R Coefficient 05241 * @note This API shall be called only when PLL3 is disabled. 05242 * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_SetR 05243 * @param R parameter can be a value between 1 and 128 05244 */ 05245 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R) 05246 { 05247 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R-1UL) << RCC_PLL3DIVR_R3_Pos); 05248 } 05249 05250 /** 05251 * @brief Set PLL3 FRACN Coefficient 05252 * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_SetFRACN 05253 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) 05254 */ 05255 __STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN) 05256 { 05257 MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos); 05258 } 05259 05260 05261 /** 05262 * @} 05263 */ 05264 05265 05266 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management 05267 * @{ 05268 */ 05269 05270 /** 05271 * @brief Clear LSI ready interrupt flag 05272 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY 05273 * @retval None 05274 */ 05275 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) 05276 { 05277 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); 05278 } 05279 05280 /** 05281 * @brief Clear LSE ready interrupt flag 05282 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY 05283 * @retval None 05284 */ 05285 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) 05286 { 05287 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); 05288 } 05289 05290 /** 05291 * @brief Clear HSI ready interrupt flag 05292 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY 05293 * @retval None 05294 */ 05295 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) 05296 { 05297 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); 05298 } 05299 05300 /** 05301 * @brief Clear HSE ready interrupt flag 05302 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY 05303 * @retval None 05304 */ 05305 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) 05306 { 05307 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); 05308 } 05309 05310 /** 05311 * @brief Clear CSI ready interrupt flag 05312 * @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY 05313 * @retval None 05314 */ 05315 __STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void) 05316 { 05317 SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC); 05318 } 05319 05320 /** 05321 * @brief Clear HSI48 ready interrupt flag 05322 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY 05323 * @retval None 05324 */ 05325 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) 05326 { 05327 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); 05328 } 05329 05330 /** 05331 * @brief Clear PLL1 ready interrupt flag 05332 * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY 05333 * @retval None 05334 */ 05335 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void) 05336 { 05337 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); 05338 } 05339 05340 /** 05341 * @brief Clear PLL2 ready interrupt flag 05342 * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY 05343 * @retval None 05344 */ 05345 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) 05346 { 05347 SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC); 05348 } 05349 05350 /** 05351 * @brief Clear PLL3 ready interrupt flag 05352 * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY 05353 * @retval None 05354 */ 05355 __STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void) 05356 { 05357 SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC); 05358 } 05359 05360 /** 05361 * @brief Clear LSE Clock security system interrupt flag 05362 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS 05363 * @retval None 05364 */ 05365 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) 05366 { 05367 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); 05368 } 05369 05370 /** 05371 * @brief Clear HSE Clock security system interrupt flag 05372 * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS 05373 * @retval None 05374 */ 05375 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) 05376 { 05377 SET_BIT(RCC->CICR, RCC_CICR_HSECSSC); 05378 } 05379 05380 /** 05381 * @brief Check if LSI ready interrupt occurred or not 05382 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY 05383 * @retval State of bit (1 or 0). 05384 */ 05385 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) 05386 { 05387 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF))?1UL:0UL); 05388 } 05389 05390 /** 05391 * @brief Check if LSE ready interrupt occurred or not 05392 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY 05393 * @retval State of bit (1 or 0). 05394 */ 05395 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) 05396 { 05397 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF))?1UL:0UL); 05398 } 05399 05400 /** 05401 * @brief Check if HSI ready interrupt occurred or not 05402 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY 05403 * @retval State of bit (1 or 0). 05404 */ 05405 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) 05406 { 05407 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF))?1UL:0UL); 05408 } 05409 05410 /** 05411 * @brief Check if HSE ready interrupt occurred or not 05412 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY 05413 * @retval State of bit (1 or 0). 05414 */ 05415 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) 05416 { 05417 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF))?1UL:0UL); 05418 } 05419 05420 /** 05421 * @brief Check if CSI ready interrupt occurred or not 05422 * @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY 05423 * @retval State of bit (1 or 0). 05424 */ 05425 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void) 05426 { 05427 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF))?1UL:0UL); 05428 } 05429 05430 /** 05431 * @brief Check if HSI48 ready interrupt occurred or not 05432 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY 05433 * @retval State of bit (1 or 0). 05434 */ 05435 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) 05436 { 05437 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))?1UL:0UL); 05438 } 05439 05440 /** 05441 * @brief Check if PLL1 ready interrupt occurred or not 05442 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLL1RDY 05443 * @retval State of bit (1 or 0). 05444 */ 05445 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) 05446 { 05447 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF))?1UL:0UL); 05448 } 05449 05450 /** 05451 * @brief Check if PLL2 ready interrupt occurred or not 05452 * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY 05453 * @retval State of bit (1 or 0). 05454 */ 05455 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) 05456 { 05457 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF))?1UL:0UL); 05458 } 05459 05460 /** 05461 * @brief Check if PLL3 ready interrupt occurred or not 05462 * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY 05463 * @retval State of bit (1 or 0). 05464 */ 05465 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void) 05466 { 05467 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF))?1UL:0UL); 05468 } 05469 05470 /** 05471 * @brief Check if LSE Clock security system interrupt occurred or not 05472 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS 05473 * @retval State of bit (1 or 0). 05474 */ 05475 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) 05476 { 05477 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF))?1UL:0UL); 05478 } 05479 05480 /** 05481 * @brief Check if HSE Clock security system interrupt occurred or not 05482 * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS 05483 * @retval State of bit (1 or 0). 05484 */ 05485 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) 05486 { 05487 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF))?1UL:0UL); 05488 } 05489 05490 /** 05491 * @brief Check if RCC flag Low Power D1 reset is set or not. 05492 * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST (*)\n 05493 * RSR LPWR1RSTF LL_RCC_IsActiveFlag_LPWRRST (**) 05494 * 05495 * (*) Only available for single core devices 05496 * (**) Only available for Dual core devices 05497 * @retval State of bit (1 or 0). 05498 */ 05499 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) 05500 { 05501 #if defined(DUAL_CORE) 05502 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL); 05503 #else 05504 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF))?1UL:0UL); 05505 #endif /*DUAL_CORE*/ 05506 } 05507 05508 #if defined(DUAL_CORE) 05509 /** 05510 * @brief Check if RCC flag Low Power D2 reset is set or not. 05511 * @rmtoll RSR LPWR2RSTF LL_RCC_IsActiveFlag_LPWR2RST 05512 * @retval State of bit (1 or 0). 05513 */ 05514 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void) 05515 { 05516 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL); 05517 } 05518 #endif /*DUAL_CORE*/ 05519 05520 /** 05521 * @brief Check if RCC flag Window Watchdog 1 reset is set or not. 05522 * @rmtoll RSR WWDG1RSTF LL_RCC_IsActiveFlag_WWDG1RST 05523 * @retval State of bit (1 or 0). 05524 */ 05525 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void) 05526 { 05527 return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL); 05528 } 05529 05530 #if defined(DUAL_CORE) 05531 /** 05532 * @brief Check if RCC flag Window Watchdog 2 reset is set or not. 05533 * @rmtoll RSR WWDG2RSTF LL_RCC_IsActiveFlag_WWDG2RST 05534 * @retval State of bit (1 or 0). 05535 */ 05536 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void) 05537 { 05538 return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL); 05539 } 05540 #endif /*DUAL_CORE*/ 05541 05542 /** 05543 * @brief Check if RCC flag Independent Watchdog 1 reset is set or not. 05544 * @rmtoll RSR IWDG1RSTF LL_RCC_IsActiveFlag_IWDG1RST 05545 * @retval State of bit (1 or 0). 05546 */ 05547 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void) 05548 { 05549 return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL); 05550 } 05551 05552 #if defined(DUAL_CORE) 05553 /** 05554 * @brief Check if RCC flag Independent Watchdog 2 reset is set or not. 05555 * @rmtoll RSR IWDG2RSTF LL_RCC_IsActiveFlag_IWDG2RST 05556 * @retval State of bit (1 or 0). 05557 */ 05558 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void) 05559 { 05560 return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL); 05561 } 05562 #endif /*DUAL_CORE*/ 05563 05564 /** 05565 * @brief Check if RCC flag Software reset is set or not. 05566 * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST (*)\n 05567 * RSR SFT1RSTF LL_RCC_IsActiveFlag_SFTRST (**) 05568 * 05569 * (*) Only available for single core devices 05570 * (**) Only available for Dual core devices 05571 * @retval State of bit (1 or 0). 05572 */ 05573 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) 05574 { 05575 #if defined(DUAL_CORE) 05576 return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL); 05577 #else 05578 return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF))?1UL:0UL); 05579 #endif /*DUAL_CORE*/ 05580 } 05581 05582 #if defined(DUAL_CORE) 05583 /** 05584 * @brief Check if RCC flag Software reset is set or not. 05585 * @rmtoll RSR SFT2RSTF LL_RCC_IsActiveFlag_SFT2RST 05586 * @retval State of bit (1 or 0). 05587 */ 05588 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void) 05589 { 05590 return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL); 05591 } 05592 #endif /*DUAL_CORE*/ 05593 05594 /** 05595 * @brief Check if RCC flag POR/PDR reset is set or not. 05596 * @rmtoll RSR PORRSTF LL_RCC_IsActiveFlag_PORRST 05597 * @retval State of bit (1 or 0). 05598 */ 05599 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) 05600 { 05601 return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL); 05602 } 05603 05604 /** 05605 * @brief Check if RCC flag Pin reset is set or not. 05606 * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST 05607 * @retval State of bit (1 or 0). 05608 */ 05609 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) 05610 { 05611 return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL); 05612 } 05613 05614 /** 05615 * @brief Check if RCC flag BOR reset is set or not. 05616 * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST 05617 * @retval State of bit (1 or 0). 05618 */ 05619 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) 05620 { 05621 return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL); 05622 } 05623 05624 #if defined(RCC_RSR_D1RSTF) 05625 /** 05626 * @brief Check if RCC flag D1 reset is set or not. 05627 * @rmtoll RSR D1RSTF LL_RCC_IsActiveFlag_D1RST 05628 * @retval State of bit (1 or 0). 05629 */ 05630 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void) 05631 { 05632 return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL); 05633 } 05634 #endif /* RCC_RSR_D1RSTF */ 05635 05636 #if defined(RCC_RSR_CDRSTF) 05637 /** 05638 * @brief Check if RCC flag CD reset is set or not. 05639 * @rmtoll RSR CDRSTF LL_RCC_IsActiveFlag_CDRST 05640 * @retval State of bit (1 or 0). 05641 */ 05642 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void) 05643 { 05644 return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF))?1UL:0UL); 05645 } 05646 #endif /* RCC_RSR_CDRSTF */ 05647 05648 #if defined(RCC_RSR_D2RSTF) 05649 /** 05650 * @brief Check if RCC flag D2 reset is set or not. 05651 * @rmtoll RSR D2RSTF LL_RCC_IsActiveFlag_D2RST 05652 * @retval State of bit (1 or 0). 05653 */ 05654 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void) 05655 { 05656 return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL); 05657 } 05658 #endif /* RCC_RSR_D2RSTF */ 05659 05660 #if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) 05661 /** 05662 * @brief Check if RCC flag CPU reset is set or not. 05663 * @rmtoll RSR CPURSTF LL_RCC_IsActiveFlag_CPURST (*)\n 05664 * RSR C1RSTF LL_RCC_IsActiveFlag_CPURST (**) 05665 * 05666 * (*) Only available for single core devices 05667 * (**) Only available for Dual core devices 05668 * @retval State of bit (1 or 0). 05669 */ 05670 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void) 05671 { 05672 #if defined(DUAL_CORE) 05673 return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL); 05674 #else 05675 return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF))?1UL:0UL); 05676 #endif/*DUAL_CORE*/ 05677 } 05678 #endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */ 05679 05680 #if defined(DUAL_CORE) 05681 /** 05682 * @brief Check if RCC flag CPU2 reset is set or not. 05683 * @rmtoll RSR C2RSTF LL_RCC_IsActiveFlag_CPU2RST 05684 * @retval State of bit (1 or 0). 05685 */ 05686 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void) 05687 { 05688 return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL); 05689 } 05690 #endif /*DUAL_CORE*/ 05691 05692 /** 05693 * @brief Set RMVF bit to clear all reset flags. 05694 * @rmtoll RSR RMVF LL_RCC_ClearResetFlags 05695 * @retval None 05696 */ 05697 __STATIC_INLINE void LL_RCC_ClearResetFlags(void) 05698 { 05699 SET_BIT(RCC->RSR, RCC_RSR_RMVF); 05700 } 05701 05702 #if defined(DUAL_CORE) 05703 /** 05704 * @brief Check if RCC_C1 flag Low Power D1 reset is set or not. 05705 * @rmtoll RSR LPWR1RSTF LL_C1_RCC_IsActiveFlag_LPWRRST 05706 * @retval State of bit (1 or 0). 05707 */ 05708 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void) 05709 { 05710 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL); 05711 } 05712 05713 /** 05714 * @brief Check if RCC_C1 flag Low Power D2 reset is set or not. 05715 * @rmtoll RSR LPWR2RSTF LL_C1_RCC_IsActiveFlag_LPWR2RST 05716 * @retval State of bit (1 or 0). 05717 */ 05718 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void) 05719 { 05720 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL); 05721 } 05722 05723 /** 05724 * @brief Check if RCC_C1 flag Window Watchdog 1 reset is set or not. 05725 * @rmtoll RSR WWDG1RSTF LL_C1_RCC_IsActiveFlag_WWDG1RST 05726 * @retval State of bit (1 or 0). 05727 */ 05728 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void) 05729 { 05730 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL); 05731 } 05732 05733 /** 05734 * @brief Check if RCC_C1 flag Window Watchdog 2 reset is set or not. 05735 * @rmtoll RSR WWDG2RSTF LL_C1_RCC_IsActiveFlag_WWDG2RST 05736 * @retval State of bit (1 or 0). 05737 */ 05738 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void) 05739 { 05740 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL); 05741 } 05742 05743 /** 05744 * @brief Check if RCC_C1 flag Independent Watchdog 1 reset is set or not. 05745 * @rmtoll RSR IWDG1RSTF LL_C1_RCC_IsActiveFlag_IWDG1RST 05746 * @retval State of bit (1 or 0). 05747 */ 05748 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void) 05749 { 05750 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL); 05751 } 05752 05753 /** 05754 * @brief Check if RCC_C1 flag Independent Watchdog 2 reset is set or not. 05755 * @rmtoll RSR IWDG2RSTF LL_C1_RCC_IsActiveFlag_IWDG2RST 05756 * @retval State of bit (1 or 0). 05757 */ 05758 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void) 05759 { 05760 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL); 05761 } 05762 05763 /** 05764 * @brief Check if RCC_C1 flag Software reset is set or not. 05765 * @rmtoll RSR SFT1RSTF LL_C1_RCC_IsActiveFlag_SFTRST 05766 * @retval State of bit (1 or 0). 05767 */ 05768 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void) 05769 { 05770 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL); 05771 } 05772 05773 /** 05774 * @brief Check if RCC_C1 flag Software reset is set or not. 05775 * @rmtoll RSR SFT2RSTF LL_C1_RCC_IsActiveFlag_SFT2RST 05776 * @retval State of bit (1 or 0). 05777 */ 05778 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void) 05779 { 05780 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL); 05781 } 05782 05783 /** 05784 * @brief Check if RCC_C1 flag POR/PDR reset is set or not. 05785 * @rmtoll RSR PORRSTF LL_C1_RCC_IsActiveFlag_PORRST 05786 * @retval State of bit (1 or 0). 05787 */ 05788 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void) 05789 { 05790 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL); 05791 } 05792 05793 /** 05794 * @brief Check if RCC_C1 flag Pin reset is set or not. 05795 * @rmtoll RSR PINRSTF LL_C1_RCC_IsActiveFlag_PINRST 05796 * @retval State of bit (1 or 0). 05797 */ 05798 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void) 05799 { 05800 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL); 05801 } 05802 05803 /** 05804 * @brief Check if RCC_C1 flag BOR reset is set or not. 05805 * @rmtoll RSR BORRSTF LL_C1_RCC_IsActiveFlag_BORRST 05806 * @retval State of bit (1 or 0). 05807 */ 05808 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void) 05809 { 05810 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL); 05811 } 05812 05813 /** 05814 * @brief Check if RCC_C1 flag D1 reset is set or not. 05815 * @rmtoll RSR D1RSTF LL_C1_RCC_IsActiveFlag_D1RST 05816 * @retval State of bit (1 or 0). 05817 */ 05818 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void) 05819 { 05820 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL); 05821 } 05822 05823 /** 05824 * @brief Check if RCC_C1 flag D2 reset is set or not. 05825 * @rmtoll RSR D2RSTF LL_C1_RCC_IsActiveFlag_D2RST 05826 * @retval State of bit (1 or 0). 05827 */ 05828 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void) 05829 { 05830 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL); 05831 } 05832 05833 /** 05834 * @brief Check if RCC_C1 flag CPU reset is set or not. 05835 * @rmtoll RSR C1RSTF LL_C1_RCC_IsActiveFlag_CPURST 05836 * @retval State of bit (1 or 0). 05837 */ 05838 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void) 05839 { 05840 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL); 05841 } 05842 05843 /** 05844 * @brief Check if RCC_C1 flag CPU2 reset is set or not. 05845 * @rmtoll RSR C2RSTF LL_C1_RCC_IsActiveFlag_CPU2RST 05846 * @retval State of bit (1 or 0). 05847 */ 05848 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void) 05849 { 05850 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL); 05851 } 05852 05853 /** 05854 * @brief Set RMVF bit to clear the reset flags. 05855 * @rmtoll RSR RMVF LL_C1_RCC_ClearResetFlags 05856 * @retval None 05857 */ 05858 __STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void) 05859 { 05860 SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF); 05861 } 05862 05863 /** 05864 * @brief Check if RCC_C2 flag Low Power D1 reset is set or not. 05865 * @rmtoll RSR LPWR1RSTF LL_C2_RCC_IsActiveFlag_LPWRRST 05866 * @retval State of bit (1 or 0). 05867 */ 05868 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void) 05869 { 05870 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL); 05871 } 05872 05873 /** 05874 * @brief Check if RCC_C2 flag Low Power D2 reset is set or not. 05875 * @rmtoll RSR LPWR2RSTF LL_C2_RCC_IsActiveFlag_LPWR2RST 05876 * @retval State of bit (1 or 0). 05877 */ 05878 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void) 05879 { 05880 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL); 05881 } 05882 05883 /** 05884 * @brief Check if RCC_C2 flag Window Watchdog 1 reset is set or not. 05885 * @rmtoll RSR WWDG1RSTF LL_C2_RCC_IsActiveFlag_WWDG1RST 05886 * @retval State of bit (1 or 0). 05887 */ 05888 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void) 05889 { 05890 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL); 05891 } 05892 05893 /** 05894 * @brief Check if RCC_C2 flag Window Watchdog 2 reset is set or not. 05895 * @rmtoll RSR WWDG2RSTF LL_C2_RCC_IsActiveFlag_WWDG2RST 05896 * @retval State of bit (1 or 0). 05897 */ 05898 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void) 05899 { 05900 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL); 05901 } 05902 05903 /** 05904 * @brief Check if RCC_C2 flag Independent Watchdog 1 reset is set or not. 05905 * @rmtoll RSR IWDG1RSTF LL_C2_RCC_IsActiveFlag_IWDG1RST 05906 * @retval State of bit (1 or 0). 05907 */ 05908 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void) 05909 { 05910 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL); 05911 } 05912 05913 /** 05914 * @brief Check if RCC_C2 flag Independent Watchdog 2 reset is set or not. 05915 * @rmtoll RSR IWDG2RSTF LL_C2_RCC_IsActiveFlag_IWDG2RST 05916 * @retval State of bit (1 or 0). 05917 */ 05918 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void) 05919 { 05920 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL); 05921 } 05922 05923 /** 05924 * @brief Check if RCC_C2 flag Software reset is set or not. 05925 * @rmtoll RSR SFT1RSTF LL_C2_RCC_IsActiveFlag_SFTRST 05926 * @retval State of bit (1 or 0). 05927 */ 05928 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void) 05929 { 05930 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL); 05931 } 05932 05933 /** 05934 * @brief Check if RCC_C2 flag Software reset is set or not. 05935 * @rmtoll RSR SFT2RSTF LL_C2_RCC_IsActiveFlag_SFT2RST 05936 * @retval State of bit (1 or 0). 05937 */ 05938 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void) 05939 { 05940 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL); 05941 } 05942 05943 /** 05944 * @brief Check if RCC_C2 flag POR/PDR reset is set or not. 05945 * @rmtoll RSR PORRSTF LL_C2_RCC_IsActiveFlag_PORRST 05946 * @retval State of bit (1 or 0). 05947 */ 05948 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void) 05949 { 05950 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL); 05951 } 05952 05953 /** 05954 * @brief Check if RCC_C2 flag Pin reset is set or not. 05955 * @rmtoll RSR PINRSTF LL_C2_RCC_IsActiveFlag_PINRST 05956 * @retval State of bit (1 or 0). 05957 */ 05958 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void) 05959 { 05960 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL); 05961 } 05962 05963 /** 05964 * @brief Check if RCC_C2 flag BOR reset is set or not. 05965 * @rmtoll RSR BORRSTF LL_C2_RCC_IsActiveFlag_BORRST 05966 * @retval State of bit (1 or 0). 05967 */ 05968 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void) 05969 { 05970 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL); 05971 } 05972 05973 /** 05974 * @brief Check if RCC_C2 flag D1 reset is set or not. 05975 * @rmtoll RSR D1RSTF LL_C2_RCC_IsActiveFlag_D1RST 05976 * @retval State of bit (1 or 0). 05977 */ 05978 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void) 05979 { 05980 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL); 05981 } 05982 05983 /** 05984 * @brief Check if RCC_C2 flag D2 reset is set or not. 05985 * @rmtoll RSR D2RSTF LL_C2_RCC_IsActiveFlag_D2RST 05986 * @retval State of bit (1 or 0). 05987 */ 05988 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void) 05989 { 05990 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL); 05991 } 05992 05993 /** 05994 * @brief Check if RCC_C2 flag CPU reset is set or not. 05995 * @rmtoll RSR C1RSTF LL_C2_RCC_IsActiveFlag_CPURST 05996 * @retval State of bit (1 or 0). 05997 */ 05998 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void) 05999 { 06000 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL); 06001 } 06002 06003 /** 06004 * @brief Check if RCC_C2 flag CPU2 reset is set or not. 06005 * @rmtoll RSR C2RSTF LL_C2_RCC_IsActiveFlag_CPU2RST 06006 * @retval State of bit (1 or 0). 06007 */ 06008 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void) 06009 { 06010 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL); 06011 } 06012 06013 /** 06014 * @brief Set RMVF bit to clear the reset flags. 06015 * @rmtoll RSR RMVF LL_C2_RCC_ClearResetFlags 06016 * @retval None 06017 */ 06018 __STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void) 06019 { 06020 SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF); 06021 } 06022 #endif /*DUAL_CORE*/ 06023 06024 /** 06025 * @} 06026 */ 06027 06028 /** @defgroup RCC_LL_EF_IT_Management IT Management 06029 * @{ 06030 */ 06031 06032 /** 06033 * @brief Enable LSI ready interrupt 06034 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY 06035 * @retval None 06036 */ 06037 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) 06038 { 06039 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); 06040 } 06041 06042 /** 06043 * @brief Enable LSE ready interrupt 06044 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY 06045 * @retval None 06046 */ 06047 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) 06048 { 06049 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); 06050 } 06051 06052 /** 06053 * @brief Enable HSI ready interrupt 06054 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY 06055 * @retval None 06056 */ 06057 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) 06058 { 06059 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); 06060 } 06061 06062 /** 06063 * @brief Enable HSE ready interrupt 06064 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY 06065 * @retval None 06066 */ 06067 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) 06068 { 06069 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); 06070 } 06071 06072 /** 06073 * @brief Enable CSI ready interrupt 06074 * @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY 06075 * @retval None 06076 */ 06077 __STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void) 06078 { 06079 SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE); 06080 } 06081 06082 /** 06083 * @brief Enable HSI48 ready interrupt 06084 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY 06085 * @retval None 06086 */ 06087 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) 06088 { 06089 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); 06090 } 06091 06092 /** 06093 * @brief Enable PLL1 ready interrupt 06094 * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY 06095 * @retval None 06096 */ 06097 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void) 06098 { 06099 SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); 06100 } 06101 06102 /** 06103 * @brief Enable PLL2 ready interrupt 06104 * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY 06105 * @retval None 06106 */ 06107 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) 06108 { 06109 SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); 06110 } 06111 06112 /** 06113 * @brief Enable PLL3 ready interrupt 06114 * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY 06115 * @retval None 06116 */ 06117 __STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void) 06118 { 06119 SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); 06120 } 06121 06122 /** 06123 * @brief Enable LSECSS interrupt 06124 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS 06125 * @retval None 06126 */ 06127 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) 06128 { 06129 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); 06130 } 06131 06132 /** 06133 * @brief Disable LSI ready interrupt 06134 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY 06135 * @retval None 06136 */ 06137 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) 06138 { 06139 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); 06140 } 06141 06142 /** 06143 * @brief Disable LSE ready interrupt 06144 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY 06145 * @retval None 06146 */ 06147 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) 06148 { 06149 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); 06150 } 06151 06152 /** 06153 * @brief Disable HSI ready interrupt 06154 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY 06155 * @retval None 06156 */ 06157 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) 06158 { 06159 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); 06160 } 06161 06162 /** 06163 * @brief Disable HSE ready interrupt 06164 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY 06165 * @retval None 06166 */ 06167 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) 06168 { 06169 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); 06170 } 06171 06172 /** 06173 * @brief Disable CSI ready interrupt 06174 * @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY 06175 * @retval None 06176 */ 06177 __STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void) 06178 { 06179 CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE); 06180 } 06181 06182 /** 06183 * @brief Disable HSI48 ready interrupt 06184 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY 06185 * @retval None 06186 */ 06187 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) 06188 { 06189 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); 06190 } 06191 06192 /** 06193 * @brief Disable PLL1 ready interrupt 06194 * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY 06195 * @retval None 06196 */ 06197 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void) 06198 { 06199 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); 06200 } 06201 06202 /** 06203 * @brief Disable PLL2 ready interrupt 06204 * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY 06205 * @retval None 06206 */ 06207 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) 06208 { 06209 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); 06210 } 06211 06212 /** 06213 * @brief Disable PLL3 ready interrupt 06214 * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY 06215 * @retval None 06216 */ 06217 __STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void) 06218 { 06219 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); 06220 } 06221 06222 /** 06223 * @brief Disable LSECSS interrupt 06224 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS 06225 * @retval None 06226 */ 06227 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) 06228 { 06229 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); 06230 } 06231 06232 /** 06233 * @brief Checks if LSI ready interrupt source is enabled or disabled. 06234 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnableIT_LSIRDY 06235 * @retval State of bit (1 or 0). 06236 */ 06237 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void) 06238 { 06239 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE)?1UL:0UL); 06240 } 06241 06242 /** 06243 * @brief Checks if LSE ready interrupt source is enabled or disabled. 06244 * @rmtoll CIER LSERDYIE LL_RCC_IsEnableIT_LSERDY 06245 * @retval State of bit (1 or 0). 06246 */ 06247 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void) 06248 { 06249 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE)?1UL:0UL); 06250 } 06251 06252 /** 06253 * @brief Checks if HSI ready interrupt source is enabled or disabled. 06254 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnableIT_HSIRDY 06255 * @retval State of bit (1 or 0). 06256 */ 06257 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void) 06258 { 06259 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE)?1UL:0UL); 06260 } 06261 06262 /** 06263 * @brief Checks if HSE ready interrupt source is enabled or disabled. 06264 * @rmtoll CIER HSERDYIE LL_RCC_IsEnableIT_HSERDY 06265 * @retval State of bit (1 or 0). 06266 */ 06267 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void) 06268 { 06269 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE)?1UL:0UL); 06270 } 06271 06272 /** 06273 * @brief Checks if CSI ready interrupt source is enabled or disabled. 06274 * @rmtoll CIER CSIRDYIE LL_RCC_IsEnableIT_CSIRDY 06275 * @retval State of bit (1 or 0). 06276 */ 06277 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void) 06278 { 06279 return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE)?1UL:0UL); 06280 } 06281 06282 /** 06283 * @brief Checks if HSI48 ready interrupt source is enabled or disabled. 06284 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnableIT_HSI48RDY 06285 * @retval State of bit (1 or 0). 06286 */ 06287 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void) 06288 { 06289 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE)?1UL:0UL); 06290 } 06291 06292 /** 06293 * @brief Checks if PLL1 ready interrupt source is enabled or disabled. 06294 * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnableIT_PLL1RDY 06295 * @retval State of bit (1 or 0). 06296 */ 06297 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void) 06298 { 06299 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE)?1UL:0UL); 06300 } 06301 06302 /** 06303 * @brief Checks if PLL2 ready interrupt source is enabled or disabled. 06304 * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnableIT_PLL2RDY 06305 * @retval State of bit (1 or 0). 06306 */ 06307 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void) 06308 { 06309 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE)?1UL:0UL); 06310 } 06311 06312 /** 06313 * @brief Checks if PLL3 ready interrupt source is enabled or disabled. 06314 * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnableIT_PLL3RDY 06315 * @retval State of bit (1 or 0). 06316 */ 06317 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void) 06318 { 06319 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE)?1UL:0UL); 06320 } 06321 06322 /** 06323 * @brief Checks if LSECSS interrupt source is enabled or disabled. 06324 * @rmtoll CIER LSECSSIE LL_RCC_IsEnableIT_LSECSS 06325 * @retval State of bit (1 or 0). 06326 */ 06327 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void) 06328 { 06329 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE)?1UL:0UL); 06330 } 06331 /** 06332 * @} 06333 */ 06334 06335 #if defined(USE_FULL_LL_DRIVER) 06336 /** @defgroup RCC_LL_EF_Init De-initialization function 06337 * @{ 06338 */ 06339 void LL_RCC_DeInit(void); 06340 /** 06341 * @} 06342 */ 06343 06344 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions 06345 * @{ 06346 */ 06347 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR); 06348 06349 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); 06350 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); 06351 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); 06352 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); 06353 06354 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); 06355 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); 06356 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); 06357 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); 06358 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); 06359 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); 06360 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); 06361 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); 06362 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); 06363 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); 06364 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); 06365 #if defined(DFSDM2_BASE) 06366 uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource); 06367 #endif /* DFSDM2_BASE */ 06368 #if defined(DSI) 06369 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); 06370 #endif /* DSI */ 06371 uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource); 06372 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); 06373 uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource); 06374 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); 06375 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource); 06376 #if defined(QUADSPI) 06377 uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource); 06378 #endif /* QUADSPI */ 06379 #if defined(OCTOSPI1) || defined(OCTOSPI2) 06380 uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource); 06381 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ 06382 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource); 06383 06384 06385 /** 06386 * @} 06387 */ 06388 #endif /* USE_FULL_LL_DRIVER */ 06389 06390 /** 06391 * @} 06392 */ 06393 06394 06395 /** 06396 * @} 06397 */ 06398 #endif /* defined(RCC) */ 06399 06400 /** 06401 * @} 06402 */ 06403 06404 #ifdef __cplusplus 06405 } 06406 #endif 06407 06408 #endif /* STM32H7xx_LL_RCC_H */ 06409
1.7.6.1