Defines
#define	TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define	I2C_TIMEOUT_ADDR (10000U)
#define	I2C_TIMEOUT_BUSY (25U)
#define	I2C_TIMEOUT_DIR (25U)
#define	I2C_TIMEOUT_RXNE (25U)
#define	I2C_TIMEOUT_STOPF (25U)
#define	I2C_TIMEOUT_TC (25U)
#define	I2C_TIMEOUT_TCR (25U)
#define	I2C_TIMEOUT_TXIS (25U)
#define	I2C_TIMEOUT_FLAG (25U)
#define	MAX_NBYTE_SIZE 255U
#define	SLAVE_ADDR_SHIFT 7U
#define	SLAVE_ADDR_MSK 0x06U
#define	I2C_STATE_MSK
#define	I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define	I2C_STATE_MASTER_BUSY_TX
#define	I2C_STATE_MASTER_BUSY_RX
#define	I2C_STATE_SLAVE_BUSY_TX
#define	I2C_STATE_SLAVE_BUSY_RX
#define	I2C_STATE_MEM_BUSY_TX
#define	I2C_STATE_MEM_BUSY_RX
#define	I2C_XFER_TX_IT (uint16_t)(0x0001U)
#define	I2C_XFER_RX_IT (uint16_t)(0x0002U)
#define	I2C_XFER_LISTEN_IT (uint16_t)(0x8000U)
#define	I2C_XFER_ERROR_IT (uint16_t)(0x0010U)
#define	I2C_XFER_CPLT_IT (uint16_t)(0x0020U)
#define	I2C_XFER_RELOAD_IT (uint16_t)(0x0040U)
#define	I2C_NO_OPTION_FRAME (0xFFFF0000U)

Define Documentation

#define I2C_STATE_MASTER_BUSY_RX

Value:

((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_MASTER))

Master Busy RX, combinaison of State LSB and Mode enum

Definition at line 367 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), I2C_ITError(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

#define I2C_STATE_MASTER_BUSY_TX

Value:

((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_MASTER))

Master Busy TX, combinaison of State LSB and Mode enum

Definition at line 364 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), I2C_ITError(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

#define I2C_STATE_MEM_BUSY_RX

Value:

((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_MEM))

Memory Busy RX, combinaison of State LSB and Mode enum

Definition at line 379 of file stm32l4xx_hal_i2c.c.

#define I2C_STATE_MEM_BUSY_TX

Value:

((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_MEM))

Memory Busy TX, combinaison of State LSB and Mode enum

Definition at line 376 of file stm32l4xx_hal_i2c.c.

#define I2C_STATE_MSK

Value:

((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
                                                         (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
                                              (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))

Mask State define, keep only RX and TX bits

Definition at line 358 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT().

#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))

Default Value

Definition at line 362 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_TreatErrorCallback().

#define I2C_STATE_SLAVE_BUSY_RX

Value:

((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_SLAVE))

Slave Busy RX, combinaison of State LSB and Mode enum

Definition at line 373 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITError(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), and I2C_Slave_ISR_DMA().

#define I2C_STATE_SLAVE_BUSY_TX

Value:

((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_SLAVE))

Slave Busy TX, combinaison of State LSB and Mode enum

Definition at line 370 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITError(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), and I2C_Slave_ISR_DMA().

#define I2C_TIMEOUT_ADDR (10000U)

10 s

Definition at line 343 of file stm32l4xx_hal_i2c.c.

#define I2C_TIMEOUT_BUSY (25U)

25 ms

Definition at line 344 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), and HAL_I2C_Mem_Write().

#define I2C_TIMEOUT_DIR (25U)

25 ms

Definition at line 345 of file stm32l4xx_hal_i2c.c.

#define I2C_TIMEOUT_FLAG (25U)

25 ms

Definition at line 351 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define I2C_TIMEOUT_RXNE (25U)

25 ms

Definition at line 346 of file stm32l4xx_hal_i2c.c.

#define I2C_TIMEOUT_STOPF (25U)

25 ms

Definition at line 347 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_IsErrorOccurred().

#define I2C_TIMEOUT_TC (25U)

25 ms

Definition at line 348 of file stm32l4xx_hal_i2c.c.

#define I2C_TIMEOUT_TCR (25U)

25 ms

Definition at line 349 of file stm32l4xx_hal_i2c.c.

#define I2C_TIMEOUT_TXIS (25U)

25 ms

Definition at line 350 of file stm32l4xx_hal_i2c.c.

#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U)

Bit definition to manage only STOP evenement

Definition at line 394 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), and I2C_Master_ISR_DMA().

#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U)

Bit definition to manage addition of global Error and NACK treatment

Definition at line 392 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U)

Bit field can be combinated with I2C_XFER_TX_IT and I2C_XFER_RX_IT

Definition at line 389 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U)

Bit definition to manage only Reload of NBYTE

Definition at line 395 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Enable_IRQ().

#define I2C_XFER_RX_IT (uint16_t)(0x0002U)

Bit field can be combinated with I2C_XFER_LISTEN_IT

Definition at line 387 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

#define I2C_XFER_TX_IT (uint16_t)(0x0001U)

#define SLAVE_ADDR_MSK 0x06U

Definition at line 355 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define SLAVE_ADDR_SHIFT 7U

Definition at line 354 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define TIMING_CLEAR_MASK (0xF0FFFFFFU)

I2C TIMING clear register Mask

Definition at line 342 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Defines

Define Documentation