STM32L443xx HAL User Manual
|
Defines | |
#define | LL_LPTIM_CLK_FILTER_NONE 0x00000000U |
#define | LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 |
#define | LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 |
#define | LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT |
#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 |
External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition
Definition at line 248 of file stm32l4xx_ll_lptim.h.
#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 |
External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition
Definition at line 249 of file stm32l4xx_ll_lptim.h.
#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT |
External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition
Definition at line 250 of file stm32l4xx_ll_lptim.h.
#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U |
Any external clock signal level change is considered as a valid transition
Definition at line 247 of file stm32l4xx_ll_lptim.h.