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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal.h 00004 * @author MCD Application Team 00005 * @brief This file contains all the functions prototypes for the HAL 00006 * module driver. 00007 ****************************************************************************** 00008 * @attention 00009 * 00010 * Copyright (c) 2017 STMicroelectronics. 00011 * All rights reserved. 00012 * 00013 * This software is licensed under terms that can be found in the LICENSE file 00014 * in the root directory of this software component. 00015 * If no LICENSE file comes with this software, it is provided AS-IS. 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32L4xx_HAL_H 00022 #define STM32L4xx_HAL_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32l4xx_hal_conf.h" 00030 00031 /** @addtogroup STM32L4xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup HAL 00036 * @{ 00037 */ 00038 00039 /* Exported types ------------------------------------------------------------*/ 00040 /** @defgroup HAL_Exported_Types HAL Exported Types 00041 * @{ 00042 */ 00043 00044 /** @defgroup HAL_TICK_FREQ Tick Frequency 00045 * @{ 00046 */ 00047 typedef enum 00048 { 00049 HAL_TICK_FREQ_10HZ = 100U, 00050 HAL_TICK_FREQ_100HZ = 10U, 00051 HAL_TICK_FREQ_1KHZ = 1U, 00052 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 00053 } HAL_TickFreqTypeDef; 00054 /** 00055 * @} 00056 */ 00057 00058 /** 00059 * @} 00060 */ 00061 00062 /* Exported constants --------------------------------------------------------*/ 00063 00064 /** @defgroup HAL_Exported_Constants HAL Exported Constants 00065 * @{ 00066 */ 00067 00068 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 00069 * @{ 00070 */ 00071 00072 /** @defgroup SYSCFG_BootMode Boot Mode 00073 * @{ 00074 */ 00075 #define SYSCFG_BOOT_MAINFLASH 0U 00076 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 00077 00078 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00079 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00080 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 00081 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00082 #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 00083 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 00084 /* STM32L496xx || STM32L4A6xx || */ 00085 /* STM32L4P5xx || STM32L4Q5xx || */ 00086 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00087 00088 #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) 00089 00090 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00091 #define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2) 00092 #define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0) 00093 #else 00094 #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) 00095 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00096 00097 /** 00098 * @} 00099 */ 00100 00101 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 00102 * @{ 00103 */ 00104 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 00105 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 00106 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 00107 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 00108 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 00109 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 00110 00111 /** 00112 * @} 00113 */ 00114 00115 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) 00116 * @{ 00117 */ 00118 #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ 00119 #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ 00120 #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ 00121 #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ 00122 #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ 00123 #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ 00124 #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ 00125 #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ 00126 #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ 00127 #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ 00128 #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ 00129 #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ 00130 #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ 00131 #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ 00132 #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ 00133 #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ 00134 #if defined(SYSCFG_SWPR_PAGE31) 00135 #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ 00136 #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ 00137 #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ 00138 #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ 00139 #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ 00140 #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ 00141 #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ 00142 #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ 00143 #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ 00144 #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ 00145 #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ 00146 #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ 00147 #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ 00148 #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ 00149 #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ 00150 #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ 00151 #endif /* SYSCFG_SWPR_PAGE31 */ 00152 00153 /** 00154 * @} 00155 */ 00156 00157 #if defined(SYSCFG_SWPR2_PAGE63) 00158 /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63) 00159 * @{ 00160 */ 00161 #define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */ 00162 #define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */ 00163 #define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */ 00164 #define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */ 00165 #define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */ 00166 #define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */ 00167 #define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */ 00168 #define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */ 00169 #define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */ 00170 #define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */ 00171 #define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */ 00172 #define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */ 00173 #define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */ 00174 #define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */ 00175 #define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */ 00176 #define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */ 00177 #define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */ 00178 #define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */ 00179 #define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */ 00180 #define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */ 00181 #define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */ 00182 #define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */ 00183 #define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */ 00184 #define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */ 00185 #define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */ 00186 #define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */ 00187 #define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */ 00188 #define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */ 00189 #define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */ 00190 #define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */ 00191 #define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */ 00192 #define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */ 00193 00194 /** 00195 * @} 00196 */ 00197 #endif /* SYSCFG_SWPR2_PAGE63 */ 00198 00199 #if defined(VREFBUF) 00200 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 00201 * @{ 00202 */ 00203 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */ 00204 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ 00205 00206 /** 00207 * @} 00208 */ 00209 00210 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 00211 * @{ 00212 */ 00213 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 00214 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 00215 00216 /** 00217 * @} 00218 */ 00219 #endif /* VREFBUF */ 00220 00221 /** @defgroup SYSCFG_flags_definition Flags 00222 * @{ 00223 */ 00224 00225 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 00226 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 00227 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 00233 * @{ 00234 */ 00235 00236 /** @brief Fast-mode Plus driving capability on a specific GPIO 00237 */ 00238 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 00239 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 00240 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) 00241 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 00242 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ 00243 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) 00244 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 00245 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ 00246 00247 /** 00248 * @} 00249 */ 00250 00251 /** 00252 * @} 00253 */ 00254 00255 /** 00256 * @} 00257 */ 00258 00259 /* Exported macros -----------------------------------------------------------*/ 00260 /** @defgroup HAL_Exported_Macros HAL Exported Macros 00261 * @{ 00262 */ 00263 00264 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 00265 * @{ 00266 */ 00267 00268 /** @brief Freeze/Unfreeze Peripherals in Debug mode 00269 */ 00270 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 00271 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 00272 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 00273 #endif 00274 00275 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 00276 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 00277 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 00278 #endif 00279 00280 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 00281 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 00282 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 00283 #endif 00284 00285 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 00286 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 00287 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 00288 #endif 00289 00290 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 00291 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 00292 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 00293 #endif 00294 00295 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 00296 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 00297 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 00298 #endif 00299 00300 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) 00301 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 00302 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 00303 #endif 00304 00305 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 00306 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 00307 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 00308 #endif 00309 00310 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 00311 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 00312 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 00313 #endif 00314 00315 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 00316 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 00317 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 00318 #endif 00319 00320 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 00321 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 00322 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 00323 #endif 00324 00325 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) 00326 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 00327 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 00328 #endif 00329 00330 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) 00331 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 00332 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 00333 #endif 00334 00335 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP) 00336 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 00337 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 00338 #endif 00339 00340 #if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP) 00341 #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) 00342 #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) 00343 #endif 00344 00345 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 00346 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 00347 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 00348 #endif 00349 00350 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 00351 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 00352 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 00353 #endif 00354 00355 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) 00356 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 00357 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 00358 #endif 00359 00360 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) 00361 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 00362 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 00363 #endif 00364 00365 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) 00366 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 00367 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 00368 #endif 00369 00370 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) 00371 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 00372 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 00373 #endif 00374 00375 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) 00376 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 00377 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 00378 #endif 00379 00380 /** 00381 * @} 00382 */ 00383 00384 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 00385 * @{ 00386 */ 00387 00388 /** @brief Main Flash memory mapped at 0x00000000. 00389 */ 00390 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 00391 00392 /** @brief System Flash memory mapped at 0x00000000. 00393 */ 00394 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) 00395 00396 /** @brief Embedded SRAM mapped at 0x00000000. 00397 */ 00398 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) 00399 00400 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00401 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00402 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 00403 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00404 00405 /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. 00406 */ 00407 #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) 00408 00409 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 00410 /* STM32L496xx || STM32L4A6xx || */ 00411 /* STM32L4P5xx || STM32L4Q5xx || */ 00412 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00413 00414 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00415 00416 /** @brief OCTOSPI mapped at 0x00000000. 00417 */ 00418 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2)) 00419 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0)) 00420 00421 #else 00422 00423 /** @brief QUADSPI mapped at 0x00000000. 00424 */ 00425 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) 00426 00427 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00428 00429 /** 00430 * @brief Return the boot mode as configured by user. 00431 * @retval The boot mode as configured by user. The returned value can be one 00432 * of the following values: 00433 * @arg @ref SYSCFG_BOOT_MAINFLASH 00434 * @arg @ref SYSCFG_BOOT_SYSTEMFLASH 00435 @if STM32L486xx 00436 * @arg @ref SYSCFG_BOOT_FMC 00437 @endif 00438 * @arg @ref SYSCFG_BOOT_SRAM 00439 @if STM32L422xx 00440 * @arg @ref SYSCFG_BOOT_QUADSPI 00441 @endif 00442 @if STM32L443xx 00443 * @arg @ref SYSCFG_BOOT_QUADSPI 00444 @endif 00445 @if STM32L462xx 00446 * @arg @ref SYSCFG_BOOT_QUADSPI 00447 @endif 00448 @if STM32L486xx 00449 * @arg @ref SYSCFG_BOOT_QUADSPI 00450 @endif 00451 */ 00452 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 00453 00454 /** @brief SRAM2 page 0 to 31 write protection enable macro 00455 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP 00456 * @note Write protection can only be disabled by a system reset 00457 */ 00458 #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 00459 SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ 00460 }while(0) 00461 00462 #if defined(SYSCFG_SWPR2_PAGE63) 00463 /** @brief SRAM2 page 32 to 63 write protection enable macro 00464 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 00465 * @note Write protection can only be disabled by a system reset 00466 */ 00467 #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 00468 SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\ 00469 }while(0) 00470 #endif /* SYSCFG_SWPR2_PAGE63 */ 00471 00472 /** @brief SRAM2 page write protection unlock prior to erase 00473 * @note Writing a wrong key reactivates the write protection 00474 */ 00475 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ 00476 SYSCFG->SKR = 0x53;\ 00477 }while(0) 00478 00479 /** @brief SRAM2 erase 00480 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase 00481 */ 00482 #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) 00483 00484 /** @brief Floating Point Unit interrupt enable/disable macros 00485 * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts 00486 */ 00487 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 00488 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 00489 }while(0) 00490 00491 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 00492 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 00493 }while(0) 00494 00495 /** @brief SYSCFG Break ECC lock. 00496 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 00497 * @note The selected configuration is locked and can be unlocked only by system reset. 00498 */ 00499 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 00500 00501 /** @brief SYSCFG Break Cortex-M4 Lockup lock. 00502 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 00503 * @note The selected configuration is locked and can be unlocked only by system reset. 00504 */ 00505 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 00506 00507 /** @brief SYSCFG Break PVD lock. 00508 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 00509 * @note The selected configuration is locked and can be unlocked only by system reset. 00510 */ 00511 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 00512 00513 /** @brief SYSCFG Break SRAM2 parity lock. 00514 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 00515 * @note The selected configuration is locked and can be unlocked by system reset. 00516 */ 00517 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 00518 00519 /** @brief Check SYSCFG flag is set or not. 00520 * @param __FLAG__ specifies the flag to check. 00521 * This parameter can be one of the following values: 00522 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 00523 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 00524 * @retval The new state of __FLAG__ (TRUE or FALSE). 00525 */ 00526 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U) 00527 00528 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 00529 */ 00530 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 00531 00532 /** @brief Fast-mode Plus driving capability enable/disable macros 00533 * @param __FASTMODEPLUS__ This parameter can be a value of : 00534 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 00535 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 00536 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 00537 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 00538 */ 00539 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 00540 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 00541 }while(0) 00542 00543 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 00544 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 00545 }while(0) 00546 00547 /** 00548 * @} 00549 */ 00550 00551 /** 00552 * @} 00553 */ 00554 00555 /* Private macros ------------------------------------------------------------*/ 00556 /** @defgroup HAL_Private_Macros HAL Private Macros 00557 * @{ 00558 */ 00559 00560 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 00561 * @{ 00562 */ 00563 00564 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 00565 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 00566 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 00567 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 00568 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 00569 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 00570 00571 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 00572 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 00573 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 00574 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 00575 00576 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL)) 00577 00578 #if defined(VREFBUF) 00579 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 00580 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 00581 00582 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 00583 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 00584 00585 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 00586 #endif /* VREFBUF */ 00587 00588 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) 00589 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 00590 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 00591 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 00592 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 00593 #elif defined(SYSCFG_FASTMODEPLUS_PB8) 00594 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 00595 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 00596 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) 00597 #elif defined(SYSCFG_FASTMODEPLUS_PB9) 00598 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 00599 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 00600 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 00601 #else 00602 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 00603 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) 00604 #endif 00605 /** 00606 * @} 00607 */ 00608 00609 /** 00610 * @} 00611 */ 00612 00613 /* Exported variables --------------------------------------------------------*/ 00614 00615 /** @addtogroup HAL_Exported_Variables 00616 * @{ 00617 */ 00618 extern __IO uint32_t uwTick; 00619 extern uint32_t uwTickPrio; 00620 extern HAL_TickFreqTypeDef uwTickFreq; 00621 /** 00622 * @} 00623 */ 00624 00625 /* Exported functions --------------------------------------------------------*/ 00626 00627 /** @addtogroup HAL_Exported_Functions 00628 * @{ 00629 */ 00630 00631 /** @addtogroup HAL_Exported_Functions_Group1 00632 * @{ 00633 */ 00634 00635 /* Initialization and de-initialization functions ******************************/ 00636 HAL_StatusTypeDef HAL_Init(void); 00637 HAL_StatusTypeDef HAL_DeInit(void); 00638 void HAL_MspInit(void); 00639 void HAL_MspDeInit(void); 00640 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 00641 00642 /** 00643 * @} 00644 */ 00645 00646 /** @addtogroup HAL_Exported_Functions_Group2 00647 * @{ 00648 */ 00649 00650 /* Peripheral Control functions ************************************************/ 00651 void HAL_IncTick(void); 00652 void HAL_Delay(uint32_t Delay); 00653 uint32_t HAL_GetTick(void); 00654 uint32_t HAL_GetTickPrio(void); 00655 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 00656 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 00657 void HAL_SuspendTick(void); 00658 void HAL_ResumeTick(void); 00659 uint32_t HAL_GetHalVersion(void); 00660 uint32_t HAL_GetREVID(void); 00661 uint32_t HAL_GetDEVID(void); 00662 uint32_t HAL_GetUIDw0(void); 00663 uint32_t HAL_GetUIDw1(void); 00664 uint32_t HAL_GetUIDw2(void); 00665 00666 /** 00667 * @} 00668 */ 00669 00670 /** @addtogroup HAL_Exported_Functions_Group3 00671 * @{ 00672 */ 00673 00674 /* DBGMCU Peripheral Control functions *****************************************/ 00675 void HAL_DBGMCU_EnableDBGSleepMode(void); 00676 void HAL_DBGMCU_DisableDBGSleepMode(void); 00677 void HAL_DBGMCU_EnableDBGStopMode(void); 00678 void HAL_DBGMCU_DisableDBGStopMode(void); 00679 void HAL_DBGMCU_EnableDBGStandbyMode(void); 00680 void HAL_DBGMCU_DisableDBGStandbyMode(void); 00681 00682 /** 00683 * @} 00684 */ 00685 00686 /** @addtogroup HAL_Exported_Functions_Group4 00687 * @{ 00688 */ 00689 00690 /* SYSCFG Control functions ****************************************************/ 00691 void HAL_SYSCFG_SRAM2Erase(void); 00692 void HAL_SYSCFG_EnableMemorySwappingBank(void); 00693 void HAL_SYSCFG_DisableMemorySwappingBank(void); 00694 00695 #if defined(VREFBUF) 00696 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 00697 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 00698 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 00699 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 00700 void HAL_SYSCFG_DisableVREFBUF(void); 00701 #endif /* VREFBUF */ 00702 00703 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 00704 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 00705 00706 /** 00707 * @} 00708 */ 00709 00710 /** 00711 * @} 00712 */ 00713 00714 /** 00715 * @} 00716 */ 00717 00718 /** 00719 * @} 00720 */ 00721 00722 #ifdef __cplusplus 00723 } 00724 #endif 00725 00726 #endif /* STM32L4xx_HAL_H */
1.7.6.1