STM32L443xx HAL User Manual
stm32l4xx_hal_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_pwr.c
00004   * @author  MCD Application Team
00005   * @brief   PWR HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Power Controller (PWR) peripheral:
00008   *           + Initialization/de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2019 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   */
00023 
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32l4xx_hal.h"
00026 
00027 /** @addtogroup STM32L4xx_HAL_Driver
00028   * @{
00029   */
00030 
00031 /** @defgroup PWR PWR
00032   * @brief PWR HAL module driver
00033   * @{
00034   */
00035 
00036 #ifdef HAL_PWR_MODULE_ENABLED
00037 
00038 /* Private typedef -----------------------------------------------------------*/
00039 /* Private define ------------------------------------------------------------*/
00040 
00041 /** @defgroup PWR_Private_Defines PWR Private Defines
00042   * @{
00043   */
00044 
00045 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
00046   * @{
00047   */
00048 #define PVD_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVD threshold crossing */
00049 #define PVD_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVD threshold crossing        */
00050 #define PVD_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVD trigger                 */
00051 #define PVD_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVD trigger                */
00052 /**
00053   * @}
00054   */
00055 
00056 /**
00057   * @}
00058   */
00059 
00060 /* Private macro -------------------------------------------------------------*/
00061 /* Private variables ---------------------------------------------------------*/
00062 /* Private function prototypes -----------------------------------------------*/
00063 /* Exported functions --------------------------------------------------------*/
00064 
00065 /** @defgroup PWR_Exported_Functions PWR Exported Functions
00066   * @{
00067   */
00068 
00069 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00070   *  @brief    Initialization and de-initialization functions
00071   *
00072 @verbatim
00073  ===============================================================================
00074               ##### Initialization and de-initialization functions #####
00075  ===============================================================================
00076     [..]
00077 
00078 @endverbatim
00079   * @{
00080   */
00081 
00082 /**
00083   * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
00084   * @retval None
00085   */
00086 void HAL_PWR_DeInit(void)
00087 {
00088   __HAL_RCC_PWR_FORCE_RESET();
00089   __HAL_RCC_PWR_RELEASE_RESET();
00090 }
00091 
00092 /**
00093   * @brief Enable access to the backup domain
00094   *        (RTC registers, RTC backup data registers).
00095   * @note  After reset, the backup domain is protected against
00096   *        possible unwanted write accesses.
00097   * @note  RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
00098   *        In order to set or modify the RTC clock, the backup domain access must be
00099   *        disabled.
00100   * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the
00101   *        back-up domain.
00102   * @retval None
00103   */
00104 void HAL_PWR_EnableBkUpAccess(void)
00105 {
00106   SET_BIT(PWR->CR1, PWR_CR1_DBP);
00107 }
00108 
00109 /**
00110   * @brief Disable access to the backup domain
00111   *        (RTC registers, RTC backup data registers).
00112   * @retval None
00113   */
00114 void HAL_PWR_DisableBkUpAccess(void)
00115 {
00116   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
00117 }
00118 
00119 
00120 
00121 
00122 /**
00123   * @}
00124   */
00125 
00126 
00127 
00128 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
00129   *  @brief Low Power modes configuration functions
00130   *
00131 @verbatim
00132 
00133  ===============================================================================
00134                  ##### Peripheral Control functions #####
00135  ===============================================================================
00136 
00137      [..]
00138      *** PVD configuration ***
00139     =========================
00140     [..]
00141       (+) The PVD is used to monitor the VDD power supply by comparing it to a
00142           threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
00143 
00144       (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
00145           than the PVD threshold. This event is internally connected to the EXTI
00146           line16 and can generate an interrupt if enabled. This is done through
00147           __HAL_PVD_EXTI_ENABLE_IT() macro.
00148       (+) The PVD is stopped in Standby mode.
00149 
00150 
00151     *** WakeUp pin configuration ***
00152     ================================
00153     [..]
00154       (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
00155           The polarity of these pins can be set to configure event detection on high
00156           level (rising edge) or low level (falling edge).
00157 
00158 
00159 
00160     *** Low Power modes configuration ***
00161     =====================================
00162     [..]
00163       The devices feature 8 low-power modes:
00164       (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
00165       (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
00166       (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
00167       (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
00168       (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
00169       (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
00170       (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
00171       (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
00172       (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
00173 
00174 
00175    *** Low-power run mode ***
00176    ==========================
00177     [..]
00178       (+) Entry: (from main run mode)
00179         (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
00180 
00181       (+) Exit:
00182         (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
00183              then can the system clock frequency be increased above 2 MHz.
00184 
00185 
00186    *** Sleep mode / Low-power sleep mode ***
00187    =========================================
00188     [..]
00189       (+) Entry:
00190           The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
00191           in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
00192           (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
00193           (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
00194           In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
00195           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00196           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00197 
00198       (+) WFI Exit:
00199         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
00200              controller (NVIC) or any wake-up event.
00201 
00202       (+) WFE Exit:
00203         (++) Any wake-up event such as an EXTI line configured in event mode.
00204 
00205          [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
00206              the MCU is in Low-power Run mode.
00207 
00208    *** Stop 0, Stop 1 and Stop 2 modes ***
00209    ===============================
00210     [..]
00211       (+) Entry:
00212           The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
00213           (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
00214           (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
00215       (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
00216           (++) PWR_MAINREGULATOR_ON
00217           (++) PWR_LOWPOWERREGULATOR_ON
00218       (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
00219           (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
00220           (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
00221 
00222       (+) WFI Exit:
00223           (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
00224           (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
00225                when programmed in wakeup mode.
00226       (+) WFE Exit:
00227           (++) Any EXTI Line (Internal or External) configured in Event mode.
00228 
00229        [..]
00230           When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
00231           depending on the LPR bit setting.
00232           When exiting Stop 2 mode, the MCU is in Run mode.
00233 
00234    *** Standby mode ***
00235    ====================
00236      [..]
00237       The Standby mode offers two options:
00238       (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
00239         SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
00240         and Standby circuitry.
00241       (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
00242         SRAM and register contents are lost except for the RTC registers, RTC backup registers
00243         and Standby circuitry.
00244 
00245       (++) Entry:
00246           (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
00247                 SRAM1 and register contents are lost except for registers in the Backup domain and
00248                 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
00249                 To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
00250                 to set RRS bit.
00251 
00252       (++) Exit:
00253           (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
00254                 external reset in NRST pin, IWDG reset.
00255 
00256       [..]    After waking up from Standby mode, program execution restarts in the same way as after a Reset.
00257 
00258 
00259     *** Shutdown mode ***
00260    ======================
00261      [..]
00262       In Shutdown mode,
00263         voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
00264         SRAM and registers contents are lost except for backup domain registers.
00265 
00266       (+) Entry:
00267           The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
00268 
00269       (+) Exit:
00270           (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
00271                external reset in NRST pin.
00272 
00273          [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
00274 
00275 
00276    *** Auto-wakeup (AWU) from low-power mode ***
00277    =============================================
00278     [..]
00279       The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
00280       Wakeup event, a tamper event or a time-stamp event, without depending on
00281       an external interrupt (Auto-wakeup mode).
00282 
00283       (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
00284 
00285 
00286         (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
00287              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
00288 
00289         (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
00290              is necessary to configure the RTC to detect the tamper or time stamp event using the
00291              HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
00292 
00293         (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
00294               configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00295 
00296 @endverbatim
00297   * @{
00298   */
00299 
00300 
00301 
00302 /**
00303   * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
00304   * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
00305   *        configuration information.
00306   * @note Refer to the electrical characteristics of your device datasheet for
00307   *         more details about the voltage thresholds corresponding to each
00308   *         detection level.
00309   * @retval None
00310   */
00311 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
00312 {
00313   /* Check the parameters */
00314   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
00315   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
00316 
00317   /* Set PLS bits according to PVDLevel value */
00318   MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
00319 
00320   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00321   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
00322   __HAL_PWR_PVD_EXTI_DISABLE_IT();
00323   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00324   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
00325 
00326   /* Configure interrupt mode */
00327   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
00328   {
00329     __HAL_PWR_PVD_EXTI_ENABLE_IT();
00330   }
00331 
00332   /* Configure event mode */
00333   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
00334   {
00335     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
00336   }
00337 
00338   /* Configure the edge */
00339   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
00340   {
00341     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
00342   }
00343 
00344   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
00345   {
00346     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00347   }
00348 
00349   return HAL_OK;
00350 }
00351 
00352 
00353 /**
00354   * @brief Enable the Power Voltage Detector (PVD).
00355   * @retval None
00356   */
00357 void HAL_PWR_EnablePVD(void)
00358 {
00359   SET_BIT(PWR->CR2, PWR_CR2_PVDE);
00360 }
00361 
00362 /**
00363   * @brief Disable the Power Voltage Detector (PVD).
00364   * @retval None
00365   */
00366 void HAL_PWR_DisablePVD(void)
00367 {
00368   CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
00369 }
00370 
00371 
00372 
00373 
00374 /**
00375   * @brief Enable the WakeUp PINx functionality.
00376   * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
00377   *         This parameter can be one of the following legacy values which set the default polarity
00378   *         i.e. detection on high level (rising edge):
00379   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
00380   *
00381   *         or one of the following value where the user can explicitly specify the enabled pin and
00382   *         the chosen polarity:
00383   *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
00384   *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
00385   *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
00386   *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
00387   *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
00388   * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
00389   * @retval None
00390   */
00391 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
00392 {
00393   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
00394 
00395   /* Specifies the Wake-Up pin polarity for the event detection
00396     (rising or falling edge) */
00397   MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
00398 
00399   /* Enable wake-up pin */
00400   SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
00401 
00402 
00403 }
00404 
00405 /**
00406   * @brief Disable the WakeUp PINx functionality.
00407   * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
00408   *         This parameter can be one of the following values:
00409   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
00410   * @retval None
00411   */
00412 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
00413 {
00414   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00415 
00416   CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
00417 }
00418 
00419 
00420 /**
00421   * @brief Enter Sleep or Low-power Sleep mode.
00422   * @note  In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
00423   * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
00424   *          This parameter can be one of the following values:
00425   *            @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
00426   *            @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
00427   * @note  Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
00428   *        in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
00429   *        to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
00430   *        Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
00431   *        Additionally, the clock frequency must be reduced below 2 MHz.
00432   *        Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
00433   *        be done before calling HAL_PWR_EnterSLEEPMode() API.
00434   * @note  When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
00435   *        Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
00436   * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
00437   *           This parameter can be one of the following values:
00438   *            @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
00439   *            @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
00440   * @note  When WFI entry is used, tick interrupt have to be disabled if not desired as
00441   *        the interrupt wake up source.
00442   * @retval None
00443   */
00444 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
00445 {
00446   /* Check the parameters */
00447   assert_param(IS_PWR_REGULATOR(Regulator));
00448   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
00449 
00450   /* Set Regulator parameter */
00451   if (Regulator == PWR_MAINREGULATOR_ON)
00452   {
00453     /* If in low-power run mode at this point, exit it */
00454     if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
00455     {
00456       if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
00457       {
00458         return ;
00459       }
00460     }
00461     /* Regulator now in main mode. */
00462   }
00463   else
00464   {
00465     /* If in run mode, first move to low-power run mode.
00466        The system clock frequency must be below 2 MHz at this point. */
00467     if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
00468     {
00469       HAL_PWREx_EnableLowPowerRunMode();
00470     }
00471   }
00472 
00473   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00474   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00475 
00476   /* Select SLEEP mode entry -------------------------------------------------*/
00477   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
00478   {
00479     /* Request Wait For Interrupt */
00480     __WFI();
00481   }
00482   else
00483   {
00484     /* Request Wait For Event */
00485     __SEV();
00486     __WFE();
00487     __WFE();
00488   }
00489 
00490 }
00491 
00492 
00493 /**
00494   * @brief Enter Stop mode
00495   * @note  This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
00496   *        on devices where only "Stop mode" is mentioned with main or low power regulator ON.
00497   * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
00498   * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,
00499   *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
00500   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
00501   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
00502   *        only to the peripheral requesting it.
00503   *        SRAM1, SRAM2 and register contents are preserved.
00504   *        The BOR is available.
00505   *        The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
00506   * @note  When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
00507   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
00508   *         is set; the MSI oscillator is selected if STOPWUCK is cleared.
00509   * @note  When the voltage regulator operates in low power mode (Stop 1), an additional
00510   *         startup delay is incurred when waking up.
00511   *         By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
00512   *         is higher although the startup time is reduced.
00513   * @param Regulator: Specifies the regulator state in Stop mode.
00514   *          This parameter can be one of the following values:
00515   *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
00516   *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power regulator ON)
00517   * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
00518   *          This parameter can be one of the following values:
00519   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI instruction.
00520   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE instruction.
00521   * @retval None
00522   */
00523 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00524 {
00525   /* Check the parameters */
00526   assert_param(IS_PWR_REGULATOR(Regulator));
00527 
00528   if(Regulator == PWR_LOWPOWERREGULATOR_ON)
00529   {
00530     HAL_PWREx_EnterSTOP1Mode(STOPEntry);
00531   }
00532   else
00533   {
00534     HAL_PWREx_EnterSTOP0Mode(STOPEntry);
00535   }
00536 }
00537 
00538 /**
00539   * @brief Enter Standby mode.
00540   * @note  In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
00541   *        off. The voltage regulator is disabled, except when SRAM2 content is preserved
00542   *        in which case the regulator is in low-power mode.
00543   *        SRAM1 and register contents are lost except for registers in the Backup domain and
00544   *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
00545   *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
00546   *        to set RRS bit.
00547   *        The BOR is available.
00548   * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
00549   *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
00550   *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
00551   *        same.
00552   *        These states are effective in Standby mode only if APC bit is set through
00553   *        HAL_PWREx_EnablePullUpPullDownConfig() API.
00554   * @retval None
00555   */
00556 void HAL_PWR_EnterSTANDBYMode(void)
00557 {
00558   /* Set Stand-by mode */
00559   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
00560 
00561   /* Set SLEEPDEEP bit of Cortex System Control Register */
00562   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00563 
00564 /* This option is used to ensure that store operations are completed */
00565 #if defined ( __CC_ARM)
00566   __force_stores();
00567 #endif
00568   /* Request Wait For Interrupt */
00569   __WFI();
00570 }
00571 
00572 
00573 
00574 /**
00575   * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
00576   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00577   *       re-enters SLEEP mode when an interruption handling is over.
00578   *       Setting this bit is useful when the processor is expected to run only on
00579   *       interruptions handling.
00580   * @retval None
00581   */
00582 void HAL_PWR_EnableSleepOnExit(void)
00583 {
00584   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00585   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00586 }
00587 
00588 
00589 /**
00590   * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
00591   * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00592   *       re-enters SLEEP mode when an interruption handling is over.
00593   * @retval None
00594   */
00595 void HAL_PWR_DisableSleepOnExit(void)
00596 {
00597   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00598   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00599 }
00600 
00601 
00602 
00603 /**
00604   * @brief Enable CORTEX M4 SEVONPEND bit.
00605   * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
00606   *       WFE to wake up when an interrupt moves from inactive to pended.
00607   * @retval None
00608   */
00609 void HAL_PWR_EnableSEVOnPend(void)
00610 {
00611   /* Set SEVONPEND bit of Cortex System Control Register */
00612   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00613 }
00614 
00615 
00616 /**
00617   * @brief Disable CORTEX M4 SEVONPEND bit.
00618   * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
00619   *       WFE to wake up when an interrupt moves from inactive to pended.
00620   * @retval None
00621   */
00622 void HAL_PWR_DisableSEVOnPend(void)
00623 {
00624   /* Clear SEVONPEND bit of Cortex System Control Register */
00625   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00626 }
00627 
00628 
00629 
00630 
00631 
00632 /**
00633   * @brief PWR PVD interrupt callback
00634   * @retval None
00635   */
00636 __weak void HAL_PWR_PVDCallback(void)
00637 {
00638   /* NOTE : This function should not be modified; when the callback is needed,
00639             the HAL_PWR_PVDCallback can be implemented in the user file
00640    */
00641 }
00642 
00643 /**
00644   * @}
00645   */
00646 
00647 /**
00648   * @}
00649   */
00650 
00651 #endif /* HAL_PWR_MODULE_ENABLED */
00652 /**
00653   * @}
00654   */
00655 
00656 /**
00657   * @}
00658   */