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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_rcc_ex.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC HAL Extended module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file in 00013 * the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 ****************************************************************************** 00016 */ 00017 00018 /* Define to prevent recursive inclusion -------------------------------------*/ 00019 #ifndef STM32L4xx_HAL_RCC_EX_H 00020 #define STM32L4xx_HAL_RCC_EX_H 00021 00022 #ifdef __cplusplus 00023 extern "C" { 00024 #endif 00025 00026 /* Includes ------------------------------------------------------------------*/ 00027 #include "stm32l4xx_hal_def.h" 00028 00029 /** @addtogroup STM32L4xx_HAL_Driver 00030 * @{ 00031 */ 00032 00033 /** @addtogroup RCCEx 00034 * @{ 00035 */ 00036 00037 /* Exported types ------------------------------------------------------------*/ 00038 00039 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 00040 * @{ 00041 */ 00042 00043 #if defined(RCC_PLLSAI1_SUPPORT) 00044 /** 00045 * @brief PLLSAI1 Clock structure definition 00046 */ 00047 typedef struct 00048 { 00049 00050 uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source. 00051 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 00052 00053 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 00054 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. 00055 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 00056 #else 00057 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. 00058 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ 00059 #endif 00060 00061 uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. 00062 This parameter must be a number between 8 and 86 or 127 depending on devices. */ 00063 00064 uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock. 00065 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 00066 00067 uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. 00068 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 00069 00070 uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock. 00071 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 00072 00073 uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. 00074 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ 00075 }RCC_PLLSAI1InitTypeDef; 00076 #endif /* RCC_PLLSAI1_SUPPORT */ 00077 00078 #if defined(RCC_PLLSAI2_SUPPORT) 00079 /** 00080 * @brief PLLSAI2 Clock structure definition 00081 */ 00082 typedef struct 00083 { 00084 00085 uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source. 00086 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 00087 00088 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 00089 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. 00090 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 00091 #else 00092 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. 00093 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ 00094 #endif 00095 00096 uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. 00097 This parameter must be a number between 8 and 86 or 127 depending on devices. */ 00098 00099 uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. 00100 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 00101 00102 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 00103 uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock. 00104 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 00105 #endif 00106 00107 uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock. 00108 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 00109 00110 uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled. 00111 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */ 00112 }RCC_PLLSAI2InitTypeDef; 00113 00114 #endif /* RCC_PLLSAI2_SUPPORT */ 00115 00116 /** 00117 * @brief RCC extended clocks structure definition 00118 */ 00119 typedef struct 00120 { 00121 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00122 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00123 #if defined(RCC_PLLSAI1_SUPPORT) 00124 00125 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. 00126 This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ 00127 #endif /* RCC_PLLSAI1_SUPPORT */ 00128 #if defined(RCC_PLLSAI2_SUPPORT) 00129 00130 RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. 00131 This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */ 00132 00133 #endif /* RCC_PLLSAI2_SUPPORT */ 00134 00135 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 00136 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 00137 00138 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 00139 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 00140 00141 #if defined(USART3) 00142 00143 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 00144 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 00145 00146 #endif /* USART3 */ 00147 00148 #if defined(UART4) 00149 00150 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 00151 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 00152 00153 #endif /* UART4 */ 00154 00155 #if defined(UART5) 00156 00157 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 00158 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 00159 00160 #endif /* UART5 */ 00161 00162 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 00163 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 00164 00165 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 00166 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 00167 00168 #if defined(I2C2) 00169 00170 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 00171 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 00172 00173 #endif /* I2C2 */ 00174 00175 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 00176 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 00177 00178 #if defined(I2C4) 00179 00180 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 00181 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 00182 00183 #endif /* I2C4 */ 00184 00185 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 00186 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 00187 00188 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 00189 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 00190 #if defined(SAI1) 00191 00192 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 00193 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 00194 #endif /* SAI1 */ 00195 00196 #if defined(SAI2) 00197 00198 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. 00199 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 00200 00201 #endif /* SAI2 */ 00202 00203 #if defined(USB_OTG_FS) || defined(USB) 00204 00205 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG). 00206 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 00207 00208 #endif /* USB_OTG_FS || USB */ 00209 00210 #if defined(SDMMC1) 00211 00212 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG). 00213 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ 00214 00215 #endif /* SDMMC1 */ 00216 00217 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). 00218 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 00219 00220 #if !defined(STM32L412xx) && !defined(STM32L422xx) 00221 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. 00222 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 00223 #endif /* !STM32L412xx && !STM32L422xx */ 00224 00225 #if defined(SWPMI1) 00226 00227 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source. 00228 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ 00229 00230 #endif /* SWPMI1 */ 00231 00232 #if defined(DFSDM1_Filter0) 00233 00234 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source. 00235 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ 00236 00237 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00238 uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source. 00239 This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ 00240 00241 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00242 00243 #endif /* DFSDM1_Filter0 */ 00244 00245 #if defined(LTDC) 00246 00247 uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source. 00248 This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ 00249 00250 #endif /* LTDC */ 00251 00252 #if defined(DSI) 00253 00254 uint32_t DsiClockSelection; /*!< Specifies DSI clock source. 00255 This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ 00256 00257 #endif /* DSI */ 00258 00259 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00260 00261 uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. 00262 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 00263 00264 #endif 00265 00266 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 00267 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00268 }RCC_PeriphCLKInitTypeDef; 00269 00270 #if defined(CRS) 00271 00272 /** 00273 * @brief RCC_CRS Init structure definition 00274 */ 00275 typedef struct 00276 { 00277 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 00278 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 00279 00280 uint32_t Source; /*!< Specifies the SYNC signal source. 00281 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 00282 00283 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 00284 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 00285 00286 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 00287 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 00288 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 00289 00290 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 00291 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 00292 00293 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 00294 This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise, 00295 or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 00296 00297 }RCC_CRSInitTypeDef; 00298 00299 /** 00300 * @brief RCC_CRS Synchronization structure definition 00301 */ 00302 typedef struct 00303 { 00304 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 00305 This parameter must be a number between 0 and 0xFFFF */ 00306 00307 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 00308 This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise */ 00309 00310 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 00311 value latched in the time of the last SYNC event. 00312 This parameter must be a number between 0 and 0xFFFF */ 00313 00314 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 00315 frequency error counter latched in the time of the last SYNC event. 00316 It shows whether the actual frequency is below or above the target. 00317 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 00318 00319 }RCC_CRSSynchroInfoTypeDef; 00320 00321 #endif /* CRS */ 00322 /** 00323 * @} 00324 */ 00325 00326 /* Exported constants --------------------------------------------------------*/ 00327 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 00328 * @{ 00329 */ 00330 00331 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 00332 * @{ 00333 */ 00334 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 00335 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 00336 /** 00337 * @} 00338 */ 00339 00340 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 00341 * @{ 00342 */ 00343 #define RCC_PERIPHCLK_USART1 0x00000001U 00344 #define RCC_PERIPHCLK_USART2 0x00000002U 00345 #if defined(USART3) 00346 #define RCC_PERIPHCLK_USART3 0x00000004U 00347 #endif 00348 #if defined(UART4) 00349 #define RCC_PERIPHCLK_UART4 0x00000008U 00350 #endif 00351 #if defined(UART5) 00352 #define RCC_PERIPHCLK_UART5 0x00000010U 00353 #endif 00354 #define RCC_PERIPHCLK_LPUART1 0x00000020U 00355 #define RCC_PERIPHCLK_I2C1 0x00000040U 00356 #if defined(I2C2) 00357 #define RCC_PERIPHCLK_I2C2 0x00000080U 00358 #endif 00359 #define RCC_PERIPHCLK_I2C3 0x00000100U 00360 #define RCC_PERIPHCLK_LPTIM1 0x00000200U 00361 #define RCC_PERIPHCLK_LPTIM2 0x00000400U 00362 #if defined(SAI1) 00363 #define RCC_PERIPHCLK_SAI1 0x00000800U 00364 #endif 00365 #if defined(SAI2) 00366 #define RCC_PERIPHCLK_SAI2 0x00001000U 00367 #endif 00368 #if defined(USB_OTG_FS) || defined(USB) 00369 #define RCC_PERIPHCLK_USB 0x00002000U 00370 #endif 00371 #define RCC_PERIPHCLK_ADC 0x00004000U 00372 #if defined(SWPMI1) 00373 #define RCC_PERIPHCLK_SWPMI1 0x00008000U 00374 #endif 00375 #if defined(DFSDM1_Filter0) 00376 #define RCC_PERIPHCLK_DFSDM1 0x00010000U 00377 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00378 #define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U 00379 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00380 #endif 00381 #define RCC_PERIPHCLK_RTC 0x00020000U 00382 #define RCC_PERIPHCLK_RNG 0x00040000U 00383 #if defined(SDMMC1) 00384 #define RCC_PERIPHCLK_SDMMC1 0x00080000U 00385 #endif 00386 #if defined(I2C4) 00387 #define RCC_PERIPHCLK_I2C4 0x00100000U 00388 #endif 00389 #if defined(LTDC) 00390 #define RCC_PERIPHCLK_LTDC 0x00400000U 00391 #endif 00392 #if defined(DSI) 00393 #define RCC_PERIPHCLK_DSI 0x00800000U 00394 #endif 00395 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00396 #define RCC_PERIPHCLK_OSPI 0x01000000U 00397 #endif 00398 /** 00399 * @} 00400 */ 00401 00402 00403 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 00404 * @{ 00405 */ 00406 #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U 00407 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 00408 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 00409 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) 00410 /** 00411 * @} 00412 */ 00413 00414 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 00415 * @{ 00416 */ 00417 #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U 00418 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 00419 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 00420 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) 00421 /** 00422 * @} 00423 */ 00424 00425 #if defined(USART3) 00426 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 00427 * @{ 00428 */ 00429 #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U 00430 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 00431 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 00432 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) 00433 /** 00434 * @} 00435 */ 00436 #endif /* USART3 */ 00437 00438 #if defined(UART4) 00439 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 00440 * @{ 00441 */ 00442 #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U 00443 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 00444 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 00445 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) 00446 /** 00447 * @} 00448 */ 00449 #endif /* UART4 */ 00450 00451 #if defined(UART5) 00452 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 00453 * @{ 00454 */ 00455 #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U 00456 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 00457 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 00458 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) 00459 /** 00460 * @} 00461 */ 00462 #endif /* UART5 */ 00463 00464 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 00465 * @{ 00466 */ 00467 #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U 00468 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 00469 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 00470 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) 00471 /** 00472 * @} 00473 */ 00474 00475 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 00476 * @{ 00477 */ 00478 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U 00479 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 00480 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 00481 /** 00482 * @} 00483 */ 00484 00485 #if defined(I2C2) 00486 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 00487 * @{ 00488 */ 00489 #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U 00490 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 00491 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 00492 /** 00493 * @} 00494 */ 00495 #endif /* I2C2 */ 00496 00497 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 00498 * @{ 00499 */ 00500 #define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U 00501 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 00502 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 00503 /** 00504 * @} 00505 */ 00506 00507 #if defined(I2C4) 00508 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 00509 * @{ 00510 */ 00511 #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U 00512 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 00513 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 00514 /** 00515 * @} 00516 */ 00517 #endif /* I2C4 */ 00518 00519 #if defined(SAI1) 00520 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 00521 * @{ 00522 */ 00523 #define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U 00524 #if defined(RCC_PLLSAI2_SUPPORT) 00525 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00526 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 00527 #else 00528 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0 00529 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00530 #endif /* RCC_PLLSAI2_SUPPORT */ 00531 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00532 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1 00533 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) 00534 #define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 00535 #else 00536 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1 00537 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL 00538 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00539 /** 00540 * @} 00541 */ 00542 #endif /* SAI1 */ 00543 00544 #if defined(SAI2) 00545 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 00546 * @{ 00547 */ 00548 #define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U 00549 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00550 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 00551 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 00552 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) 00553 #define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 00554 #else 00555 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0 00556 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1 00557 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL 00558 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00559 /** 00560 * @} 00561 */ 00562 #endif /* SAI2 */ 00563 00564 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 00565 * @{ 00566 */ 00567 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 00568 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 00569 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 00570 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL 00571 /** 00572 * @} 00573 */ 00574 00575 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 00576 * @{ 00577 */ 00578 #define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U 00579 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 00580 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 00581 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL 00582 /** 00583 * @} 00584 */ 00585 00586 #if defined(SDMMC1) 00587 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source 00588 * @{ 00589 */ 00590 #if defined(RCC_HSI48_SUPPORT) 00591 #define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock selected as SDMMC1 clock */ 00592 #else 00593 #define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /*!< No clock selected as SDMMC1 clock */ 00594 #endif /* RCC_HSI48_SUPPORT */ 00595 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */ 00596 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */ 00597 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock selected as SDMMC1 clock */ 00598 #if defined(RCC_CCIPR2_SDMMCSEL) 00599 #define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "P" clock selected as SDMMC1 kernel clock */ 00600 #endif /* RCC_CCIPR2_SDMMCSEL */ 00601 /** 00602 * @} 00603 */ 00604 #endif /* SDMMC1 */ 00605 00606 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source 00607 * @{ 00608 */ 00609 #if defined(RCC_HSI48_SUPPORT) 00610 #define RCC_RNGCLKSOURCE_HSI48 0x00000000U 00611 #else 00612 #define RCC_RNGCLKSOURCE_NONE 0x00000000U 00613 #endif /* RCC_HSI48_SUPPORT */ 00614 #if defined(RCC_PLLSAI1_SUPPORT) 00615 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 00616 #endif /* RCC_PLLSAI1_SUPPORT */ 00617 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 00618 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL 00619 /** 00620 * @} 00621 */ 00622 00623 #if defined(USB_OTG_FS) || defined(USB) 00624 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 00625 * @{ 00626 */ 00627 #if defined(RCC_HSI48_SUPPORT) 00628 #define RCC_USBCLKSOURCE_HSI48 0x00000000U 00629 #else 00630 #define RCC_USBCLKSOURCE_NONE 0x00000000U 00631 #endif /* RCC_HSI48_SUPPORT */ 00632 #if defined(RCC_PLLSAI1_SUPPORT) 00633 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 00634 #endif /* RCC_PLLSAI1_SUPPORT */ 00635 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 00636 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL 00637 /** 00638 * @} 00639 */ 00640 #endif /* USB_OTG_FS || USB */ 00641 00642 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source 00643 * @{ 00644 */ 00645 #define RCC_ADCCLKSOURCE_NONE 0x00000000U 00646 #if defined(RCC_PLLSAI1_SUPPORT) 00647 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 00648 #endif /* RCC_PLLSAI1_SUPPORT */ 00649 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 00650 #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 00651 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 00652 #if defined(RCC_CCIPR_ADCSEL) 00653 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL 00654 #else 00655 #define RCC_ADCCLKSOURCE_SYSCLK 0x30000000U 00656 #endif /* RCC_CCIPR_ADCSEL */ 00657 /** 00658 * @} 00659 */ 00660 00661 #if defined(SWPMI1) 00662 /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source 00663 * @{ 00664 */ 00665 #define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U 00666 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL 00667 /** 00668 * @} 00669 */ 00670 #endif /* SWPMI1 */ 00671 00672 #if defined(DFSDM1_Filter0) 00673 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source 00674 * @{ 00675 */ 00676 #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U 00677 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00678 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL 00679 #else 00680 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL 00681 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00682 /** 00683 * @} 00684 */ 00685 00686 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00687 /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source 00688 * @{ 00689 */ 00690 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U 00691 #define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 00692 #define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 00693 /** 00694 * @} 00695 */ 00696 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00697 #endif /* DFSDM1_Filter0 */ 00698 00699 #if defined(LTDC) 00700 /** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source 00701 * @{ 00702 */ 00703 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U 00704 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 00705 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 00706 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR 00707 /** 00708 * @} 00709 */ 00710 #endif /* LTDC */ 00711 00712 #if defined(DSI) 00713 /** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source 00714 * @{ 00715 */ 00716 #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U 00717 #define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL 00718 /** 00719 * @} 00720 */ 00721 #endif /* DSI */ 00722 00723 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00724 /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source 00725 * @{ 00726 */ 00727 #define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U 00728 #define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 00729 #define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 00730 /** 00731 * @} 00732 */ 00733 #endif /* OCTOSPI1 || OCTOSPI2 */ 00734 00735 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 00736 * @{ 00737 */ 00738 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ 00739 /** 00740 * @} 00741 */ 00742 00743 #if defined(CRS) 00744 00745 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 00746 * @{ 00747 */ 00748 #define RCC_CRS_NONE 0x00000000U 00749 #define RCC_CRS_TIMEOUT 0x00000001U 00750 #define RCC_CRS_SYNCOK 0x00000002U 00751 #define RCC_CRS_SYNCWARN 0x00000004U 00752 #define RCC_CRS_SYNCERR 0x00000008U 00753 #define RCC_CRS_SYNCMISS 0x00000010U 00754 #define RCC_CRS_TRIMOVF 0x00000020U 00755 /** 00756 * @} 00757 */ 00758 00759 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 00760 * @{ 00761 */ 00762 #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ 00763 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 00764 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 00765 /** 00766 * @} 00767 */ 00768 00769 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 00770 * @{ 00771 */ 00772 #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ 00773 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 00774 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 00775 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 00776 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 00777 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 00778 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 00779 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 00780 /** 00781 * @} 00782 */ 00783 00784 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 00785 * @{ 00786 */ 00787 #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ 00788 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 00789 /** 00790 * @} 00791 */ 00792 00793 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 00794 * @{ 00795 */ 00796 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 00797 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 00798 /** 00799 * @} 00800 */ 00801 00802 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 00803 * @{ 00804 */ 00805 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 00806 /** 00807 * @} 00808 */ 00809 00810 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 00811 * @{ 00812 */ 00813 #if defined(STM32L412xx) || defined(STM32L422xx) 00814 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. 00815 The trimming step is specified in the product datasheet. A higher TRIM value 00816 corresponds to a higher output frequency */ 00817 #else 00818 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. 00819 The trimming step is specified in the product datasheet. A higher TRIM value 00820 corresponds to a higher output frequency */ 00821 #endif 00822 /** 00823 * @} 00824 */ 00825 00826 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 00827 * @{ 00828 */ 00829 #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ 00830 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 00831 /** 00832 * @} 00833 */ 00834 00835 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 00836 * @{ 00837 */ 00838 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 00839 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 00840 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 00841 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 00842 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 00843 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 00844 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 00845 00846 /** 00847 * @} 00848 */ 00849 00850 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 00851 * @{ 00852 */ 00853 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 00854 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 00855 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 00856 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 00857 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 00858 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 00859 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 00860 00861 /** 00862 * @} 00863 */ 00864 00865 #endif /* CRS */ 00866 00867 /** 00868 * @} 00869 */ 00870 00871 /* Exported macros -----------------------------------------------------------*/ 00872 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 00873 * @{ 00874 */ 00875 00876 #if defined(RCC_PLLSAI1_SUPPORT) 00877 00878 /** 00879 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. 00880 * 00881 * @note This function must be used only when the PLLSAI1 is disabled. 00882 * @note PLLSAI1 clock source is common with the main PLL (configured through 00883 * __HAL_RCC_PLL_CONFIG() macro) 00884 * 00885 @if STM32L4S9xx 00886 * @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock. 00887 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 00888 * 00889 @endif 00890 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. 00891 * This parameter must be a number between 8 and 86 or 127 depending on devices. 00892 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO 00893 * output frequency is between 64 and 344 MHz. 00894 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N 00895 * 00896 * @param __PLLSAI1P__ specifies the division factor for SAI clock. 00897 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx 00898 * else (2 to 31). 00899 * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P 00900 * 00901 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 00902 * This parameter must be in the range (2, 4, 6 or 8). 00903 * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q 00904 * 00905 * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock. 00906 * This parameter must be in the range (2, 4, 6 or 8). 00907 * ADC clock frequency = f(PLLSAI1) / PLLSAI1R 00908 * 00909 * @retval None 00910 */ 00911 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 00912 00913 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 00914 00915 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 00916 MODIFY_REG(RCC->PLLSAI1CFGR, \ 00917 (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \ 00918 RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \ 00919 ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \ 00920 ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 00921 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 00922 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 00923 ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))) 00924 00925 #else 00926 00927 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 00928 MODIFY_REG(RCC->PLLSAI1CFGR, \ 00929 (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \ 00930 RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \ 00931 ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \ 00932 ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 00933 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 00934 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 00935 (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos))) 00936 00937 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 00938 00939 #else 00940 00941 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 00942 00943 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 00944 MODIFY_REG(RCC->PLLSAI1CFGR, \ 00945 (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \ 00946 RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \ 00947 (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 00948 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 00949 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 00950 ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))) 00951 00952 #else 00953 00954 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 00955 MODIFY_REG(RCC->PLLSAI1CFGR, \ 00956 (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \ 00957 RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \ 00958 (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 00959 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 00960 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 00961 (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos))) 00962 00963 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 00964 00965 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 00966 00967 /** 00968 * @brief Macro to configure the PLLSAI1 clock multiplication factor N. 00969 * 00970 * @note This function must be used only when the PLLSAI1 is disabled. 00971 * @note PLLSAI1 clock source is common with the main PLL (configured through 00972 * __HAL_RCC_PLL_CONFIG() macro) 00973 * 00974 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. 00975 * This parameter must be a number between 8 and 86 or 127 depending on devices. 00976 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO 00977 * output frequency is between 64 and 344 MHz. 00978 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N 00979 * 00980 * @retval None 00981 */ 00982 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ 00983 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) 00984 00985 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 00986 00987 /** @brief Macro to configure the PLLSAI1 input clock division factor M. 00988 * 00989 * @note This function must be used only when the PLLSAI1 is disabled. 00990 * @note PLLSAI1 clock source is common with the main PLL (configured through 00991 * __HAL_RCC_PLL_CONFIG() macro) 00992 * 00993 * @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock. 00994 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 00995 * 00996 * @retval None 00997 */ 00998 00999 #define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \ 01000 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) 01001 01002 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 01003 01004 /** @brief Macro to configure the PLLSAI1 clock division factor P. 01005 * 01006 * @note This function must be used only when the PLLSAI1 is disabled. 01007 * @note PLLSAI1 clock source is common with the main PLL (configured through 01008 * __HAL_RCC_PLL_CONFIG() macro) 01009 * 01010 * @param __PLLSAI1P__ specifies the division factor for SAI clock. 01011 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx 01012 * else (2 to 31). 01013 * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P 01014 * 01015 * @retval None 01016 */ 01017 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 01018 01019 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ 01020 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) 01021 01022 #else 01023 01024 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ 01025 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) 01026 01027 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 01028 01029 /** @brief Macro to configure the PLLSAI1 clock division factor Q. 01030 * 01031 * @note This function must be used only when the PLLSAI1 is disabled. 01032 * @note PLLSAI1 clock source is common with the main PLL (configured through 01033 * __HAL_RCC_PLL_CONFIG() macro) 01034 * 01035 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 01036 * This parameter must be in the range (2, 4, 6 or 8). 01037 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q 01038 * 01039 * @retval None 01040 */ 01041 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ 01042 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) 01043 01044 /** @brief Macro to configure the PLLSAI1 clock division factor R. 01045 * 01046 * @note This function must be used only when the PLLSAI1 is disabled. 01047 * @note PLLSAI1 clock source is common with the main PLL (configured through 01048 * __HAL_RCC_PLL_CONFIG() macro) 01049 * 01050 * @param __PLLSAI1R__ specifies the division factor for ADC clock. 01051 * This parameter must be in the range (2, 4, 6 or 8) 01052 * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R 01053 * 01054 * @retval None 01055 */ 01056 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ 01057 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) 01058 01059 /** 01060 * @brief Macros to enable or disable the PLLSAI1. 01061 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. 01062 * @retval None 01063 */ 01064 01065 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON) 01066 01067 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON) 01068 01069 /** 01070 * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). 01071 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 01072 * This is mainly used to save Power. 01073 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 01074 * This parameter can be one or a combination of the following values: 01075 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve 01076 * high-quality audio performance on SAI interface in case. 01077 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), 01078 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). 01079 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. 01080 * @retval None 01081 */ 01082 01083 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 01084 01085 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 01086 01087 /** 01088 * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). 01089 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 01090 * This parameter can be one of the following values: 01091 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve 01092 * high-quality audio performance on SAI interface in case. 01093 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), 01094 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). 01095 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. 01096 * @retval SET / RESET 01097 */ 01098 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 01099 01100 #endif /* RCC_PLLSAI1_SUPPORT */ 01101 01102 #if defined(RCC_PLLSAI2_SUPPORT) 01103 01104 /** 01105 * @brief Macro to configure the PLLSAI2 clock multiplication and division factors. 01106 * 01107 * @note This function must be used only when the PLLSAI2 is disabled. 01108 * @note PLLSAI2 clock source is common with the main PLL (configured through 01109 * __HAL_RCC_PLL_CONFIG() macro) 01110 * 01111 @if STM32L4S9xx 01112 * @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock. 01113 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 01114 * 01115 @endif 01116 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. 01117 * This parameter must be a number between 8 and 86. 01118 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO 01119 * output frequency is between 64 and 344 MHz. 01120 * 01121 * @param __PLLSAI2P__ specifies the division factor for SAI clock. 01122 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx 01123 * else (2 to 31). 01124 * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P 01125 * 01126 @if STM32L4S9xx 01127 * @param __PLLSAI2Q__ specifies the division factor for DSI clock. 01128 * This parameter must be in the range (2, 4, 6 or 8). 01129 * DSI clock frequency = f(PLLSAI2) / PLLSAI2Q 01130 * 01131 @endif 01132 * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock. 01133 * This parameter must be in the range (2, 4, 6 or 8). 01134 * 01135 * @retval None 01136 */ 01137 01138 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01139 01140 # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) 01141 01142 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ 01143 MODIFY_REG(RCC->PLLSAI2CFGR, \ 01144 (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ 01145 RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ 01146 ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ 01147 ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 01148 ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ 01149 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 01150 ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) 01151 01152 # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 01153 01154 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 01155 MODIFY_REG(RCC->PLLSAI2CFGR, \ 01156 (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ 01157 RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ 01158 ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ 01159 ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 01160 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 01161 ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) 01162 01163 # else 01164 01165 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 01166 MODIFY_REG(RCC->PLLSAI2CFGR, \ 01167 (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ 01168 RCC_PLLSAI2CFGR_PLLSAI2R), \ 01169 ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ 01170 ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 01171 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 01172 (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos))) 01173 01174 # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ 01175 01176 #else 01177 01178 # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) 01179 01180 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ 01181 MODIFY_REG(RCC->PLLSAI2CFGR, \ 01182 (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ 01183 RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ 01184 (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 01185 ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ 01186 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 01187 ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) 01188 01189 # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 01190 01191 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 01192 MODIFY_REG(RCC->PLLSAI2CFGR, \ 01193 (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ 01194 RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ 01195 (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 01196 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 01197 ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) 01198 01199 # else 01200 01201 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 01202 MODIFY_REG(RCC->PLLSAI2CFGR, \ 01203 (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ 01204 RCC_PLLSAI2CFGR_PLLSAI2R), \ 01205 (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 01206 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 01207 (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos))) 01208 01209 # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ 01210 01211 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 01212 01213 01214 /** 01215 * @brief Macro to configure the PLLSAI2 clock multiplication factor N. 01216 * 01217 * @note This function must be used only when the PLLSAI2 is disabled. 01218 * @note PLLSAI2 clock source is common with the main PLL (configured through 01219 * __HAL_RCC_PLL_CONFIG() macro) 01220 * 01221 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. 01222 * This parameter must be a number between 8 and 86. 01223 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO 01224 * output frequency is between 64 and 344 MHz. 01225 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N 01226 * 01227 * @retval None 01228 */ 01229 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ 01230 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) 01231 01232 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01233 01234 /** @brief Macro to configure the PLLSAI2 input clock division factor M. 01235 * 01236 * @note This function must be used only when the PLLSAI2 is disabled. 01237 * @note PLLSAI2 clock source is common with the main PLL (configured through 01238 * __HAL_RCC_PLL_CONFIG() macro) 01239 * 01240 * @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock. 01241 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 01242 * 01243 * @retval None 01244 */ 01245 01246 #define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \ 01247 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) 01248 01249 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 01250 01251 /** @brief Macro to configure the PLLSAI2 clock division factor P. 01252 * 01253 * @note This function must be used only when the PLLSAI2 is disabled. 01254 * @note PLLSAI2 clock source is common with the main PLL (configured through 01255 * __HAL_RCC_PLL_CONFIG() macro) 01256 * 01257 * @param __PLLSAI2P__ specifies the division factor. 01258 * This parameter must be a number in the range (7 or 17). 01259 * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__ 01260 * 01261 * @retval None 01262 */ 01263 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ 01264 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) 01265 01266 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 01267 01268 /** @brief Macro to configure the PLLSAI2 clock division factor Q. 01269 * 01270 * @note This function must be used only when the PLLSAI2 is disabled. 01271 * @note PLLSAI2 clock source is common with the main PLL (configured through 01272 * __HAL_RCC_PLL_CONFIG() macro) 01273 * 01274 * @param __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 01275 * This parameter must be in the range (2, 4, 6 or 8). 01276 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q 01277 * 01278 * @retval None 01279 */ 01280 #define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \ 01281 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) 01282 01283 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 01284 01285 /** @brief Macro to configure the PLLSAI2 clock division factor R. 01286 * 01287 * @note This function must be used only when the PLLSAI2 is disabled. 01288 * @note PLLSAI2 clock source is common with the main PLL (configured through 01289 * __HAL_RCC_PLL_CONFIG() macro) 01290 * 01291 * @param __PLLSAI2R__ specifies the division factor. 01292 * This parameter must be in the range (2, 4, 6 or 8). 01293 * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__ 01294 * 01295 * @retval None 01296 */ 01297 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \ 01298 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) 01299 01300 /** 01301 * @brief Macros to enable or disable the PLLSAI2. 01302 * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes. 01303 * @retval None 01304 */ 01305 01306 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON) 01307 01308 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) 01309 01310 /** 01311 * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). 01312 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 01313 * This is mainly used to save Power. 01314 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. 01315 * This parameter can be one or a combination of the following values: 01316 @if STM32L486xx 01317 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 01318 * high-quality audio performance on SAI interface in case. 01319 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 01320 @endif 01321 @if STM32L4A6xx 01322 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 01323 * high-quality audio performance on SAI interface in case. 01324 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 01325 @endif 01326 @if STM32L4S9xx 01327 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 01328 * high-quality audio performance on SAI interface in case. 01329 * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. 01330 @endif 01331 * @retval None 01332 */ 01333 01334 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 01335 01336 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 01337 01338 /** 01339 * @brief Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). 01340 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. 01341 * This parameter can be one of the following values: 01342 @if STM32L486xx 01343 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 01344 * high-quality audio performance on SAI interface in case. 01345 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 01346 @endif 01347 @if STM32L4A6xx 01348 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 01349 * high-quality audio performance on SAI interface in case. 01350 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 01351 @endif 01352 @if STM32L4S9xx 01353 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 01354 * high-quality audio performance on SAI interface in case. 01355 * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. 01356 @endif 01357 * @retval SET / RESET 01358 */ 01359 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 01360 01361 #endif /* RCC_PLLSAI2_SUPPORT */ 01362 01363 #if defined(SAI1) 01364 01365 /** 01366 * @brief Macro to configure the SAI1 clock source. 01367 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 01368 * from the PLLSAI1, system PLL or external clock (through a dedicated pin). 01369 * This parameter can be one of the following values: 01370 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 01371 @if STM32L486xx 01372 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 01373 @endif 01374 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) 01375 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 01376 @if STM32L4S9xx 01377 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 01378 @endif 01379 * 01380 @if STM32L443xx 01381 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. 01382 @endif 01383 * 01384 * @retval None 01385 */ 01386 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01387 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 01388 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__)) 01389 #else 01390 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 01391 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) 01392 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01393 01394 /** @brief Macro to get the SAI1 clock source. 01395 * @retval The clock source can be one of the following values: 01396 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 01397 @if STM32L486xx 01398 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 01399 @endif 01400 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) 01401 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 01402 * 01403 * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 01404 * clock source when PLLs are disabled for devices without PLLSAI2. 01405 * 01406 */ 01407 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01408 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL)) 01409 #else 01410 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) 01411 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01412 01413 #endif /* SAI1 */ 01414 01415 #if defined(SAI2) 01416 01417 /** 01418 * @brief Macro to configure the SAI2 clock source. 01419 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived 01420 * from the PLLSAI2, system PLL or external clock (through a dedicated pin). 01421 * This parameter can be one of the following values: 01422 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 01423 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 01424 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) 01425 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 01426 @if STM32L4S9xx 01427 * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 01428 @endif 01429 * 01430 * @retval None 01431 */ 01432 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01433 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 01434 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__)) 01435 #else 01436 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 01437 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__)) 01438 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01439 01440 /** @brief Macro to get the SAI2 clock source. 01441 * @retval The clock source can be one of the following values: 01442 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 01443 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 01444 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) 01445 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 01446 */ 01447 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01448 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL)) 01449 #else 01450 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)) 01451 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01452 01453 #endif /* SAI2 */ 01454 01455 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 01456 * 01457 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 01458 * This parameter can be one of the following values: 01459 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 01460 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 01461 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 01462 * @retval None 01463 */ 01464 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 01465 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) 01466 01467 /** @brief Macro to get the I2C1 clock source. 01468 * @retval The clock source can be one of the following values: 01469 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 01470 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 01471 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 01472 */ 01473 #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) 01474 01475 #if defined(I2C2) 01476 01477 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 01478 * 01479 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 01480 * This parameter can be one of the following values: 01481 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 01482 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 01483 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 01484 * @retval None 01485 */ 01486 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 01487 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) 01488 01489 /** @brief Macro to get the I2C2 clock source. 01490 * @retval The clock source can be one of the following values: 01491 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 01492 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 01493 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 01494 */ 01495 #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) 01496 01497 #endif /* I2C2 */ 01498 01499 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 01500 * 01501 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 01502 * This parameter can be one of the following values: 01503 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 01504 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 01505 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 01506 * @retval None 01507 */ 01508 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 01509 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) 01510 01511 /** @brief Macro to get the I2C3 clock source. 01512 * @retval The clock source can be one of the following values: 01513 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 01514 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 01515 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 01516 */ 01517 #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) 01518 01519 #if defined(I2C4) 01520 01521 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 01522 * 01523 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 01524 * This parameter can be one of the following values: 01525 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 01526 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 01527 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 01528 * @retval None 01529 */ 01530 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 01531 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) 01532 01533 /** @brief Macro to get the I2C4 clock source. 01534 * @retval The clock source can be one of the following values: 01535 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 01536 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 01537 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 01538 */ 01539 #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) 01540 01541 #endif /* I2C4 */ 01542 01543 01544 /** @brief Macro to configure the USART1 clock (USART1CLK). 01545 * 01546 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 01547 * This parameter can be one of the following values: 01548 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 01549 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 01550 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 01551 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock 01552 * @retval None 01553 */ 01554 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 01555 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) 01556 01557 /** @brief Macro to get the USART1 clock source. 01558 * @retval The clock source can be one of the following values: 01559 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 01560 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 01561 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 01562 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 01563 */ 01564 #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) 01565 01566 /** @brief Macro to configure the USART2 clock (USART2CLK). 01567 * 01568 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 01569 * This parameter can be one of the following values: 01570 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 01571 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 01572 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 01573 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 01574 * @retval None 01575 */ 01576 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 01577 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) 01578 01579 /** @brief Macro to get the USART2 clock source. 01580 * @retval The clock source can be one of the following values: 01581 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 01582 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 01583 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 01584 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 01585 */ 01586 #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) 01587 01588 #if defined(USART3) 01589 01590 /** @brief Macro to configure the USART3 clock (USART3CLK). 01591 * 01592 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 01593 * This parameter can be one of the following values: 01594 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 01595 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 01596 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 01597 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 01598 * @retval None 01599 */ 01600 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 01601 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) 01602 01603 /** @brief Macro to get the USART3 clock source. 01604 * @retval The clock source can be one of the following values: 01605 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 01606 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 01607 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 01608 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 01609 */ 01610 #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) 01611 01612 #endif /* USART3 */ 01613 01614 #if defined(UART4) 01615 01616 /** @brief Macro to configure the UART4 clock (UART4CLK). 01617 * 01618 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 01619 * This parameter can be one of the following values: 01620 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 01621 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 01622 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 01623 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 01624 * @retval None 01625 */ 01626 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 01627 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) 01628 01629 /** @brief Macro to get the UART4 clock source. 01630 * @retval The clock source can be one of the following values: 01631 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 01632 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 01633 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 01634 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 01635 */ 01636 #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) 01637 01638 #endif /* UART4 */ 01639 01640 #if defined(UART5) 01641 01642 /** @brief Macro to configure the UART5 clock (UART5CLK). 01643 * 01644 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 01645 * This parameter can be one of the following values: 01646 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 01647 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 01648 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 01649 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 01650 * @retval None 01651 */ 01652 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 01653 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) 01654 01655 /** @brief Macro to get the UART5 clock source. 01656 * @retval The clock source can be one of the following values: 01657 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 01658 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 01659 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 01660 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 01661 */ 01662 #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) 01663 01664 #endif /* UART5 */ 01665 01666 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 01667 * 01668 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 01669 * This parameter can be one of the following values: 01670 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 01671 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 01672 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 01673 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 01674 * @retval None 01675 */ 01676 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 01677 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) 01678 01679 /** @brief Macro to get the LPUART1 clock source. 01680 * @retval The clock source can be one of the following values: 01681 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 01682 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 01683 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 01684 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 01685 */ 01686 #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) 01687 01688 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 01689 * 01690 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 01691 * This parameter can be one of the following values: 01692 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 01693 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 01694 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock 01695 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 01696 * @retval None 01697 */ 01698 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 01699 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) 01700 01701 /** @brief Macro to get the LPTIM1 clock source. 01702 * @retval The clock source can be one of the following values: 01703 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 01704 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock 01705 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock 01706 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock 01707 */ 01708 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) 01709 01710 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 01711 * 01712 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 01713 * This parameter can be one of the following values: 01714 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 01715 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 01716 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock 01717 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 01718 * @retval None 01719 */ 01720 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 01721 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__)) 01722 01723 /** @brief Macro to get the LPTIM2 clock source. 01724 * @retval The clock source can be one of the following values: 01725 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 01726 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock 01727 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock 01728 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock 01729 */ 01730 #define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)) 01731 01732 #if defined(SDMMC1) 01733 01734 /** @brief Macro to configure the SDMMC1 clock. 01735 * 01736 @if STM32L486xx 01737 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 01738 @endif 01739 * 01740 @if STM32L443xx 01741 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 01742 @endif 01743 * 01744 * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. 01745 * This parameter can be one of the following values: 01746 @if STM32L486xx 01747 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 01748 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 01749 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock 01750 @endif 01751 @if STM32L443xx 01752 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 01753 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 01754 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock 01755 @endif 01756 @if STM32L4S9xx 01757 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 01758 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 01759 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock 01760 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock 01761 @endif 01762 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock 01763 * @retval None 01764 */ 01765 #if defined(RCC_CCIPR2_SDMMCSEL) 01766 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 01767 do \ 01768 { \ 01769 if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ 01770 { \ 01771 SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ 01772 } \ 01773 else \ 01774 { \ 01775 CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ 01776 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \ 01777 } \ 01778 } while(0) 01779 #else 01780 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 01781 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)) 01782 #endif /* RCC_CCIPR2_SDMMCSEL */ 01783 01784 /** @brief Macro to get the SDMMC1 clock. 01785 * @retval The clock source can be one of the following values: 01786 @if STM32L486xx 01787 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 01788 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 01789 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock 01790 @endif 01791 @if STM32L443xx 01792 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 01793 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 01794 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock 01795 @endif 01796 @if STM32L4S9xx 01797 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 01798 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 01799 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock 01800 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock 01801 @endif 01802 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock 01803 */ 01804 #if defined(RCC_CCIPR2_SDMMCSEL) 01805 #define __HAL_RCC_GET_SDMMC1_SOURCE() \ 01806 ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) 01807 #else 01808 #define __HAL_RCC_GET_SDMMC1_SOURCE() \ 01809 (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 01810 #endif /* RCC_CCIPR2_SDMMCSEL */ 01811 01812 #endif /* SDMMC1 */ 01813 01814 /** @brief Macro to configure the RNG clock. 01815 * 01816 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 01817 * 01818 * @param __RNG_CLKSOURCE__ specifies the RNG clock source. 01819 * This parameter can be one of the following values: 01820 @if STM32L486xx 01821 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 01822 @endif 01823 @if STM32L443xx 01824 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 01825 @endif 01826 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock 01827 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock 01828 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock 01829 * @retval None 01830 */ 01831 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 01832 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) 01833 01834 /** @brief Macro to get the RNG clock. 01835 * @retval The clock source can be one of the following values: 01836 @if STM32L486xx 01837 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 01838 @endif 01839 @if STM32L443xx 01840 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 01841 @endif 01842 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock 01843 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock 01844 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock 01845 */ 01846 #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 01847 01848 #if defined(USB_OTG_FS) || defined(USB) 01849 01850 /** @brief Macro to configure the USB clock (USBCLK). 01851 * 01852 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 01853 * 01854 * @param __USB_CLKSOURCE__ specifies the USB clock source. 01855 * This parameter can be one of the following values: 01856 @if STM32L486xx 01857 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 01858 @endif 01859 @if STM32L443xx 01860 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 01861 @endif 01862 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 01863 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 01864 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 01865 * @retval None 01866 */ 01867 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ 01868 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) 01869 01870 /** @brief Macro to get the USB clock source. 01871 * @retval The clock source can be one of the following values: 01872 @if STM32L486xx 01873 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 01874 @endif 01875 @if STM32L443xx 01876 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 01877 @endif 01878 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 01879 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 01880 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 01881 */ 01882 #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 01883 01884 #endif /* USB_OTG_FS || USB */ 01885 01886 #if defined(RCC_CCIPR_ADCSEL) 01887 01888 /** @brief Macro to configure the ADC interface clock. 01889 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. 01890 * This parameter can be one of the following values: 01891 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 01892 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 01893 @if STM32L486xx 01894 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices 01895 @endif 01896 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 01897 * @retval None 01898 */ 01899 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ 01900 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__)) 01901 01902 /** @brief Macro to get the ADC clock source. 01903 * @retval The clock source can be one of the following values: 01904 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 01905 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 01906 @if STM32L486xx 01907 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices 01908 @endif 01909 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 01910 */ 01911 #define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)) 01912 #else 01913 01914 /** @brief Macro to get the ADC clock source. 01915 * @retval The clock source can be one of the following values: 01916 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 01917 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 01918 */ 01919 #define __HAL_RCC_GET_ADC_SOURCE() ((__HAL_RCC_ADC_IS_CLK_ENABLED() != 0U) ? RCC_ADCCLKSOURCE_SYSCLK : RCC_ADCCLKSOURCE_NONE) 01920 01921 #endif /* RCC_CCIPR_ADCSEL */ 01922 01923 #if defined(SWPMI1) 01924 01925 /** @brief Macro to configure the SWPMI1 clock. 01926 * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source. 01927 * This parameter can be one of the following values: 01928 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock 01929 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock 01930 * @retval None 01931 */ 01932 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ 01933 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__)) 01934 01935 /** @brief Macro to get the SWPMI1 clock source. 01936 * @retval The clock source can be one of the following values: 01937 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock 01938 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock 01939 */ 01940 #define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)) 01941 01942 #endif /* SWPMI1 */ 01943 01944 #if defined(DFSDM1_Filter0) 01945 /** @brief Macro to configure the DFSDM1 clock. 01946 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. 01947 * This parameter can be one of the following values: 01948 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock 01949 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock 01950 * @retval None 01951 */ 01952 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01953 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ 01954 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 01955 #else 01956 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ 01957 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 01958 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01959 01960 /** @brief Macro to get the DFSDM1 clock source. 01961 * @retval The clock source can be one of the following values: 01962 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock 01963 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock 01964 */ 01965 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01966 #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL)) 01967 #else 01968 #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)) 01969 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01970 01971 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01972 01973 /** @brief Macro to configure the DFSDM1 audio clock. 01974 * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source. 01975 * This parameter can be one of the following values: 01976 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock 01977 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock 01978 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock 01979 * @retval None 01980 */ 01981 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ 01982 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__)) 01983 01984 /** @brief Macro to get the DFSDM1 audio clock source. 01985 * @retval The clock source can be one of the following values: 01986 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock 01987 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock 01988 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock 01989 */ 01990 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL)) 01991 01992 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01993 01994 #endif /* DFSDM1_Filter0 */ 01995 01996 #if defined(LTDC) 01997 01998 /** @brief Macro to configure the LTDC clock. 01999 * @param __LTDC_CLKSOURCE__ specifies the LTDC clock source. 02000 * This parameter can be one of the following values: 02001 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock 02002 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock 02003 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock 02004 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock 02005 * @retval None 02006 */ 02007 #define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ 02008 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__)) 02009 02010 /** @brief Macro to get the LTDC clock source. 02011 * @retval The clock source can be one of the following values: 02012 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock 02013 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock 02014 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock 02015 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock 02016 */ 02017 #define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)) 02018 02019 #endif /* LTDC */ 02020 02021 #if defined(DSI ) 02022 02023 /** @brief Macro to configure the DSI clock. 02024 * @param __DSI_CLKSOURCE__ specifies the DSI clock source. 02025 * This parameter can be one of the following values: 02026 * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock 02027 * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock 02028 * @retval None 02029 */ 02030 #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ 02031 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__)) 02032 02033 /** @brief Macro to get the DSI clock source. 02034 * @retval The clock source can be one of the following values: 02035 * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock 02036 * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock 02037 */ 02038 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL)) 02039 02040 #endif /* DSI */ 02041 02042 #if defined(OCTOSPI1) || defined(OCTOSPI2) 02043 02044 /** @brief Macro to configure the OctoSPI clock. 02045 * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. 02046 * This parameter can be one of the following values: 02047 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 02048 * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock 02049 * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock 02050 * @retval None 02051 */ 02052 #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ 02053 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__)) 02054 02055 /** @brief Macro to get the OctoSPI clock source. 02056 * @retval The clock source can be one of the following values: 02057 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 02058 * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock 02059 * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock 02060 */ 02061 #define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL)) 02062 02063 #endif /* OCTOSPI1 || OCTOSPI2 */ 02064 02065 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 02066 * @brief macros to manage the specified RCC Flags and interrupts. 02067 * @{ 02068 */ 02069 #if defined(RCC_PLLSAI1_SUPPORT) 02070 02071 /** @brief Enable PLLSAI1RDY interrupt. 02072 * @retval None 02073 */ 02074 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) 02075 02076 /** @brief Disable PLLSAI1RDY interrupt. 02077 * @retval None 02078 */ 02079 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) 02080 02081 /** @brief Clear the PLLSAI1RDY interrupt pending bit. 02082 * @retval None 02083 */ 02084 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC) 02085 02086 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not. 02087 * @retval TRUE or FALSE. 02088 */ 02089 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) 02090 02091 /** @brief Check whether the PLLSAI1RDY flag is set or not. 02092 * @retval TRUE or FALSE. 02093 */ 02094 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) 02095 02096 #endif /* RCC_PLLSAI1_SUPPORT */ 02097 02098 #if defined(RCC_PLLSAI2_SUPPORT) 02099 02100 /** @brief Enable PLLSAI2RDY interrupt. 02101 * @retval None 02102 */ 02103 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) 02104 02105 /** @brief Disable PLLSAI2RDY interrupt. 02106 * @retval None 02107 */ 02108 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) 02109 02110 /** @brief Clear the PLLSAI2RDY interrupt pending bit. 02111 * @retval None 02112 */ 02113 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC) 02114 02115 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not. 02116 * @retval TRUE or FALSE. 02117 */ 02118 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) 02119 02120 /** @brief Check whether the PLLSAI2RDY flag is set or not. 02121 * @retval TRUE or FALSE. 02122 */ 02123 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)) 02124 02125 #endif /* RCC_PLLSAI2_SUPPORT */ 02126 02127 02128 /** 02129 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 02130 * @retval None 02131 */ 02132 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 02133 02134 /** 02135 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 02136 * @retval None 02137 */ 02138 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 02139 02140 /** 02141 * @brief Enable the RCC LSE CSS Event Line. 02142 * @retval None. 02143 */ 02144 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 02145 02146 /** 02147 * @brief Disable the RCC LSE CSS Event Line. 02148 * @retval None. 02149 */ 02150 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 02151 02152 02153 /** 02154 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 02155 * @retval None. 02156 */ 02157 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 02158 02159 02160 /** 02161 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 02162 * @retval None. 02163 */ 02164 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 02165 02166 02167 /** 02168 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 02169 * @retval None. 02170 */ 02171 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 02172 02173 /** 02174 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 02175 * @retval None. 02176 */ 02177 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 02178 02179 /** 02180 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 02181 * @retval None. 02182 */ 02183 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 02184 do { \ 02185 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 02186 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 02187 } while(0) 02188 02189 /** 02190 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 02191 * @retval None. 02192 */ 02193 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 02194 do { \ 02195 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 02196 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 02197 } while(0) 02198 02199 /** 02200 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 02201 * @retval EXTI RCC LSE CSS Line Status. 02202 */ 02203 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 02204 02205 /** 02206 * @brief Clear the RCC LSE CSS EXTI flag. 02207 * @retval None. 02208 */ 02209 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) 02210 02211 /** 02212 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 02213 * @retval None. 02214 */ 02215 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) 02216 02217 02218 #if defined(CRS) 02219 02220 /** 02221 * @brief Enable the specified CRS interrupts. 02222 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 02223 * This parameter can be any combination of the following values: 02224 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 02225 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 02226 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 02227 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 02228 * @retval None 02229 */ 02230 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 02231 02232 /** 02233 * @brief Disable the specified CRS interrupts. 02234 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 02235 * This parameter can be any combination of the following values: 02236 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 02237 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 02238 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 02239 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 02240 * @retval None 02241 */ 02242 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 02243 02244 /** @brief Check whether the CRS interrupt has occurred or not. 02245 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 02246 * This parameter can be one of the following values: 02247 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 02248 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 02249 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 02250 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 02251 * @retval The new state of __INTERRUPT__ (SET or RESET). 02252 */ 02253 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 02254 02255 /** @brief Clear the CRS interrupt pending bits 02256 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 02257 * This parameter can be any combination of the following values: 02258 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 02259 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 02260 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 02261 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 02262 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 02263 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 02264 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 02265 */ 02266 /* CRS IT Error Mask */ 02267 #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) 02268 02269 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 02270 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 02271 { \ 02272 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 02273 } \ 02274 else \ 02275 { \ 02276 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 02277 } \ 02278 } while(0) 02279 02280 /** 02281 * @brief Check whether the specified CRS flag is set or not. 02282 * @param __FLAG__ specifies the flag to check. 02283 * This parameter can be one of the following values: 02284 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 02285 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 02286 * @arg @ref RCC_CRS_FLAG_ERR Error 02287 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 02288 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 02289 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 02290 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 02291 * @retval The new state of _FLAG_ (TRUE or FALSE). 02292 */ 02293 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 02294 02295 /** 02296 * @brief Clear the CRS specified FLAG. 02297 * @param __FLAG__ specifies the flag to clear. 02298 * This parameter can be one of the following values: 02299 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 02300 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 02301 * @arg @ref RCC_CRS_FLAG_ERR Error 02302 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 02303 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 02304 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 02305 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 02306 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 02307 * @retval None 02308 */ 02309 02310 /* CRS Flag Error Mask */ 02311 #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) 02312 02313 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 02314 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 02315 { \ 02316 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 02317 } \ 02318 else \ 02319 { \ 02320 WRITE_REG(CRS->ICR, (__FLAG__)); \ 02321 } \ 02322 } while(0) 02323 02324 #endif /* CRS */ 02325 02326 /** 02327 * @} 02328 */ 02329 02330 #if defined(CRS) 02331 02332 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 02333 * @{ 02334 */ 02335 /** 02336 * @brief Enable the oscillator clock for frequency error counter. 02337 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 02338 * @retval None 02339 */ 02340 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 02341 02342 /** 02343 * @brief Disable the oscillator clock for frequency error counter. 02344 * @retval None 02345 */ 02346 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 02347 02348 /** 02349 * @brief Enable the automatic hardware adjustement of TRIM bits. 02350 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 02351 * @retval None 02352 */ 02353 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 02354 02355 /** 02356 * @brief Enable or disable the automatic hardware adjustement of TRIM bits. 02357 * @retval None 02358 */ 02359 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 02360 02361 /** 02362 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 02363 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 02364 * of the synchronization source after prescaling. It is then decreased by one in order to 02365 * reach the expected synchronization on the zero value. The formula is the following: 02366 * RELOAD = (fTARGET / fSYNC) -1 02367 * @param __FTARGET__ Target frequency (value in Hz) 02368 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 02369 * @retval None 02370 */ 02371 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 02372 02373 /** 02374 * @} 02375 */ 02376 02377 #endif /* CRS */ 02378 02379 #if defined(PSSI) 02380 02381 /** @defgroup RCCEx_PSSI_Macros_Aliases RCCEx PSSI Macros Aliases 02382 * @{ 02383 */ 02384 02385 #define __HAL_RCC_PSSI_CLK_ENABLE() __HAL_RCC_DCMI_CLK_ENABLE() 02386 02387 #define __HAL_RCC_PSSI_CLK_DISABLE() __HAL_RCC_DCMI_CLK_DISABLE() 02388 02389 #define __HAL_RCC_PSSI_IS_CLK_ENABLED() __HAL_RCC_DCMI_IS_CLK_ENABLED() 02390 02391 #define __HAL_RCC_PSSI_IS_CLK_DISABLED() __HAL_RCC_DCMI_IS_CLK_DISABLED() 02392 02393 #define __HAL_RCC_PSSI_FORCE_RESET() __HAL_RCC_DCMI_FORCE_RESET() 02394 02395 #define __HAL_RCC_PSSI_RELEASE_RESET() __HAL_RCC_DCMI_RELEASE_RESET() 02396 02397 #define __HAL_RCC_PSSI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() 02398 02399 #define __HAL_RCC_PSSI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() 02400 02401 #define __HAL_RCC_PSSI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() 02402 02403 #define __HAL_RCC_PSSI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() 02404 02405 /** 02406 * @} 02407 */ 02408 02409 #endif /* PSSI */ 02410 02411 /** 02412 * @} 02413 */ 02414 02415 /* Exported functions --------------------------------------------------------*/ 02416 /** @addtogroup RCCEx_Exported_Functions 02417 * @{ 02418 */ 02419 02420 /** @addtogroup RCCEx_Exported_Functions_Group1 02421 * @{ 02422 */ 02423 02424 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 02425 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 02426 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 02427 02428 /** 02429 * @} 02430 */ 02431 02432 /** @addtogroup RCCEx_Exported_Functions_Group2 02433 * @{ 02434 */ 02435 #if defined(RCC_PLLSAI1_SUPPORT) 02436 02437 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); 02438 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); 02439 02440 #endif /* RCC_PLLSAI1_SUPPORT */ 02441 02442 #if defined(RCC_PLLSAI2_SUPPORT) 02443 02444 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); 02445 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void); 02446 02447 #endif /* RCC_PLLSAI2_SUPPORT */ 02448 02449 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 02450 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); 02451 void HAL_RCCEx_EnableLSECSS(void); 02452 void HAL_RCCEx_DisableLSECSS(void); 02453 void HAL_RCCEx_EnableLSECSS_IT(void); 02454 void HAL_RCCEx_LSECSS_IRQHandler(void); 02455 void HAL_RCCEx_LSECSS_Callback(void); 02456 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 02457 void HAL_RCCEx_DisableLSCO(void); 02458 void HAL_RCCEx_EnableMSIPLLMode(void); 02459 void HAL_RCCEx_DisableMSIPLLMode(void); 02460 #if defined (OCTOSPI1) && defined (OCTOSPI2) 02461 void HAL_RCCEx_OCTOSPIDelayConfig(uint32_t Delay1, uint32_t Delay2); 02462 #endif /* OCTOSPI1 && OCTOSPI2 */ 02463 02464 /** 02465 * @} 02466 */ 02467 02468 #if defined(CRS) 02469 02470 /** @addtogroup RCCEx_Exported_Functions_Group3 02471 * @{ 02472 */ 02473 02474 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 02475 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 02476 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 02477 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 02478 void HAL_RCCEx_CRS_IRQHandler(void); 02479 void HAL_RCCEx_CRS_SyncOkCallback(void); 02480 void HAL_RCCEx_CRS_SyncWarnCallback(void); 02481 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 02482 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 02483 02484 /** 02485 * @} 02486 */ 02487 02488 #endif /* CRS */ 02489 02490 /** 02491 * @} 02492 */ 02493 02494 /* Private constants ---------------------------------------------------------*/ 02495 /** @addtogroup RCCEx_Private_Constants 02496 * @{ 02497 */ 02498 /* Define used for IS_RCC_* macros below */ 02499 #if defined(STM32L412xx) || defined(STM32L422xx) 02500 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 02501 RCC_PERIPHCLK_LPUART1 | \ 02502 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 02503 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02504 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ 02505 RCC_PERIPHCLK_RNG) 02506 #elif defined(STM32L431xx) 02507 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 02508 RCC_PERIPHCLK_LPUART1 | \ 02509 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 02510 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02511 RCC_PERIPHCLK_SAI1 | \ 02512 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ 02513 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 02514 #elif defined(STM32L432xx) || defined(STM32L442xx) 02515 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ 02516 RCC_PERIPHCLK_LPUART1 | \ 02517 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \ 02518 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02519 RCC_PERIPHCLK_SAI1 | \ 02520 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | \ 02521 RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG) 02522 #elif defined(STM32L433xx) || defined(STM32L443xx) 02523 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ 02524 RCC_PERIPHCLK_LPUART1 | \ 02525 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 02526 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02527 RCC_PERIPHCLK_SAI1 | \ 02528 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ 02529 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 02530 #elif defined(STM32L451xx) 02531 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ 02532 RCC_PERIPHCLK_UART4 | \ 02533 RCC_PERIPHCLK_LPUART1 | \ 02534 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 02535 RCC_PERIPHCLK_I2C4 | \ 02536 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02537 RCC_PERIPHCLK_SAI1 | \ 02538 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 02539 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 02540 #elif defined(STM32L452xx) || defined(STM32L462xx) 02541 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ 02542 RCC_PERIPHCLK_UART4 | \ 02543 RCC_PERIPHCLK_LPUART1 | \ 02544 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 02545 RCC_PERIPHCLK_I2C4 | \ 02546 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02547 RCC_PERIPHCLK_SAI1 | \ 02548 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 02549 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 02550 #elif defined(STM32L471xx) 02551 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 02552 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 02553 RCC_PERIPHCLK_LPUART1 | \ 02554 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 02555 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02556 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 02557 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ 02558 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 02559 #elif defined(STM32L496xx) || defined(STM32L4A6xx) 02560 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 02561 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 02562 RCC_PERIPHCLK_LPUART1 | \ 02563 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 02564 RCC_PERIPHCLK_I2C4 | \ 02565 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02566 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 02567 RCC_PERIPHCLK_USB | \ 02568 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ 02569 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 02570 #elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) 02571 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 02572 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 02573 RCC_PERIPHCLK_LPUART1 | \ 02574 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 02575 RCC_PERIPHCLK_I2C4 | \ 02576 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02577 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 02578 RCC_PERIPHCLK_USB | \ 02579 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \ 02580 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \ 02581 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC) 02582 #elif defined(STM32L4R5xx) || defined(STM32L4S5xx) 02583 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 02584 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 02585 RCC_PERIPHCLK_LPUART1 | \ 02586 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 02587 RCC_PERIPHCLK_I2C4 | \ 02588 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02589 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 02590 RCC_PERIPHCLK_USB | \ 02591 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \ 02592 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \ 02593 RCC_PERIPHCLK_OSPI) 02594 #elif defined(STM32L4R7xx) || defined(STM32L4S7xx) 02595 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 02596 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 02597 RCC_PERIPHCLK_LPUART1 | \ 02598 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 02599 RCC_PERIPHCLK_I2C4 | \ 02600 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02601 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 02602 RCC_PERIPHCLK_USB | \ 02603 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \ 02604 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \ 02605 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC) 02606 #elif defined(STM32L4R9xx) || defined(STM32L4S9xx) 02607 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 02608 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 02609 RCC_PERIPHCLK_LPUART1 | \ 02610 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 02611 RCC_PERIPHCLK_I2C4 | \ 02612 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02613 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 02614 RCC_PERIPHCLK_USB | \ 02615 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \ 02616 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \ 02617 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI) 02618 #else 02619 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 02620 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 02621 RCC_PERIPHCLK_LPUART1 | \ 02622 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 02623 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 02624 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 02625 RCC_PERIPHCLK_USB | \ 02626 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ 02627 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 02628 #endif /* STM32L412xx || STM32L422xx */ 02629 02630 /** 02631 * @} 02632 */ 02633 02634 /* Private macros ------------------------------------------------------------*/ 02635 /** @addtogroup RCCEx_Private_Macros 02636 * @{ 02637 */ 02638 02639 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 02640 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 02641 02642 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \ 02643 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u)) 02644 02645 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 02646 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 02647 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 02648 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 02649 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 02650 02651 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 02652 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 02653 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 02654 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 02655 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 02656 02657 #if defined(USART3) 02658 02659 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 02660 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 02661 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ 02662 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ 02663 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) 02664 02665 #endif /* USART3 */ 02666 02667 #if defined(UART4) 02668 02669 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 02670 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 02671 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ 02672 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ 02673 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) 02674 02675 #endif /* UART4 */ 02676 02677 #if defined(UART5) 02678 02679 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 02680 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 02681 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ 02682 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ 02683 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) 02684 02685 #endif /* UART5 */ 02686 02687 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 02688 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 02689 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 02690 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 02691 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 02692 02693 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 02694 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 02695 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 02696 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 02697 02698 #if defined(I2C2) 02699 02700 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 02701 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 02702 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ 02703 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) 02704 02705 #endif /* I2C2 */ 02706 02707 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 02708 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 02709 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 02710 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 02711 02712 #if defined(I2C4) 02713 02714 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 02715 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ 02716 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ 02717 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) 02718 02719 #endif /* I2C4 */ 02720 02721 #if defined(RCC_PLLSAI2_SUPPORT) 02722 02723 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 02724 #define IS_RCC_SAI1CLK(__SOURCE__) \ 02725 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 02726 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ 02727 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 02728 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ 02729 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) 02730 #else 02731 #define IS_RCC_SAI1CLK(__SOURCE__) \ 02732 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 02733 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ 02734 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 02735 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 02736 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 02737 02738 #elif defined(RCC_PLLSAI1_SUPPORT) 02739 02740 #define IS_RCC_SAI1CLK(__SOURCE__) \ 02741 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 02742 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 02743 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 02744 02745 #endif /* RCC_PLLSAI2_SUPPORT */ 02746 02747 #if defined(RCC_PLLSAI2_SUPPORT) 02748 02749 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 02750 #define IS_RCC_SAI2CLK(__SOURCE__) \ 02751 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ 02752 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ 02753 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 02754 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ 02755 ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) 02756 #else 02757 #define IS_RCC_SAI2CLK(__SOURCE__) \ 02758 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ 02759 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ 02760 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 02761 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) 02762 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 02763 02764 #endif /* RCC_PLLSAI2_SUPPORT */ 02765 02766 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 02767 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 02768 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 02769 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 02770 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 02771 02772 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 02773 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 02774 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 02775 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ 02776 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) 02777 02778 #if defined(SDMMC1) 02779 #if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL) 02780 02781 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 02782 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \ 02783 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ 02784 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 02785 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 02786 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) 02787 02788 #elif defined(RCC_HSI48_SUPPORT) 02789 02790 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 02791 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ 02792 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 02793 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 02794 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) 02795 #else 02796 02797 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 02798 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \ 02799 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 02800 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 02801 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) 02802 02803 #endif /* RCC_HSI48_SUPPORT */ 02804 #endif /* SDMMC1 */ 02805 02806 #if defined(RCC_HSI48_SUPPORT) 02807 02808 #if defined(RCC_PLLSAI1_SUPPORT) 02809 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 02810 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 02811 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ 02812 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 02813 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 02814 #else 02815 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 02816 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 02817 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 02818 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 02819 #endif /* RCC_PLLSAI1_SUPPORT */ 02820 02821 #else 02822 02823 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 02824 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ 02825 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ 02826 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 02827 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 02828 02829 #endif /* RCC_HSI48_SUPPORT */ 02830 02831 #if defined(USB_OTG_FS) || defined(USB) 02832 #if defined(RCC_HSI48_SUPPORT) 02833 02834 #if defined(RCC_PLLSAI1_SUPPORT) 02835 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 02836 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 02837 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ 02838 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 02839 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 02840 #else 02841 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 02842 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 02843 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 02844 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 02845 #endif /* RCC_PLLSAI1_SUPPORT */ 02846 02847 #else 02848 02849 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 02850 (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \ 02851 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ 02852 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 02853 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 02854 02855 #endif /* RCC_HSI48_SUPPORT */ 02856 #endif /* USB_OTG_FS || USB */ 02857 02858 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 02859 02860 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 02861 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 02862 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ 02863 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \ 02864 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 02865 02866 #else 02867 02868 #if defined(RCC_PLLSAI1_SUPPORT) 02869 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 02870 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 02871 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ 02872 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 02873 #else 02874 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 02875 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 02876 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 02877 #endif /* RCC_PLLSAI1_SUPPORT */ 02878 02879 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 02880 02881 #if defined(SWPMI1) 02882 02883 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \ 02884 (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \ 02885 ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI)) 02886 02887 #endif /* SWPMI1 */ 02888 02889 #if defined(DFSDM1_Filter0) 02890 02891 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \ 02892 (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ 02893 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 02894 02895 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 02896 02897 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \ 02898 (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ 02899 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ 02900 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) 02901 02902 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 02903 02904 #endif /* DFSDM1_Filter0 */ 02905 02906 #if defined(LTDC) 02907 02908 #define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ 02909 (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \ 02910 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \ 02911 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \ 02912 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16)) 02913 02914 #endif /* LTDC */ 02915 02916 #if defined(DSI) 02917 02918 #define IS_RCC_DSICLKSOURCE(__SOURCE__) \ 02919 (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \ 02920 ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2)) 02921 02922 #endif /* DSI */ 02923 02924 #if defined(OCTOSPI1) || defined(OCTOSPI2) 02925 02926 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ 02927 (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ 02928 ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ 02929 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) 02930 02931 #endif /* OCTOSPI1 || OCTOSPI2 */ 02932 02933 #if defined(RCC_PLLSAI1_SUPPORT) 02934 02935 #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) 02936 02937 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 02938 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 02939 #else 02940 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 02941 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 02942 02943 #if defined(RCC_PLLSAI1N_MUL_8_127_SUPPORT) 02944 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U)) 02945 #else 02946 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 02947 #endif /* RCC_PLLSAI1N_MUL_8_127_SUPPORT */ 02948 02949 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 02950 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 02951 #else 02952 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 02953 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 02954 02955 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 02956 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 02957 02958 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 02959 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 02960 02961 #endif /* RCC_PLLSAI1_SUPPORT */ 02962 02963 #if defined(RCC_PLLSAI2_SUPPORT) 02964 02965 #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) 02966 02967 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 02968 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 02969 #else 02970 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 02971 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 02972 02973 #if defined(RCC_PLLSAI2N_MUL_8_127_SUPPORT) 02974 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U)) 02975 #else 02976 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 02977 #endif /* RCC_PLLSAI2N_MUL_8_127_SUPPORT */ 02978 02979 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 02980 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 02981 #else 02982 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 02983 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 02984 02985 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 02986 #define IS_RCC_PLLSAI2Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 02987 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 02988 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 02989 02990 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 02991 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 02992 02993 #endif /* RCC_PLLSAI2_SUPPORT */ 02994 02995 #if defined (OCTOSPI1) && defined (OCTOSPI2) 02996 #define IS_RCC_OCTOSPIDELAY(__DELAY__) (((__DELAY__) <= 0xFU)) 02997 #endif /* OCTOSPI1 && OCTOSPI2 */ 02998 02999 #if defined(CRS) 03000 03001 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 03002 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 03003 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 03004 03005 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 03006 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 03007 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 03008 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 03009 03010 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 03011 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 03012 03013 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 03014 03015 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 03016 03017 #if defined(STM32L412xx) || defined(STM32L422xx) 03018 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) 03019 #else 03020 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 03021 #endif /* STM32L412xx || STM32L422xx */ 03022 03023 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 03024 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 03025 03026 #endif /* CRS */ 03027 03028 /** 03029 * @} 03030 */ 03031 03032 /** 03033 * @} 03034 */ 03035 03036 /** 03037 * @} 03038 */ 03039 03040 #ifdef __cplusplus 03041 } 03042 #endif 03043 03044 #endif /* STM32L4xx_HAL_RCC_EX_H */ 03045
1.7.6.1