RCC_PLLSAI1InitTypeDef Struct Reference

PLLSAI1 Clock structure definition. More...

#include <stm32l4xx_hal_rcc_ex.h>

Data Fields
uint32_t	PLLSAI1Source
uint32_t	PLLSAI1M
uint32_t	PLLSAI1N
uint32_t	PLLSAI1P
uint32_t	PLLSAI1Q
uint32_t	PLLSAI1R
uint32_t	PLLSAI1ClockOut

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Detailed Description

PLLSAI1 Clock structure definition.

Definition at line 47 of file stm32l4xx_hal_rcc_ex.h.

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Field Documentation

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1ClockOut

PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. This parameter must be a value of PLLSAI1 Clock Output

Definition at line 73 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1M

PLLSAI1M: specifies the division factor for PLLSAI1 input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 8

Definition at line 57 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1N

PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. This parameter must be a number between 8 and 86 or 127 depending on devices.

Definition at line 61 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1P

PLLSAI1P: specifies the division factor for SAI clock. This parameter must be a value of PLLP Clock Divider

Definition at line 64 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1Q

PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. This parameter must be a value of PLLQ Clock Divider

Definition at line 67 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1R

PLLSAI1R: specifies the division factor for ADC clock. This parameter must be a value of PLLR Clock Divider

Definition at line 70 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1Source

PLLSAI1Source: PLLSAI1 entry clock source. This parameter must be a value of PLL Clock Source

Definition at line 50 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

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The documentation for this struct was generated from the following file:

• stm32l4xx_hal_rcc_ex.h