stm32l4xx_ll_bus.h File Reference

Header file of BUS LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Defines
#define	LL_AHB1_GRP1_PERIPH_ALL   0xFFFFFFFFU
#define	LL_AHB1_GRP1_PERIPH_DMA1   RCC_AHB1ENR_DMA1EN
#define	LL_AHB1_GRP1_PERIPH_DMA2   RCC_AHB1ENR_DMA2EN
#define	LL_AHB1_GRP1_PERIPH_FLASH   RCC_AHB1ENR_FLASHEN
#define	LL_AHB1_GRP1_PERIPH_CRC   RCC_AHB1ENR_CRCEN
#define	LL_AHB1_GRP1_PERIPH_TSC   RCC_AHB1ENR_TSCEN
#define	LL_AHB1_GRP1_PERIPH_SRAM1   RCC_AHB1SMENR_SRAM1SMEN
#define	LL_AHB2_GRP1_PERIPH_ALL   0xFFFFFFFFU
#define	LL_AHB2_GRP1_PERIPH_GPIOA   RCC_AHB2ENR_GPIOAEN
#define	LL_AHB2_GRP1_PERIPH_GPIOB   RCC_AHB2ENR_GPIOBEN
#define	LL_AHB2_GRP1_PERIPH_GPIOC   RCC_AHB2ENR_GPIOCEN
#define	LL_AHB2_GRP1_PERIPH_GPIOD   RCC_AHB2ENR_GPIODEN
#define	LL_AHB2_GRP1_PERIPH_GPIOE   RCC_AHB2ENR_GPIOEEN
#define	LL_AHB2_GRP1_PERIPH_GPIOH   RCC_AHB2ENR_GPIOHEN
#define	LL_AHB2_GRP1_PERIPH_ADC   RCC_AHB2ENR_ADCEN
#define	LL_AHB2_GRP1_PERIPH_AES   RCC_AHB2ENR_AESEN
#define	LL_AHB2_GRP1_PERIPH_RNG   RCC_AHB2ENR_RNGEN
#define	LL_AHB2_GRP1_PERIPH_SRAM2   RCC_AHB2SMENR_SRAM2SMEN
#define	LL_AHB3_GRP1_PERIPH_ALL   0xFFFFFFFFU
#define	LL_AHB3_GRP1_PERIPH_QSPI   RCC_AHB3ENR_QSPIEN
#define	LL_APB1_GRP1_PERIPH_ALL   0xFFFFFFFFU
#define	LL_APB1_GRP1_PERIPH_TIM2   RCC_APB1ENR1_TIM2EN
#define	LL_APB1_GRP1_PERIPH_TIM6   RCC_APB1ENR1_TIM6EN
#define	LL_APB1_GRP1_PERIPH_TIM7   RCC_APB1ENR1_TIM7EN
#define	LL_APB1_GRP1_PERIPH_LCD   RCC_APB1ENR1_LCDEN
#define	LL_APB1_GRP1_PERIPH_RTCAPB   RCC_APB1ENR1_RTCAPBEN
#define	LL_APB1_GRP1_PERIPH_WWDG   RCC_APB1ENR1_WWDGEN
#define	LL_APB1_GRP1_PERIPH_SPI2   RCC_APB1ENR1_SPI2EN
#define	LL_APB1_GRP1_PERIPH_SPI3   RCC_APB1ENR1_SPI3EN
#define	LL_APB1_GRP1_PERIPH_USART2   RCC_APB1ENR1_USART2EN
#define	LL_APB1_GRP1_PERIPH_USART3   RCC_APB1ENR1_USART3EN
#define	LL_APB1_GRP1_PERIPH_I2C1   RCC_APB1ENR1_I2C1EN
#define	LL_APB1_GRP1_PERIPH_I2C2   RCC_APB1ENR1_I2C2EN
#define	LL_APB1_GRP1_PERIPH_I2C3   RCC_APB1ENR1_I2C3EN
#define	LL_APB1_GRP1_PERIPH_CRS   RCC_APB1ENR1_CRSEN
#define	LL_APB1_GRP1_PERIPH_CAN1   RCC_APB1ENR1_CAN1EN
#define	LL_APB1_GRP1_PERIPH_USB   RCC_APB1ENR1_USBFSEN
#define	LL_APB1_GRP1_PERIPH_PWR   RCC_APB1ENR1_PWREN
#define	LL_APB1_GRP1_PERIPH_DAC1   RCC_APB1ENR1_DAC1EN
#define	LL_APB1_GRP1_PERIPH_OPAMP   RCC_APB1ENR1_OPAMPEN
#define	LL_APB1_GRP1_PERIPH_LPTIM1   RCC_APB1ENR1_LPTIM1EN
#define	LL_APB1_GRP2_PERIPH_ALL   0xFFFFFFFFU
#define	LL_APB1_GRP2_PERIPH_LPUART1   RCC_APB1ENR2_LPUART1EN
#define	LL_APB1_GRP2_PERIPH_SWPMI1   RCC_APB1ENR2_SWPMI1EN
#define	LL_APB1_GRP2_PERIPH_LPTIM2   RCC_APB1ENR2_LPTIM2EN
#define	LL_APB2_GRP1_PERIPH_ALL   0xFFFFFFFFU
#define	LL_APB2_GRP1_PERIPH_SYSCFG   RCC_APB2ENR_SYSCFGEN
#define	LL_APB2_GRP1_PERIPH_FW   RCC_APB2ENR_FWEN
#define	LL_APB2_GRP1_PERIPH_SDMMC1   RCC_APB2ENR_SDMMC1EN
#define	LL_APB2_GRP1_PERIPH_TIM1   RCC_APB2ENR_TIM1EN
#define	LL_APB2_GRP1_PERIPH_SPI1   RCC_APB2ENR_SPI1EN
#define	LL_APB2_GRP1_PERIPH_USART1   RCC_APB2ENR_USART1EN
#define	LL_APB2_GRP1_PERIPH_TIM15   RCC_APB2ENR_TIM15EN
#define	LL_APB2_GRP1_PERIPH_TIM16   RCC_APB2ENR_TIM16EN
#define	LL_APB2_GRP1_PERIPH_SAI1   RCC_APB2ENR_SAI1EN
Functions
__STATIC_INLINE void	LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t	LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB1 peripherals clock.
__STATIC_INLINE void	LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
	Force AHB1 peripherals reset.
__STATIC_INLINE void	LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB1 peripherals reset.
__STATIC_INLINE void	LL_AHB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
	Enable AHB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void	LL_AHB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
	Disable AHB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void	LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB2 peripherals clock.
__STATIC_INLINE uint32_t	LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB2 peripherals clock.
__STATIC_INLINE void	LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
	Force AHB2 peripherals reset.
__STATIC_INLINE void	LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB2 peripherals reset.
__STATIC_INLINE void	LL_AHB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
	Enable AHB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void	LL_AHB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
	Disable AHB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void	LL_AHB3_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB3 peripherals clock.
__STATIC_INLINE uint32_t	LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_AHB3_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB3 peripherals clock.
__STATIC_INLINE void	LL_AHB3_GRP1_ForceReset (uint32_t Periphs)
	Force AHB3 peripherals reset.
__STATIC_INLINE void	LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB3 peripherals reset.
__STATIC_INLINE void	LL_AHB3_GRP1_EnableClockStopSleep (uint32_t Periphs)
	Enable AHB3 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void	LL_AHB3_GRP1_DisableClockStopSleep (uint32_t Periphs)
	Disable AHB3 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void	LL_APB1_GRP1_EnableClock (uint32_t Periphs)
	Enable APB1 peripherals clock.
__STATIC_INLINE void	LL_APB1_GRP2_EnableClock (uint32_t Periphs)
	Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t	LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE uint32_t	LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
	Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_APB1_GRP1_DisableClock (uint32_t Periphs)
	Disable APB1 peripherals clock.
__STATIC_INLINE void	LL_APB1_GRP2_DisableClock (uint32_t Periphs)
	Disable APB1 peripherals clock.
__STATIC_INLINE void	LL_APB1_GRP1_ForceReset (uint32_t Periphs)
	Force APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP2_ForceReset (uint32_t Periphs)
	Force APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
	Release APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP2_ReleaseReset (uint32_t Periphs)
	Release APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
	Enable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void	LL_APB1_GRP2_EnableClockStopSleep (uint32_t Periphs)
	Enable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void	LL_APB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
	Disable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void	LL_APB1_GRP2_DisableClockStopSleep (uint32_t Periphs)
	Disable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void	LL_APB2_GRP1_EnableClock (uint32_t Periphs)
	Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t	LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_APB2_GRP1_DisableClock (uint32_t Periphs)
	Disable APB2 peripherals clock.
__STATIC_INLINE void	LL_APB2_GRP1_ForceReset (uint32_t Periphs)
	Force APB2 peripherals reset.
__STATIC_INLINE void	LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
	Release APB2 peripherals reset.
__STATIC_INLINE void	LL_APB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
	Enable APB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void	LL_APB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
	Disable APB2 peripheral clocks in Sleep and Stop modes.

---

Detailed Description

Header file of BUS LL module.

Author:

MCD Application Team

                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.

  

Attention:

Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32l4xx_ll_bus.h.