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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_bus.h 00004 * @author MCD Application Team 00005 * @brief Header file of BUS LL module. 00006 00007 @verbatim 00008 ##### RCC Limitations ##### 00009 ============================================================================== 00010 [..] 00011 A delay between an RCC peripheral clock enable and the effective peripheral 00012 enabling should be taken into account in order to manage the peripheral read/write 00013 from/to registers. 00014 (+) This delay depends on the peripheral mapping. 00015 (++) AHB & APB peripherals, 1 dummy read is necessary 00016 00017 [..] 00018 Workarounds: 00019 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 00020 inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 00021 00022 @endverbatim 00023 ****************************************************************************** 00024 * @attention 00025 * 00026 * Copyright (c) 2017 STMicroelectronics. 00027 * All rights reserved. 00028 * 00029 * This software is licensed under terms that can be found in the LICENSE file in 00030 * the root directory of this software component. 00031 * If no LICENSE file comes with this software, it is provided AS-IS. 00032 ****************************************************************************** 00033 */ 00034 00035 /* Define to prevent recursive inclusion -------------------------------------*/ 00036 #ifndef STM32L4xx_LL_BUS_H 00037 #define STM32L4xx_LL_BUS_H 00038 00039 #ifdef __cplusplus 00040 extern "C" { 00041 #endif 00042 00043 /* Includes ------------------------------------------------------------------*/ 00044 #include "stm32l4xx.h" 00045 00046 /** @addtogroup STM32L4xx_LL_Driver 00047 * @{ 00048 */ 00049 00050 #if defined(RCC) 00051 00052 /** @defgroup BUS_LL BUS 00053 * @{ 00054 */ 00055 00056 /* Private types -------------------------------------------------------------*/ 00057 /* Private variables ---------------------------------------------------------*/ 00058 00059 /* Private constants ---------------------------------------------------------*/ 00060 00061 /* Private macros ------------------------------------------------------------*/ 00062 00063 /* Exported types ------------------------------------------------------------*/ 00064 /* Exported constants --------------------------------------------------------*/ 00065 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 00066 * @{ 00067 */ 00068 00069 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 00070 * @{ 00071 */ 00072 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 00073 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN 00074 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 00075 #if defined(DMAMUX1) 00076 #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN 00077 #endif /* DMAMUX1 */ 00078 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN 00079 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 00080 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN 00081 #if defined(DMA2D) 00082 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN 00083 #endif /* DMA2D */ 00084 #if defined(GFXMMU) 00085 #define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN 00086 #endif /* GFXMMU */ 00087 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN 00088 /** 00089 * @} 00090 */ 00091 00092 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 00093 * @{ 00094 */ 00095 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 00096 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN 00097 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN 00098 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN 00099 #if defined(GPIOD) 00100 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN 00101 #endif /*GPIOD*/ 00102 #if defined(GPIOE) 00103 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN 00104 #endif /*GPIOE*/ 00105 #if defined(GPIOF) 00106 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN 00107 #endif /* GPIOF */ 00108 #if defined(GPIOG) 00109 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN 00110 #endif /* GPIOG */ 00111 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN 00112 #if defined(GPIOI) 00113 #define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN 00114 #endif /* GPIOI */ 00115 #if defined(USB_OTG_FS) 00116 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN 00117 #endif /* USB_OTG_FS */ 00118 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN 00119 #if defined(DCMI) 00120 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN 00121 #endif /* DCMI */ 00122 #if defined(AES) 00123 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN 00124 #endif /* AES */ 00125 #if defined(HASH) 00126 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN 00127 #endif /* HASH */ 00128 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 00129 #if defined(OCTOSPIM) 00130 #define LL_AHB2_GRP1_PERIPH_OSPIM RCC_AHB2ENR_OSPIMEN 00131 #endif /* OCTOSPIM */ 00132 #if defined(PKA) 00133 #define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN 00134 #endif /* PKA */ 00135 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 00136 #define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR_SDMMC1EN 00137 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 00138 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN 00139 #if defined(SRAM3_BASE) 00140 #define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2SMENR_SRAM3SMEN 00141 #endif /* SRAM3_BASE */ 00142 /** 00143 * @} 00144 */ 00145 00146 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 00147 * @{ 00148 */ 00149 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU 00150 #if defined(FMC_Bank1_R) 00151 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 00152 #endif /* FMC_Bank1_R */ 00153 #if defined(QUADSPI) 00154 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 00155 #endif /* QUADSPI */ 00156 #if defined(OCTOSPI1) 00157 #define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN 00158 #endif /* OCTOSPI1 */ 00159 #if defined(OCTOSPI2) 00160 #define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN 00161 #endif /* OCTOSPI2 */ 00162 /** 00163 * @} 00164 */ 00165 00166 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 00167 * @{ 00168 */ 00169 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 00170 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN 00171 #if defined(TIM3) 00172 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN 00173 #endif /* TIM3 */ 00174 #if defined(TIM4) 00175 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN 00176 #endif /* TIM4 */ 00177 #if defined(TIM5) 00178 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN 00179 #endif /* TIM5 */ 00180 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN 00181 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN 00182 #if defined(LCD) 00183 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN 00184 #endif /* LCD */ 00185 #if defined(RCC_APB1ENR1_RTCAPBEN) 00186 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN 00187 #endif /* RCC_APB1ENR1_RTCAPBEN */ 00188 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN 00189 #if defined(SPI2) 00190 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN 00191 #endif /* SPI2 */ 00192 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN 00193 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN 00194 #if defined(USART3) 00195 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN 00196 #endif /* USART3 */ 00197 #if defined(UART4) 00198 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN 00199 #endif /* UART4 */ 00200 #if defined(UART5) 00201 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN 00202 #endif /* UART5 */ 00203 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN 00204 #if defined(I2C2) 00205 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN 00206 #endif /* I2C2 */ 00207 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN 00208 #if defined(CRS) 00209 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN 00210 #endif /* CRS */ 00211 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN 00212 #if defined(CAN2) 00213 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR1_CAN2EN 00214 #endif /* CAN2 */ 00215 #if defined(USB) 00216 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN 00217 #endif /* USB */ 00218 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN 00219 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN 00220 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN 00221 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN 00222 /** 00223 * @} 00224 */ 00225 00226 00227 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH 00228 * @{ 00229 */ 00230 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU 00231 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN 00232 #if defined(I2C4) 00233 #define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN 00234 #endif /* I2C4 */ 00235 #if defined(SWPMI1) 00236 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN 00237 #endif /* SWPMI1 */ 00238 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN 00239 /** 00240 * @} 00241 */ 00242 00243 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 00244 * @{ 00245 */ 00246 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 00247 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN 00248 #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN 00249 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 00250 #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN 00251 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 00252 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 00253 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 00254 #if defined(TIM8) 00255 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 00256 #endif /* TIM8 */ 00257 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 00258 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN 00259 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN 00260 #if defined(TIM17) 00261 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN 00262 #endif /* TIM17 */ 00263 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN 00264 #if defined(SAI2) 00265 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN 00266 #endif /* SAI2 */ 00267 #if defined(DFSDM1_Channel0) 00268 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN 00269 #endif /* DFSDM1_Channel0 */ 00270 #if defined(LTDC) 00271 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN 00272 #endif /* LTDC */ 00273 #if defined(DSI) 00274 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN 00275 #endif /* DSI */ 00276 /** 00277 * @} 00278 */ 00279 00280 /** Legacy definitions for compatibility purpose 00281 @cond 0 00282 */ 00283 #if defined(DFSDM1_Channel0) 00284 #define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1 00285 #endif /* DFSDM1_Channel0 */ 00286 /** 00287 @endcond 00288 */ 00289 00290 /** 00291 * @} 00292 */ 00293 00294 /* Exported macro ------------------------------------------------------------*/ 00295 /* Exported functions --------------------------------------------------------*/ 00296 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 00297 * @{ 00298 */ 00299 00300 /** @defgroup BUS_LL_EF_AHB1 AHB1 00301 * @{ 00302 */ 00303 00304 /** 00305 * @brief Enable AHB1 peripherals clock. 00306 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n 00307 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n 00308 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n 00309 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n 00310 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n 00311 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n 00312 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n 00313 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock 00314 * @param Periphs This parameter can be a combination of the following values: 00315 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00316 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00317 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00318 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00319 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00320 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00321 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00322 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00323 * 00324 * (*) value not defined in all devices. 00325 * @retval None 00326 */ 00327 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 00328 { 00329 __IO uint32_t tmpreg; 00330 SET_BIT(RCC->AHB1ENR, Periphs); 00331 /* Delay after an RCC peripheral clock enabling */ 00332 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 00333 (void)tmpreg; 00334 } 00335 00336 /** 00337 * @brief Check if AHB1 peripheral clock is enabled or not 00338 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n 00339 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n 00340 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n 00341 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n 00342 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n 00343 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n 00344 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n 00345 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock 00346 * @param Periphs This parameter can be a combination of the following values: 00347 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00348 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00349 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00350 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00351 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00352 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00353 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00354 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00355 * 00356 * (*) value not defined in all devices. 00357 * @retval State of Periphs (1 or 0). 00358 */ 00359 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 00360 { 00361 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); 00362 } 00363 00364 /** 00365 * @brief Disable AHB1 peripherals clock. 00366 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n 00367 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n 00368 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n 00369 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n 00370 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n 00371 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n 00372 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n 00373 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock 00374 * @param Periphs This parameter can be a combination of the following values: 00375 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00376 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00377 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00378 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00379 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00380 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00381 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00382 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00383 * 00384 * (*) value not defined in all devices. 00385 * @retval None 00386 */ 00387 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 00388 { 00389 CLEAR_BIT(RCC->AHB1ENR, Periphs); 00390 } 00391 00392 /** 00393 * @brief Force AHB1 peripherals reset. 00394 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n 00395 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n 00396 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n 00397 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n 00398 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n 00399 * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n 00400 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n 00401 * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset 00402 * @param Periphs This parameter can be a combination of the following values: 00403 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00404 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00405 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00406 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00407 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00408 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00409 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00410 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00411 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00412 * 00413 * (*) value not defined in all devices. 00414 * @retval None 00415 */ 00416 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 00417 { 00418 SET_BIT(RCC->AHB1RSTR, Periphs); 00419 } 00420 00421 /** 00422 * @brief Release AHB1 peripherals reset. 00423 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n 00424 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n 00425 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n 00426 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n 00427 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n 00428 * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n 00429 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n 00430 * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset 00431 * @param Periphs This parameter can be a combination of the following values: 00432 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00433 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00434 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00435 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00436 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00437 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00438 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00439 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00440 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00441 * 00442 * (*) value not defined in all devices. 00443 * @retval None 00444 */ 00445 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 00446 { 00447 CLEAR_BIT(RCC->AHB1RSTR, Periphs); 00448 } 00449 00450 /** 00451 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes 00452 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00453 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00454 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00455 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00456 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00457 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00458 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00459 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00460 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep 00461 * @param Periphs This parameter can be a combination of the following values: 00462 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00463 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00464 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00465 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00466 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 00467 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00468 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00469 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00470 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00471 * 00472 * (*) value not defined in all devices. 00473 * @retval None 00474 */ 00475 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) 00476 { 00477 __IO uint32_t tmpreg; 00478 SET_BIT(RCC->AHB1SMENR, Periphs); 00479 /* Delay after an RCC peripheral clock enabling */ 00480 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs); 00481 (void)tmpreg; 00482 } 00483 00484 /** 00485 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes 00486 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00487 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00488 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00489 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00490 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00491 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00492 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00493 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00494 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep 00495 * @param Periphs This parameter can be a combination of the following values: 00496 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00497 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00498 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00499 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00500 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 00501 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00502 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00503 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00504 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00505 * 00506 * (*) value not defined in all devices. 00507 * @retval None 00508 */ 00509 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) 00510 { 00511 CLEAR_BIT(RCC->AHB1SMENR, Periphs); 00512 } 00513 00514 /** 00515 * @} 00516 */ 00517 00518 /** @defgroup BUS_LL_EF_AHB2 AHB2 00519 * @{ 00520 */ 00521 00522 /** 00523 * @brief Enable AHB2 peripherals clock. 00524 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n 00525 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n 00526 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n 00527 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n 00528 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n 00529 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n 00530 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n 00531 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n 00532 * AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n 00533 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n 00534 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n 00535 * AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n 00536 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n 00537 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n 00538 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n 00539 * AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock\n 00540 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock 00541 * @param Periphs This parameter can be a combination of the following values: 00542 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00543 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00544 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00545 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00546 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00547 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00548 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00549 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00550 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00551 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00552 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00553 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00554 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00555 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00556 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00557 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00558 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00559 * 00560 * (*) value not defined in all devices. 00561 * @retval None 00562 */ 00563 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 00564 { 00565 __IO uint32_t tmpreg; 00566 SET_BIT(RCC->AHB2ENR, Periphs); 00567 /* Delay after an RCC peripheral clock enabling */ 00568 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 00569 (void)tmpreg; 00570 } 00571 00572 /** 00573 * @brief Check if AHB2 peripheral clock is enabled or not 00574 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n 00575 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n 00576 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n 00577 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n 00578 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n 00579 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n 00580 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n 00581 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n 00582 * AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n 00583 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n 00584 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n 00585 * AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n 00586 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n 00587 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n 00588 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n 00589 * AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock\n 00590 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock 00591 * @param Periphs This parameter can be a combination of the following values: 00592 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00593 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00594 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00595 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00596 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00597 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00598 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00599 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00600 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00601 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00602 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00603 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00604 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00605 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00606 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00607 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00608 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00609 * 00610 * (*) value not defined in all devices. 00611 * @retval State of Periphs (1 or 0). 00612 */ 00613 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 00614 { 00615 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); 00616 } 00617 00618 /** 00619 * @brief Disable AHB2 peripherals clock. 00620 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n 00621 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n 00622 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n 00623 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n 00624 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n 00625 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n 00626 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n 00627 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n 00628 * AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n 00629 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n 00630 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n 00631 * AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n 00632 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n 00633 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n 00634 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n 00635 * AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock\n 00636 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock 00637 * @param Periphs This parameter can be a combination of the following values: 00638 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00639 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00640 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00641 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00642 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00643 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00644 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00645 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00646 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00647 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00648 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00649 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00650 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00651 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00652 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00653 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00654 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00655 * 00656 * (*) value not defined in all devices. 00657 * @retval None 00658 */ 00659 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) 00660 { 00661 CLEAR_BIT(RCC->AHB2ENR, Periphs); 00662 } 00663 00664 /** 00665 * @brief Force AHB2 peripherals reset. 00666 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n 00667 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n 00668 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n 00669 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n 00670 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n 00671 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n 00672 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n 00673 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n 00674 * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset\n 00675 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n 00676 * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n 00677 * AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n 00678 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n 00679 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n 00680 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n 00681 * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset\n 00682 * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset 00683 * @param Periphs This parameter can be a combination of the following values: 00684 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00685 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00686 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00687 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00688 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00689 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00690 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00691 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00692 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00693 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00694 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00695 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00696 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00697 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00698 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00699 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00700 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00701 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00702 * 00703 * (*) value not defined in all devices. 00704 * @retval None 00705 */ 00706 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) 00707 { 00708 SET_BIT(RCC->AHB2RSTR, Periphs); 00709 } 00710 00711 /** 00712 * @brief Release AHB2 peripherals reset. 00713 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n 00714 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n 00715 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n 00716 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n 00717 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n 00718 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n 00719 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n 00720 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n 00721 * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset\n 00722 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n 00723 * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n 00724 * AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n 00725 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n 00726 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n 00727 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n 00728 * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset\n 00729 * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset 00730 * @param Periphs This parameter can be a combination of the following values: 00731 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00732 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00733 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00734 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00735 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00736 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00737 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00738 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00739 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00740 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00741 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00742 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00743 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00744 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00745 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00746 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00747 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00748 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00749 * 00750 * (*) value not defined in all devices. 00751 * @retval None 00752 */ 00753 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) 00754 { 00755 CLEAR_BIT(RCC->AHB2RSTR, Periphs); 00756 } 00757 00758 /** 00759 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes 00760 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00761 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00762 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00763 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00764 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00765 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00766 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00767 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00768 * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00769 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00770 * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00771 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00772 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00773 * AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00774 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00775 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00776 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00777 * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00778 * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep 00779 * @param Periphs This parameter can be a combination of the following values: 00780 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00781 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00782 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00783 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00784 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00785 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00786 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00787 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00788 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00789 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 00790 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) 00791 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00792 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00793 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00794 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00795 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00796 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00797 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00798 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00799 * 00800 * (*) value not defined in all devices. 00801 * @retval None 00802 */ 00803 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) 00804 { 00805 __IO uint32_t tmpreg; 00806 SET_BIT(RCC->AHB2SMENR, Periphs); 00807 /* Delay after an RCC peripheral clock enabling */ 00808 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs); 00809 (void)tmpreg; 00810 } 00811 00812 /** 00813 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes 00814 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00815 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00816 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00817 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00818 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00819 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00820 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00821 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00822 * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00823 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00824 * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00825 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00826 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00827 * AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00828 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00829 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00830 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00831 * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00832 * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep 00833 * @param Periphs This parameter can be a combination of the following values: 00834 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00835 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00836 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00837 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00838 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00839 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00840 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00841 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00842 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00843 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 00844 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) 00845 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00846 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00847 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00848 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00849 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00850 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00851 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00852 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00853 * 00854 * (*) value not defined in all devices. 00855 * @retval None 00856 */ 00857 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) 00858 { 00859 CLEAR_BIT(RCC->AHB2SMENR, Periphs); 00860 } 00861 00862 /** 00863 * @} 00864 */ 00865 00866 /** @defgroup BUS_LL_EF_AHB3 AHB3 00867 * @{ 00868 */ 00869 00870 /** 00871 * @brief Enable AHB3 peripherals clock. 00872 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n 00873 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n 00874 * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n 00875 * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock 00876 * @param Periphs This parameter can be a combination of the following values: 00877 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00878 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00879 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00880 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00881 * 00882 * (*) value not defined in all devices. 00883 * @retval None 00884 */ 00885 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) 00886 { 00887 __IO uint32_t tmpreg; 00888 SET_BIT(RCC->AHB3ENR, Periphs); 00889 /* Delay after an RCC peripheral clock enabling */ 00890 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 00891 (void)tmpreg; 00892 } 00893 00894 /** 00895 * @brief Check if AHB3 peripheral clock is enabled or not 00896 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n 00897 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n 00898 * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n 00899 * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock 00900 * @param Periphs This parameter can be a combination of the following values: 00901 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00902 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00903 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00904 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00905 * 00906 * (*) value not defined in all devices. 00907 * @retval State of Periphs (1 or 0). 00908 */ 00909 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 00910 { 00911 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); 00912 } 00913 00914 /** 00915 * @brief Disable AHB3 peripherals clock. 00916 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n 00917 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n 00918 * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n 00919 * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock 00920 * @param Periphs This parameter can be a combination of the following values: 00921 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00922 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00923 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00924 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00925 * 00926 * (*) value not defined in all devices. 00927 * @retval None 00928 */ 00929 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) 00930 { 00931 CLEAR_BIT(RCC->AHB3ENR, Periphs); 00932 } 00933 00934 /** 00935 * @brief Force AHB3 peripherals reset. 00936 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n 00937 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n 00938 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n 00939 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset 00940 * @param Periphs This parameter can be a combination of the following values: 00941 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL 00942 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00943 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00944 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00945 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00946 * 00947 * (*) value not defined in all devices. 00948 * @retval None 00949 */ 00950 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) 00951 { 00952 SET_BIT(RCC->AHB3RSTR, Periphs); 00953 } 00954 00955 /** 00956 * @brief Release AHB3 peripherals reset. 00957 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n 00958 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n 00959 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n 00960 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset 00961 * @param Periphs This parameter can be a combination of the following values: 00962 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00963 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00964 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00965 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00966 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00967 * 00968 * (*) value not defined in all devices. 00969 * @retval None 00970 */ 00971 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) 00972 { 00973 CLEAR_BIT(RCC->AHB3RSTR, Periphs); 00974 } 00975 00976 /** 00977 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes 00978 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n 00979 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep\n 00980 * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n 00981 * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_EnableClockStopSleep 00982 * @param Periphs This parameter can be a combination of the following values: 00983 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00984 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00985 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00986 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00987 * 00988 * (*) value not defined in all devices. 00989 * @retval None 00990 */ 00991 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) 00992 { 00993 __IO uint32_t tmpreg; 00994 SET_BIT(RCC->AHB3SMENR, Periphs); 00995 /* Delay after an RCC peripheral clock enabling */ 00996 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs); 00997 (void)tmpreg; 00998 } 00999 01000 /** 01001 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes 01002 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n 01003 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep\n 01004 * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n 01005 * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n 01006 * @param Periphs This parameter can be a combination of the following values: 01007 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01008 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01009 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 01010 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 01011 * 01012 * (*) value not defined in all devices. 01013 * @retval None 01014 */ 01015 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) 01016 { 01017 CLEAR_BIT(RCC->AHB3SMENR, Periphs); 01018 } 01019 01020 /** 01021 * @} 01022 */ 01023 01024 /** @defgroup BUS_LL_EF_APB1 APB1 01025 * @{ 01026 */ 01027 01028 /** 01029 * @brief Enable APB1 peripherals clock. 01030 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n 01031 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n 01032 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n 01033 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n 01034 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n 01035 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n 01036 * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n 01037 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n 01038 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n 01039 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n 01040 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n 01041 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n 01042 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n 01043 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n 01044 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n 01045 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n 01046 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n 01047 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n 01048 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n 01049 * APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n 01050 * APB1ENR1 USBFSEN LL_APB1_GRP1_EnableClock\n 01051 * APB1ENR1 CAN2EN LL_APB1_GRP1_EnableClock\n 01052 * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n 01053 * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n 01054 * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n 01055 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock 01056 * @param Periphs This parameter can be a combination of the following values: 01057 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01058 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01059 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01060 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01061 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01062 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01063 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01064 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01065 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01066 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01067 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01068 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01069 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01070 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01071 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01072 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01073 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01074 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01075 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01076 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01077 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01078 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01079 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01080 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01081 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01082 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01083 * 01084 * (*) value not defined in all devices. 01085 * @retval None 01086 */ 01087 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 01088 { 01089 __IO uint32_t tmpreg; 01090 SET_BIT(RCC->APB1ENR1, Periphs); 01091 /* Delay after an RCC peripheral clock enabling */ 01092 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); 01093 (void)tmpreg; 01094 } 01095 01096 /** 01097 * @brief Enable APB1 peripherals clock. 01098 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n 01099 * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n 01100 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n 01101 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock 01102 * @param Periphs This parameter can be a combination of the following values: 01103 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01104 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01105 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01106 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01107 * 01108 * (*) value not defined in all devices. 01109 * @retval None 01110 */ 01111 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) 01112 { 01113 __IO uint32_t tmpreg; 01114 SET_BIT(RCC->APB1ENR2, Periphs); 01115 /* Delay after an RCC peripheral clock enabling */ 01116 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); 01117 (void)tmpreg; 01118 } 01119 01120 /** 01121 * @brief Check if APB1 peripheral clock is enabled or not 01122 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n 01123 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n 01124 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n 01125 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n 01126 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n 01127 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n 01128 * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n 01129 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n 01130 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n 01131 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n 01132 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n 01133 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n 01134 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n 01135 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n 01136 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n 01137 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n 01138 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n 01139 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n 01140 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n 01141 * APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n 01142 * APB1ENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock\n 01143 * APB1ENR1 CAN2EN LL_APB1_GRP1_IsEnabledClock\n 01144 * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n 01145 * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n 01146 * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n 01147 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock 01148 * @param Periphs This parameter can be a combination of the following values: 01149 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01150 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01151 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01152 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01153 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01154 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01155 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01156 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01157 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01158 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01159 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01160 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01161 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01162 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01163 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01164 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01165 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01166 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01167 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01168 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01169 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01170 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01171 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01172 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01173 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01174 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01175 * 01176 * (*) value not defined in all devices. 01177 * @retval State of Periphs (1 or 0). 01178 */ 01179 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 01180 { 01181 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL); 01182 } 01183 01184 /** 01185 * @brief Check if APB1 peripheral clock is enabled or not 01186 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n 01187 * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n 01188 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n 01189 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock 01190 * @param Periphs This parameter can be a combination of the following values: 01191 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01192 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01193 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01194 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01195 * 01196 * (*) value not defined in all devices. 01197 * @retval State of Periphs (1 or 0). 01198 */ 01199 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) 01200 { 01201 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); 01202 } 01203 01204 /** 01205 * @brief Disable APB1 peripherals clock. 01206 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n 01207 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n 01208 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n 01209 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n 01210 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n 01211 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n 01212 * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n 01213 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n 01214 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n 01215 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n 01216 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n 01217 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n 01218 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n 01219 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n 01220 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n 01221 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n 01222 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n 01223 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n 01224 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n 01225 * APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n 01226 * APB1ENR1 USBFSEN LL_APB1_GRP1_DisableClock\n 01227 * APB1ENR1 CAN2EN LL_APB1_GRP1_DisableClock\n 01228 * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n 01229 * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n 01230 * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n 01231 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock 01232 * @param Periphs This parameter can be a combination of the following values: 01233 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01234 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01235 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01236 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01237 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01238 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01239 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01240 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01241 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01242 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01243 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01244 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01245 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01246 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01247 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01248 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01249 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01250 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01251 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01252 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01253 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01254 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01255 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01256 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01257 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01258 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01259 * 01260 * (*) value not defined in all devices. 01261 * @retval None 01262 */ 01263 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 01264 { 01265 CLEAR_BIT(RCC->APB1ENR1, Periphs); 01266 } 01267 01268 /** 01269 * @brief Disable APB1 peripherals clock. 01270 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n 01271 * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n 01272 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n 01273 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock 01274 * @param Periphs This parameter can be a combination of the following values: 01275 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01276 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01277 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01278 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01279 * 01280 * (*) value not defined in all devices. 01281 * @retval None 01282 */ 01283 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) 01284 { 01285 CLEAR_BIT(RCC->APB1ENR2, Periphs); 01286 } 01287 01288 /** 01289 * @brief Force APB1 peripherals reset. 01290 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n 01291 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n 01292 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n 01293 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n 01294 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n 01295 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n 01296 * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n 01297 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n 01298 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n 01299 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n 01300 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n 01301 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n 01302 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n 01303 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n 01304 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n 01305 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n 01306 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n 01307 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n 01308 * APB1RSTR1 USBFSRST LL_APB1_GRP1_ForceReset\n 01309 * APB1RSTR1 CAN2RST LL_APB1_GRP1_ForceReset\n 01310 * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n 01311 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n 01312 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n 01313 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset 01314 * @param Periphs This parameter can be a combination of the following values: 01315 * @arg @ref LL_APB1_GRP1_PERIPH_ALL 01316 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01317 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01318 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01319 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01320 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01321 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01322 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01323 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01324 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01325 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01326 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01327 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01328 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01329 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01330 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01331 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01332 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01333 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01334 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01335 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01336 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01337 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01338 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01339 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01340 * 01341 * (*) value not defined in all devices. 01342 * @retval None 01343 */ 01344 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 01345 { 01346 SET_BIT(RCC->APB1RSTR1, Periphs); 01347 } 01348 01349 /** 01350 * @brief Force APB1 peripherals reset. 01351 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n 01352 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n 01353 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n 01354 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset 01355 * @param Periphs This parameter can be a combination of the following values: 01356 * @arg @ref LL_APB1_GRP2_PERIPH_ALL 01357 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01358 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01359 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01360 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01361 * 01362 * (*) value not defined in all devices. 01363 * @retval None 01364 */ 01365 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) 01366 { 01367 SET_BIT(RCC->APB1RSTR2, Periphs); 01368 } 01369 01370 /** 01371 * @brief Release APB1 peripherals reset. 01372 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n 01373 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n 01374 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n 01375 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n 01376 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n 01377 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n 01378 * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n 01379 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n 01380 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n 01381 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n 01382 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n 01383 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n 01384 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n 01385 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n 01386 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n 01387 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n 01388 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n 01389 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n 01390 * APB1RSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset\n 01391 * APB1RSTR1 CAN2RST LL_APB1_GRP1_ReleaseReset\n 01392 * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n 01393 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n 01394 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n 01395 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset 01396 * @param Periphs This parameter can be a combination of the following values: 01397 * @arg @ref LL_APB1_GRP1_PERIPH_ALL 01398 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01399 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01400 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01401 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01402 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01403 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01404 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01405 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01406 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01407 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01408 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01409 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01410 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01411 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01412 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01413 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01414 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01415 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01416 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01417 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01418 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01419 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01420 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01421 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01422 * 01423 * (*) value not defined in all devices. 01424 * @retval None 01425 */ 01426 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 01427 { 01428 CLEAR_BIT(RCC->APB1RSTR1, Periphs); 01429 } 01430 01431 /** 01432 * @brief Release APB1 peripherals reset. 01433 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n 01434 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n 01435 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n 01436 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset 01437 * @param Periphs This parameter can be a combination of the following values: 01438 * @arg @ref LL_APB1_GRP2_PERIPH_ALL 01439 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01440 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01441 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01442 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01443 * 01444 * (*) value not defined in all devices. 01445 * @retval None 01446 */ 01447 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) 01448 { 01449 CLEAR_BIT(RCC->APB1RSTR2, Periphs); 01450 } 01451 01452 /** 01453 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes 01454 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01455 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01456 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01457 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01458 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01459 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01460 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01461 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01462 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01463 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01464 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01465 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01466 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01467 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01468 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01469 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01470 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01471 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01472 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01473 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01474 * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01475 * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01476 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01477 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01478 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01479 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep 01480 * @param Periphs This parameter can be a combination of the following values: 01481 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01482 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01483 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01484 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01485 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01486 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01487 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01488 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01489 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01490 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01491 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01492 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01493 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01494 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01495 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01496 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01497 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01498 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01499 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01500 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01501 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01502 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01503 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01504 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01505 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01506 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01507 * 01508 * (*) value not defined in all devices. 01509 * @retval None 01510 */ 01511 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) 01512 { 01513 __IO uint32_t tmpreg; 01514 SET_BIT(RCC->APB1SMENR1, Periphs); 01515 /* Delay after an RCC peripheral clock enabling */ 01516 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs); 01517 (void)tmpreg; 01518 } 01519 01520 /** 01521 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes 01522 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n 01523 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n 01524 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n 01525 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep 01526 * @param Periphs This parameter can be a combination of the following values: 01527 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01528 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01529 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01530 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01531 * 01532 * (*) value not defined in all devices. 01533 * @retval None 01534 */ 01535 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) 01536 { 01537 __IO uint32_t tmpreg; 01538 SET_BIT(RCC->APB1SMENR2, Periphs); 01539 /* Delay after an RCC peripheral clock enabling */ 01540 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs); 01541 (void)tmpreg; 01542 } 01543 01544 /** 01545 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes 01546 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01547 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01548 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01549 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01550 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01551 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01552 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01553 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01554 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01555 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01556 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01557 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01558 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01559 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01560 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01561 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01562 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01563 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01564 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01565 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01566 * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01567 * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01568 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01569 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01570 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01571 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep 01572 * @param Periphs This parameter can be a combination of the following values: 01573 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01574 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01575 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01576 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01577 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01578 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01579 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01580 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01581 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01582 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01583 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01584 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01585 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01586 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01587 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01588 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01589 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01590 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01591 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01592 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01593 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01594 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01595 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01596 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01597 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01598 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01599 * 01600 * (*) value not defined in all devices. 01601 * @retval None 01602 */ 01603 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) 01604 { 01605 CLEAR_BIT(RCC->APB1SMENR1, Periphs); 01606 } 01607 01608 /** 01609 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes 01610 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n 01611 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n 01612 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n 01613 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep 01614 * @param Periphs This parameter can be a combination of the following values: 01615 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01616 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01617 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01618 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01619 * 01620 * (*) value not defined in all devices. 01621 * @retval None 01622 */ 01623 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) 01624 { 01625 CLEAR_BIT(RCC->APB1SMENR2, Periphs); 01626 } 01627 01628 /** 01629 * @} 01630 */ 01631 01632 /** @defgroup BUS_LL_EF_APB2 APB2 01633 * @{ 01634 */ 01635 01636 /** 01637 * @brief Enable APB2 peripherals clock. 01638 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n 01639 * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n 01640 * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n 01641 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 01642 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 01643 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 01644 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n 01645 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n 01646 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n 01647 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n 01648 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n 01649 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n 01650 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n 01651 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n 01652 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock 01653 * @param Periphs This parameter can be a combination of the following values: 01654 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01655 * @arg @ref LL_APB2_GRP1_PERIPH_FW 01656 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01657 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01658 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01659 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01660 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01661 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01662 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01663 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01664 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01665 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01666 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01667 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01668 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01669 * 01670 * (*) value not defined in all devices. 01671 * @retval None 01672 */ 01673 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 01674 { 01675 __IO uint32_t tmpreg; 01676 SET_BIT(RCC->APB2ENR, Periphs); 01677 /* Delay after an RCC peripheral clock enabling */ 01678 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 01679 (void)tmpreg; 01680 } 01681 01682 /** 01683 * @brief Check if APB2 peripheral clock is enabled or not 01684 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n 01685 * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n 01686 * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n 01687 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n 01688 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n 01689 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n 01690 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n 01691 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n 01692 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n 01693 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n 01694 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n 01695 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n 01696 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n 01697 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n 01698 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock 01699 * @param Periphs This parameter can be a combination of the following values: 01700 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01701 * @arg @ref LL_APB2_GRP1_PERIPH_FW 01702 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01703 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01704 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01705 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01706 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01707 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01708 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01709 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01710 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01711 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01712 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01713 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01714 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01715 * 01716 * (*) value not defined in all devices. 01717 * @retval State of Periphs (1 or 0). 01718 */ 01719 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 01720 { 01721 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); 01722 } 01723 01724 /** 01725 * @brief Disable APB2 peripherals clock. 01726 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n 01727 * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n 01728 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n 01729 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n 01730 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n 01731 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n 01732 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n 01733 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n 01734 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n 01735 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n 01736 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n 01737 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n 01738 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n 01739 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock 01740 * @param Periphs This parameter can be a combination of the following values: 01741 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01742 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01743 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01744 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01745 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01746 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01747 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01748 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01749 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01750 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01751 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01752 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01753 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01754 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01755 * 01756 * (*) value not defined in all devices. 01757 * @retval None 01758 */ 01759 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) 01760 { 01761 CLEAR_BIT(RCC->APB2ENR, Periphs); 01762 } 01763 01764 /** 01765 * @brief Force APB2 peripherals reset. 01766 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n 01767 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n 01768 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n 01769 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n 01770 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n 01771 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n 01772 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n 01773 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n 01774 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n 01775 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n 01776 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n 01777 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n 01778 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n 01779 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset 01780 * @param Periphs This parameter can be a combination of the following values: 01781 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 01782 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01783 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01784 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01785 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01786 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01787 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01788 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01789 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01790 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01791 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01792 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01793 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01794 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01795 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01796 * 01797 * (*) value not defined in all devices. 01798 * @retval None 01799 */ 01800 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) 01801 { 01802 SET_BIT(RCC->APB2RSTR, Periphs); 01803 } 01804 01805 /** 01806 * @brief Release APB2 peripherals reset. 01807 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n 01808 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n 01809 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n 01810 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n 01811 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n 01812 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n 01813 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n 01814 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n 01815 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n 01816 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n 01817 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n 01818 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n 01819 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n 01820 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset 01821 * @param Periphs This parameter can be a combination of the following values: 01822 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 01823 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01824 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01825 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01826 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01827 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01828 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01829 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01830 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01831 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01832 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01833 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01834 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01835 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01836 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01837 * 01838 * (*) value not defined in all devices. 01839 * @retval None 01840 */ 01841 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) 01842 { 01843 CLEAR_BIT(RCC->APB2RSTR, Periphs); 01844 } 01845 01846 /** 01847 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes 01848 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n 01849 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01850 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01851 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01852 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01853 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01854 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01855 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01856 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01857 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01858 * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01859 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01860 * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n 01861 * APB2SMENR DSISMEN LL_APB2_GRP1_EnableClockStopSleep 01862 * @param Periphs This parameter can be a combination of the following values: 01863 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01864 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01865 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01866 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01867 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01868 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01869 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01870 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01871 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01872 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01873 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01874 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01875 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01876 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01877 * 01878 * (*) value not defined in all devices. 01879 * @retval None 01880 */ 01881 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) 01882 { 01883 __IO uint32_t tmpreg; 01884 SET_BIT(RCC->APB2SMENR, Periphs); 01885 /* Delay after an RCC peripheral clock enabling */ 01886 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); 01887 (void)tmpreg; 01888 } 01889 01890 /** 01891 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes 01892 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n 01893 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01894 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01895 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01896 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01897 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01898 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01899 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01900 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01901 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01902 * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01903 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01904 * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n 01905 * APB2SMENR DSISMEN LL_APB2_GRP1_DisableClockStopSleep 01906 * @param Periphs This parameter can be a combination of the following values: 01907 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01908 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01909 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01910 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01911 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01912 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01913 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01914 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01915 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01916 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01917 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01918 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01919 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01920 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01921 * 01922 * (*) value not defined in all devices. 01923 * @retval None 01924 */ 01925 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) 01926 { 01927 CLEAR_BIT(RCC->APB2SMENR, Periphs); 01928 } 01929 01930 /** 01931 * @} 01932 */ 01933 01934 01935 /** 01936 * @} 01937 */ 01938 01939 /** 01940 * @} 01941 */ 01942 01943 #endif /* defined(RCC) */ 01944 01945 /** 01946 * @} 01947 */ 01948 01949 #ifdef __cplusplus 01950 } 01951 #endif 01952 01953 #endif /* STM32L4xx_LL_BUS_H */ 01954
1.7.6.1