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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_dac.h 00004 * @author MCD Application Team 00005 * @brief Header file of DAC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_LL_DAC_H 00021 #define STM32L4xx_LL_DAC_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx.h" 00029 00030 /** @addtogroup STM32L4xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (DAC1) 00035 00036 /** @defgroup DAC_LL DAC 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 00043 /* Private constants ---------------------------------------------------------*/ 00044 /** @defgroup DAC_LL_Private_Constants DAC Private Constants 00045 * @{ 00046 */ 00047 00048 /* Internal masks for DAC channels definition */ 00049 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ 00050 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ 00051 /* - channel bits position into register SWTRIG */ 00052 /* - channel register offset of data holding register DHRx */ 00053 /* - channel register offset of data output register DORx */ 00054 /* - channel register offset of sample-and-hold sample time register SHSRx */ 00055 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ 00056 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ 00057 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) 00058 00059 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ 00060 #if defined(DAC_CHANNEL2_SUPPORT) 00061 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ 00062 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) 00063 #else 00064 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) 00065 #endif /* DAC_CHANNEL2_SUPPORT */ 00066 00067 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ 00068 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ 00069 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ 00070 #if defined(DAC_CHANNEL2_SUPPORT) 00071 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ 00072 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ 00073 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ 00074 #endif /* DAC_CHANNEL2_SUPPORT */ 00075 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U 00076 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U 00077 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U 00078 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) 00079 00080 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ 00081 #if defined(DAC_CHANNEL2_SUPPORT) 00082 #define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */ 00083 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) 00084 #else 00085 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) 00086 #endif /* DAC_CHANNEL2_SUPPORT */ 00087 00088 #define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */ 00089 #if defined(DAC_CHANNEL2_SUPPORT) 00090 #define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */ 00091 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) 00092 #else 00093 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET) 00094 #endif /* DAC_CHANNEL2_SUPPORT */ 00095 00096 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ 00097 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */ 00098 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */ 00099 00100 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ 00101 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ 00102 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ 00103 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */ 00104 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */ 00105 00106 /* DAC registers bits positions */ 00107 #if defined(DAC_CHANNEL2_SUPPORT) 00108 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos 00109 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos 00110 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos 00111 #endif /* DAC_CHANNEL2_SUPPORT */ 00112 00113 /* Miscellaneous data */ 00114 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ 00115 00116 /** 00117 * @} 00118 */ 00119 00120 00121 /* Private macros ------------------------------------------------------------*/ 00122 /** @defgroup DAC_LL_Private_Macros DAC Private Macros 00123 * @{ 00124 */ 00125 00126 /** 00127 * @brief Driver macro reserved for internal use: set a pointer to 00128 * a register from a register basis from which an offset 00129 * is applied. 00130 * @param __REG__ Register basis from which the offset is applied. 00131 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). 00132 * @retval Pointer to register address 00133 */ 00134 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 00135 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) 00136 00137 /** 00138 * @} 00139 */ 00140 00141 00142 /* Exported types ------------------------------------------------------------*/ 00143 #if defined(USE_FULL_LL_DRIVER) 00144 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure 00145 * @{ 00146 */ 00147 00148 /** 00149 * @brief Structure definition of some features of DAC instance. 00150 */ 00151 typedef struct 00152 { 00153 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). 00154 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE 00155 00156 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ 00157 00158 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. 00159 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE 00160 00161 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ 00162 00163 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. 00164 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS 00165 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE 00166 @note If waveform automatic generation mode is disabled, this parameter is discarded. 00167 00168 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude() 00169 depending on the wave automatic generation selected. */ 00170 00171 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. 00172 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER 00173 00174 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ 00175 00176 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel. 00177 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION 00178 00179 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */ 00180 00181 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel. 00182 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE 00183 00184 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */ 00185 } LL_DAC_InitTypeDef; 00186 00187 /** 00188 * @} 00189 */ 00190 #endif /* USE_FULL_LL_DRIVER */ 00191 00192 /* Exported constants --------------------------------------------------------*/ 00193 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants 00194 * @{ 00195 */ 00196 00197 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags 00198 * @brief Flags defines which can be used with LL_DAC_ReadReg function 00199 * @{ 00200 */ 00201 /* DAC channel 1 flags */ 00202 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ 00203 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */ 00204 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */ 00205 00206 #if defined(DAC_CHANNEL2_SUPPORT) 00207 /* DAC channel 2 flags */ 00208 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ 00209 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */ 00210 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */ 00211 #endif /* DAC_CHANNEL2_SUPPORT */ 00212 /** 00213 * @} 00214 */ 00215 00216 /** @defgroup DAC_LL_EC_IT DAC interruptions 00217 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions 00218 * @{ 00219 */ 00220 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ 00221 #if defined(DAC_CHANNEL2_SUPPORT) 00222 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ 00223 #endif /* DAC_CHANNEL2_SUPPORT */ 00224 /** 00225 * @} 00226 */ 00227 00228 /** @defgroup DAC_LL_EC_CHANNEL DAC channels 00229 * @{ 00230 */ 00231 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ 00232 #if defined(DAC_CHANNEL2_SUPPORT) 00233 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ 00234 #endif /* DAC_CHANNEL2_SUPPORT */ 00235 /** 00236 * @} 00237 */ 00238 #if defined (DAC_CR_HFSEL) /* High frequency interface mode */ 00239 00240 /** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode 00241 * @brief High frequency interface mode defines that can be used with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode 00242 * @{ 00243 */ 00244 #define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */ 00245 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_CR_HFSEL) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ 00246 /** 00247 * @} 00248 */ 00249 #endif /* High frequency interface mode */ 00250 00251 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode 00252 * @{ 00253 */ 00254 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000U /*!< DAC channel in mode normal operation */ 00255 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */ 00256 /** 00257 * @} 00258 */ 00259 00260 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source 00261 * @{ 00262 */ 00263 #if defined (DAC_CR_TSEL1_3) 00264 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM1 TRGO. */ 00265 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ 00266 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ 00267 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ 00268 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ 00269 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ 00270 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ 00271 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ 00272 #define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 TRGO. */ 00273 #define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 TRGO. */ 00274 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ 00275 #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */ 00276 #else 00277 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ 00278 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ 00279 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ 00280 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ 00281 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ 00282 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ 00283 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ 00284 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ 00285 #endif 00286 00287 /** 00288 * @} 00289 */ 00290 00291 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode 00292 * @{ 00293 */ 00294 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ 00295 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ 00296 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ 00297 /** 00298 * @} 00299 */ 00300 00301 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits 00302 * @{ 00303 */ 00304 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ 00305 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ 00306 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ 00307 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ 00308 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ 00309 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ 00310 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ 00311 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ 00312 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ 00313 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ 00314 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ 00315 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ 00316 /** 00317 * @} 00318 */ 00319 00320 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude 00321 * @{ 00322 */ 00323 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ 00324 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ 00325 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ 00326 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ 00327 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ 00328 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ 00329 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ 00330 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ 00331 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ 00332 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ 00333 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ 00334 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ 00335 /** 00336 * @} 00337 */ 00338 00339 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode 00340 * @{ 00341 */ 00342 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000U /*!< The selected DAC channel output is on mode normal. */ 00343 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */ 00344 /** 00345 * @} 00346 */ 00347 00348 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer 00349 * @{ 00350 */ 00351 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ 00352 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ 00353 /** 00354 * @} 00355 */ 00356 00357 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection 00358 * @{ 00359 */ 00360 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /*!< The selected DAC channel output is connected to external pin */ 00361 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */ 00362 /** 00363 * @} 00364 */ 00365 00366 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution 00367 * @{ 00368 */ 00369 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ 00370 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ 00371 /** 00372 * @} 00373 */ 00374 00375 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose 00376 * @{ 00377 */ 00378 /* List of DAC registers intended to be used (most commonly) with */ 00379 /* DMA transfer. */ 00380 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ 00381 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ 00382 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ 00383 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ 00384 /** 00385 * @} 00386 */ 00387 00388 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays 00389 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, 00390 * not timeout values. 00391 * For details on delays values, refer to descriptions in source code 00392 * above each literal definition. 00393 * @{ 00394 */ 00395 00396 /* Delay for DAC channel voltage settling time from DAC channel startup */ 00397 /* (transition from disable to enable). */ 00398 /* Note: DAC channel startup time depends on board application environment: */ 00399 /* impedance connected to DAC channel output. */ 00400 /* The delay below is specified under conditions: */ 00401 /* - voltage maximum transition (lowest to highest value) */ 00402 /* - until voltage reaches final value +-1LSB */ 00403 /* - DAC channel output buffer enabled */ 00404 /* - load impedance of 5kOhm (min), 50pF (max) */ 00405 /* Literal set to maximum value (refer to device datasheet, */ 00406 /* parameter "tWAKEUP"). */ 00407 /* Unit: us */ 00408 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ 00409 00410 00411 /* Delay for DAC channel voltage settling time. */ 00412 /* Note: DAC channel startup time depends on board application environment: */ 00413 /* impedance connected to DAC channel output. */ 00414 /* The delay below is specified under conditions: */ 00415 /* - voltage maximum transition (lowest to highest value) */ 00416 /* - until voltage reaches final value +-1LSB */ 00417 /* - DAC channel output buffer enabled */ 00418 /* - load impedance of 5kOhm min, 50pF max */ 00419 /* Literal set to maximum value (refer to device datasheet, */ 00420 /* parameter "tSETTLING"). */ 00421 /* Unit: us */ 00422 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3U /*!< Delay for DAC channel voltage settling time */ 00423 00424 /** 00425 * @} 00426 */ 00427 00428 /** 00429 * @} 00430 */ 00431 00432 /* Exported macro ------------------------------------------------------------*/ 00433 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros 00434 * @{ 00435 */ 00436 00437 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros 00438 * @{ 00439 */ 00440 00441 /** 00442 * @brief Write a value in DAC register 00443 * @param __INSTANCE__ DAC Instance 00444 * @param __REG__ Register to be written 00445 * @param __VALUE__ Value to be written in the register 00446 * @retval None 00447 */ 00448 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00449 00450 /** 00451 * @brief Read a value in DAC register 00452 * @param __INSTANCE__ DAC Instance 00453 * @param __REG__ Register to be read 00454 * @retval Register value 00455 */ 00456 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00457 00458 /** 00459 * @} 00460 */ 00461 00462 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro 00463 * @{ 00464 */ 00465 00466 /** 00467 * @brief Helper macro to get DAC channel number in decimal format 00468 * from literals LL_DAC_CHANNEL_x. 00469 * Example: 00470 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) 00471 * will return decimal number "1". 00472 * @note The input can be a value from functions where a channel 00473 * number is returned. 00474 * @param __CHANNEL__ This parameter can be one of the following values: 00475 * @arg @ref LL_DAC_CHANNEL_1 00476 * @arg @ref LL_DAC_CHANNEL_2 00477 * @retval 1...2 00478 */ 00479 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 00480 ((__CHANNEL__) & DAC_SWTR_CHX_MASK) 00481 00482 /** 00483 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x 00484 * from number in decimal format. 00485 * Example: 00486 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) 00487 * will return a data equivalent to "LL_DAC_CHANNEL_1". 00488 * @note If the input parameter does not correspond to a DAC channel, 00489 * this macro returns value '0'. 00490 * @param __DECIMAL_NB__ 1...2 00491 * @retval Returned value can be one of the following values: 00492 * @arg @ref LL_DAC_CHANNEL_1 00493 * @arg @ref LL_DAC_CHANNEL_2 00494 */ 00495 #if defined(DAC_CHANNEL2_SUPPORT) 00496 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 00497 (((__DECIMAL_NB__) == 1U) \ 00498 ? ( \ 00499 LL_DAC_CHANNEL_1 \ 00500 ) \ 00501 : \ 00502 (((__DECIMAL_NB__) == 2U) \ 00503 ? ( \ 00504 LL_DAC_CHANNEL_2 \ 00505 ) \ 00506 : \ 00507 ( \ 00508 0U \ 00509 ) \ 00510 ) \ 00511 ) 00512 #else 00513 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 00514 (((__DECIMAL_NB__) == 1U) \ 00515 ? ( \ 00516 LL_DAC_CHANNEL_1 \ 00517 ) \ 00518 : \ 00519 ( \ 00520 0U \ 00521 ) \ 00522 ) 00523 #endif /* DAC_CHANNEL2_SUPPORT */ 00524 00525 /** 00526 * @brief Helper macro to define the DAC conversion data full-scale digital 00527 * value corresponding to the selected DAC resolution. 00528 * @note DAC conversion data full-scale corresponds to voltage range 00529 * determined by analog voltage references Vref+ and Vref- 00530 * (refer to reference manual). 00531 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 00532 * @arg @ref LL_DAC_RESOLUTION_12B 00533 * @arg @ref LL_DAC_RESOLUTION_8B 00534 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 00535 */ 00536 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 00537 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) 00538 00539 /** 00540 * @brief Helper macro to calculate the DAC conversion data (unit: digital 00541 * value) corresponding to a voltage (unit: mVolt). 00542 * @note This helper macro is intended to provide input data in voltage 00543 * rather than digital value, 00544 * to be used with LL DAC functions such as 00545 * @ref LL_DAC_ConvertData12RightAligned(). 00546 * @note Analog reference voltage (Vref+) must be either known from 00547 * user board environment or can be calculated using ADC measurement 00548 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 00549 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 00550 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel 00551 * (unit: mVolt). 00552 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 00553 * @arg @ref LL_DAC_RESOLUTION_12B 00554 * @arg @ref LL_DAC_RESOLUTION_8B 00555 * @retval DAC conversion data (unit: digital value) 00556 */ 00557 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ 00558 __DAC_VOLTAGE__,\ 00559 __DAC_RESOLUTION__) \ 00560 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 00561 / (__VREFANALOG_VOLTAGE__) \ 00562 ) 00563 00564 /** 00565 * @} 00566 */ 00567 00568 /** 00569 * @} 00570 */ 00571 00572 00573 /* Exported functions --------------------------------------------------------*/ 00574 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions 00575 * @{ 00576 */ 00577 00578 #if defined (DAC_CR_HFSEL) /* High frequency interface mode */ 00579 00580 /** @defgroup DAC_LL_EF_High_Frequency_Configuration High Frequency Configuration of DAC instance 00581 * @{ 00582 */ 00583 /** 00584 * @brief Set the high frequency interface mode for the selected DAC instance 00585 * @rmtoll CR HFSEL LL_DAC_SetHighFrequencyMode 00586 * @param DACx DAC instance 00587 * @param HighFreqMode This parameter can be one of the following values: 00588 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE 00589 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ 00590 * @retval None 00591 */ 00592 __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode) 00593 { 00594 MODIFY_REG(DACx->CR, DAC_CR_HFSEL, HighFreqMode); 00595 } 00596 00597 /** 00598 * @brief Get the high frequency interface mode for the selected DAC instance 00599 * @rmtoll CR HFSEL LL_DAC_GetHighFrequencyMode 00600 * @param DACx DAC instance 00601 * @retval Returned value can be one of the following values: 00602 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE 00603 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ 00604 */ 00605 __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx) 00606 { 00607 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_HFSEL)); 00608 } 00609 /** 00610 * @} 00611 */ 00612 00613 #endif /* High frequency interface mode */ 00614 00615 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels 00616 * @{ 00617 */ 00618 00619 /** 00620 * @brief Set the operating mode for the selected DAC channel: 00621 * calibration or normal operating mode. 00622 * @rmtoll CR CEN1 LL_DAC_SetMode\n 00623 * CR CEN2 LL_DAC_SetMode 00624 * @param DACx DAC instance 00625 * @param DAC_Channel This parameter can be one of the following values: 00626 * @arg @ref LL_DAC_CHANNEL_1 00627 * @arg @ref LL_DAC_CHANNEL_2 00628 * @param ChannelMode This parameter can be one of the following values: 00629 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION 00630 * @arg @ref LL_DAC_MODE_CALIBRATION 00631 * @retval None 00632 */ 00633 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode) 00634 { 00635 MODIFY_REG(DACx->CR, 00636 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00637 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00638 } 00639 00640 /** 00641 * @brief Get the operating mode for the selected DAC channel: 00642 * calibration or normal operating mode. 00643 * @rmtoll CR CEN1 LL_DAC_GetMode\n 00644 * CR CEN2 LL_DAC_GetMode 00645 * @param DACx DAC instance 00646 * @param DAC_Channel This parameter can be one of the following values: 00647 * @arg @ref LL_DAC_CHANNEL_1 00648 * @arg @ref LL_DAC_CHANNEL_2 00649 * @retval Returned value can be one of the following values: 00650 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION 00651 * @arg @ref LL_DAC_MODE_CALIBRATION 00652 */ 00653 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00654 { 00655 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00656 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00657 ); 00658 } 00659 00660 /** 00661 * @brief Set the offset trimming value for the selected DAC channel. 00662 * Trimming has an impact when output buffer is enabled 00663 * and is intended to replace factory calibration default values. 00664 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n 00665 * CCR OTRIM2 LL_DAC_SetTrimmingValue 00666 * @param DACx DAC instance 00667 * @param DAC_Channel This parameter can be one of the following values: 00668 * @arg @ref LL_DAC_CHANNEL_1 00669 * @arg @ref LL_DAC_CHANNEL_2 00670 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F 00671 * @retval None 00672 */ 00673 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue) 00674 { 00675 MODIFY_REG(DACx->CCR, 00676 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00677 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00678 } 00679 00680 /** 00681 * @brief Get the offset trimming value for the selected DAC channel. 00682 * Trimming has an impact when output buffer is enabled 00683 * and is intended to replace factory calibration default values. 00684 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n 00685 * CCR OTRIM2 LL_DAC_GetTrimmingValue 00686 * @param DACx DAC instance 00687 * @param DAC_Channel This parameter can be one of the following values: 00688 * @arg @ref LL_DAC_CHANNEL_1 00689 * @arg @ref LL_DAC_CHANNEL_2 00690 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F 00691 */ 00692 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00693 { 00694 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00695 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00696 ); 00697 } 00698 00699 /** 00700 * @brief Set the conversion trigger source for the selected DAC channel. 00701 * @note For conversion trigger source to be effective, DAC trigger 00702 * must be enabled using function @ref LL_DAC_EnableTrigger(). 00703 * @note To set conversion trigger source, DAC channel must be disabled. 00704 * Otherwise, the setting is discarded. 00705 * @note Availability of parameters of trigger sources from timer 00706 * depends on timers availability on the selected device. 00707 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n 00708 * CR TSEL2 LL_DAC_SetTriggerSource 00709 * @param DACx DAC instance 00710 * @param DAC_Channel This parameter can be one of the following values: 00711 * @arg @ref LL_DAC_CHANNEL_1 00712 * @arg @ref LL_DAC_CHANNEL_2 00713 * @param TriggerSource This parameter can be one of the following values: 00714 * @arg @ref LL_DAC_TRIG_SOFTWARE 00715 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO 00716 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 00717 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 00718 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 00719 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 00720 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 00721 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO 00722 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO 00723 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT 00724 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT 00725 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 00726 * @retval None 00727 */ 00728 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) 00729 { 00730 MODIFY_REG(DACx->CR, 00731 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00732 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00733 } 00734 00735 /** 00736 * @brief Get the conversion trigger source for the selected DAC channel. 00737 * @note For conversion trigger source to be effective, DAC trigger 00738 * must be enabled using function @ref LL_DAC_EnableTrigger(). 00739 * @note Availability of parameters of trigger sources from timer 00740 * depends on timers availability on the selected device. 00741 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n 00742 * CR TSEL2 LL_DAC_GetTriggerSource 00743 * @param DACx DAC instance 00744 * @param DAC_Channel This parameter can be one of the following values: 00745 * @arg @ref LL_DAC_CHANNEL_1 00746 * @arg @ref LL_DAC_CHANNEL_2 (1) 00747 * 00748 * (1) On this STM32 serie, parameter not available on all devices. 00749 * Refer to device datasheet for channels availability. 00750 * @retval Returned value can be one of the following values: 00751 * @arg @ref LL_DAC_TRIG_SOFTWARE 00752 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO 00753 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 00754 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 00755 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 00756 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 00757 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 00758 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO 00759 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO 00760 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT 00761 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT 00762 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 00763 */ 00764 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00765 { 00766 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00767 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00768 ); 00769 } 00770 00771 /** 00772 * @brief Set the waveform automatic generation mode 00773 * for the selected DAC channel. 00774 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n 00775 * CR WAVE2 LL_DAC_SetWaveAutoGeneration 00776 * @param DACx DAC instance 00777 * @param DAC_Channel This parameter can be one of the following values: 00778 * @arg @ref LL_DAC_CHANNEL_1 00779 * @arg @ref LL_DAC_CHANNEL_2 (1) 00780 * 00781 * (1) On this STM32 serie, parameter not available on all devices. 00782 * Refer to device datasheet for channels availability. 00783 * @param WaveAutoGeneration This parameter can be one of the following values: 00784 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 00785 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 00786 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 00787 * @retval None 00788 */ 00789 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) 00790 { 00791 MODIFY_REG(DACx->CR, 00792 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00793 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00794 } 00795 00796 /** 00797 * @brief Get the waveform automatic generation mode 00798 * for the selected DAC channel. 00799 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n 00800 * CR WAVE2 LL_DAC_GetWaveAutoGeneration 00801 * @param DACx DAC instance 00802 * @param DAC_Channel This parameter can be one of the following values: 00803 * @arg @ref LL_DAC_CHANNEL_1 00804 * @arg @ref LL_DAC_CHANNEL_2 (1) 00805 * 00806 * (1) On this STM32 serie, parameter not available on all devices. 00807 * Refer to device datasheet for channels availability. 00808 * @retval Returned value can be one of the following values: 00809 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 00810 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 00811 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 00812 */ 00813 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00814 { 00815 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00816 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00817 ); 00818 } 00819 00820 /** 00821 * @brief Set the noise waveform generation for the selected DAC channel: 00822 * Noise mode and parameters LFSR (linear feedback shift register). 00823 * @note For wave generation to be effective, DAC channel 00824 * wave generation mode must be enabled using 00825 * function @ref LL_DAC_SetWaveAutoGeneration(). 00826 * @note This setting can be set when the selected DAC channel is disabled 00827 * (otherwise, the setting operation is ignored). 00828 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n 00829 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR 00830 * @param DACx DAC instance 00831 * @param DAC_Channel This parameter can be one of the following values: 00832 * @arg @ref LL_DAC_CHANNEL_1 00833 * @arg @ref LL_DAC_CHANNEL_2 (1) 00834 * 00835 * (1) On this STM32 serie, parameter not available on all devices. 00836 * Refer to device datasheet for channels availability. 00837 * @param NoiseLFSRMask This parameter can be one of the following values: 00838 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 00839 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 00840 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 00841 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 00842 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 00843 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 00844 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 00845 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 00846 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 00847 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 00848 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 00849 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 00850 * @retval None 00851 */ 00852 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) 00853 { 00854 MODIFY_REG(DACx->CR, 00855 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00856 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00857 } 00858 00859 /** 00860 * @brief Get the noise waveform generation for the selected DAC channel: 00861 * Noise mode and parameters LFSR (linear feedback shift register). 00862 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n 00863 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR 00864 * @param DACx DAC instance 00865 * @param DAC_Channel This parameter can be one of the following values: 00866 * @arg @ref LL_DAC_CHANNEL_1 00867 * @arg @ref LL_DAC_CHANNEL_2 (1) 00868 * 00869 * (1) On this STM32 serie, parameter not available on all devices. 00870 * Refer to device datasheet for channels availability. 00871 * @retval Returned value can be one of the following values: 00872 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 00873 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 00874 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 00875 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 00876 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 00877 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 00878 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 00879 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 00880 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 00881 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 00882 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 00883 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 00884 */ 00885 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00886 { 00887 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00888 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00889 ); 00890 } 00891 00892 /** 00893 * @brief Set the triangle waveform generation for the selected DAC channel: 00894 * triangle mode and amplitude. 00895 * @note For wave generation to be effective, DAC channel 00896 * wave generation mode must be enabled using 00897 * function @ref LL_DAC_SetWaveAutoGeneration(). 00898 * @note This setting can be set when the selected DAC channel is disabled 00899 * (otherwise, the setting operation is ignored). 00900 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n 00901 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude 00902 * @param DACx DAC instance 00903 * @param DAC_Channel This parameter can be one of the following values: 00904 * @arg @ref LL_DAC_CHANNEL_1 00905 * @arg @ref LL_DAC_CHANNEL_2 (1) 00906 * 00907 * (1) On this STM32 serie, parameter not available on all devices. 00908 * Refer to device datasheet for channels availability. 00909 * @param TriangleAmplitude This parameter can be one of the following values: 00910 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 00911 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 00912 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 00913 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 00914 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 00915 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 00916 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 00917 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 00918 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 00919 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 00920 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 00921 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 00922 * @retval None 00923 */ 00924 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, 00925 uint32_t TriangleAmplitude) 00926 { 00927 MODIFY_REG(DACx->CR, 00928 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00929 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00930 } 00931 00932 /** 00933 * @brief Get the triangle waveform generation for the selected DAC channel: 00934 * triangle mode and amplitude. 00935 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n 00936 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude 00937 * @param DACx DAC instance 00938 * @param DAC_Channel This parameter can be one of the following values: 00939 * @arg @ref LL_DAC_CHANNEL_1 00940 * @arg @ref LL_DAC_CHANNEL_2 (1) 00941 * 00942 * (1) On this STM32 serie, parameter not available on all devices. 00943 * Refer to device datasheet for channels availability. 00944 * @retval Returned value can be one of the following values: 00945 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 00946 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 00947 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 00948 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 00949 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 00950 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 00951 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 00952 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 00953 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 00954 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 00955 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 00956 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 00957 */ 00958 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00959 { 00960 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00961 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00962 ); 00963 } 00964 00965 /** 00966 * @brief Set the output for the selected DAC channel. 00967 * @note This function set several features: 00968 * - mode normal or sample-and-hold 00969 * - buffer 00970 * - connection to GPIO or internal path. 00971 * These features can also be set individually using 00972 * dedicated functions: 00973 * - @ref LL_DAC_SetOutputBuffer() 00974 * - @ref LL_DAC_SetOutputMode() 00975 * - @ref LL_DAC_SetOutputConnection() 00976 * @note On this STM32 serie, output connection depends on output mode 00977 * (normal or sample and hold) and output buffer state. 00978 * - if output connection is set to internal path and output buffer 00979 * is enabled (whatever output mode): 00980 * output connection is also connected to GPIO pin 00981 * (both connections to GPIO pin and internal path). 00982 * - if output connection is set to GPIO pin, output buffer 00983 * is disabled, output mode set to sample and hold: 00984 * output connection is also connected to internal path 00985 * (both connections to GPIO pin and internal path). 00986 * @note Mode sample-and-hold requires an external capacitor 00987 * to be connected between DAC channel output and ground. 00988 * Capacitor value depends on load on DAC channel output and 00989 * sample-and-hold timings configured. 00990 * As indication, capacitor typical value is 100nF 00991 * (refer to device datasheet, parameter "CSH"). 00992 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n 00993 * CR MODE2 LL_DAC_ConfigOutput 00994 * @param DACx DAC instance 00995 * @param DAC_Channel This parameter can be one of the following values: 00996 * @arg @ref LL_DAC_CHANNEL_1 00997 * @arg @ref LL_DAC_CHANNEL_2 (1) 00998 * 00999 * (1) On this STM32 serie, parameter not available on all devices. 01000 * Refer to device datasheet for channels availability. 01001 * @param OutputMode This parameter can be one of the following values: 01002 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL 01003 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD 01004 * @param OutputBuffer This parameter can be one of the following values: 01005 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 01006 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 01007 * @param OutputConnection This parameter can be one of the following values: 01008 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO 01009 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL 01010 * @retval None 01011 */ 01012 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, 01013 uint32_t OutputBuffer, uint32_t OutputConnection) 01014 { 01015 MODIFY_REG(DACx->MCR, 01016 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01017 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01018 } 01019 01020 /** 01021 * @brief Set the output mode normal or sample-and-hold 01022 * for the selected DAC channel. 01023 * @note Mode sample-and-hold requires an external capacitor 01024 * to be connected between DAC channel output and ground. 01025 * Capacitor value depends on load on DAC channel output and 01026 * sample-and-hold timings configured. 01027 * As indication, capacitor typical value is 100nF 01028 * (refer to device datasheet, parameter "CSH"). 01029 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n 01030 * CR MODE2 LL_DAC_SetOutputMode 01031 * @param DACx DAC instance 01032 * @param DAC_Channel This parameter can be one of the following values: 01033 * @arg @ref LL_DAC_CHANNEL_1 01034 * @arg @ref LL_DAC_CHANNEL_2 (1) 01035 * 01036 * (1) On this STM32 serie, parameter not available on all devices. 01037 * Refer to device datasheet for channels availability. 01038 * @param OutputMode This parameter can be one of the following values: 01039 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL 01040 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD 01041 * @retval None 01042 */ 01043 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode) 01044 { 01045 MODIFY_REG(DACx->MCR, 01046 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01047 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01048 } 01049 01050 /** 01051 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel. 01052 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n 01053 * CR MODE2 LL_DAC_GetOutputMode 01054 * @param DACx DAC instance 01055 * @param DAC_Channel This parameter can be one of the following values: 01056 * @arg @ref LL_DAC_CHANNEL_1 01057 * @arg @ref LL_DAC_CHANNEL_2 (1) 01058 * 01059 * (1) On this STM32 serie, parameter not available on all devices. 01060 * Refer to device datasheet for channels availability. 01061 * @retval Returned value can be one of the following values: 01062 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL 01063 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD 01064 */ 01065 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01066 { 01067 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01068 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01069 ); 01070 } 01071 01072 /** 01073 * @brief Set the output buffer for the selected DAC channel. 01074 * @note On this STM32 serie, when buffer is enabled, its offset can be 01075 * trimmed: factory calibration default values can be 01076 * replaced by user trimming values, using function 01077 * @ref LL_DAC_SetTrimmingValue(). 01078 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n 01079 * CR MODE2 LL_DAC_SetOutputBuffer 01080 * @param DACx DAC instance 01081 * @param DAC_Channel This parameter can be one of the following values: 01082 * @arg @ref LL_DAC_CHANNEL_1 01083 * @arg @ref LL_DAC_CHANNEL_2 (1) 01084 * 01085 * (1) On this STM32 serie, parameter not available on all devices. 01086 * Refer to device datasheet for channels availability. 01087 * @param OutputBuffer This parameter can be one of the following values: 01088 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 01089 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 01090 * @retval None 01091 */ 01092 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) 01093 { 01094 MODIFY_REG(DACx->MCR, 01095 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01096 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01097 } 01098 01099 /** 01100 * @brief Get the output buffer state for the selected DAC channel. 01101 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n 01102 * CR MODE2 LL_DAC_GetOutputBuffer 01103 * @param DACx DAC instance 01104 * @param DAC_Channel This parameter can be one of the following values: 01105 * @arg @ref LL_DAC_CHANNEL_1 01106 * @arg @ref LL_DAC_CHANNEL_2 (1) 01107 * 01108 * (1) On this STM32 serie, parameter not available on all devices. 01109 * Refer to device datasheet for channels availability. 01110 * @retval Returned value can be one of the following values: 01111 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 01112 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 01113 */ 01114 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01115 { 01116 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01117 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01118 ); 01119 } 01120 01121 /** 01122 * @brief Set the output connection for the selected DAC channel. 01123 * @note On this STM32 serie, output connection depends on output mode (normal or 01124 * sample and hold) and output buffer state. 01125 * - if output connection is set to internal path and output buffer 01126 * is enabled (whatever output mode): 01127 * output connection is also connected to GPIO pin 01128 * (both connections to GPIO pin and internal path). 01129 * - if output connection is set to GPIO pin, output buffer 01130 * is disabled, output mode set to sample and hold: 01131 * output connection is also connected to internal path 01132 * (both connections to GPIO pin and internal path). 01133 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n 01134 * CR MODE2 LL_DAC_SetOutputConnection 01135 * @param DACx DAC instance 01136 * @param DAC_Channel This parameter can be one of the following values: 01137 * @arg @ref LL_DAC_CHANNEL_1 01138 * @arg @ref LL_DAC_CHANNEL_2 (1) 01139 * 01140 * (1) On this STM32 serie, parameter not available on all devices. 01141 * Refer to device datasheet for channels availability. 01142 * @param OutputConnection This parameter can be one of the following values: 01143 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO 01144 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL 01145 * @retval None 01146 */ 01147 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection) 01148 { 01149 MODIFY_REG(DACx->MCR, 01150 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01151 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01152 } 01153 01154 /** 01155 * @brief Get the output connection for the selected DAC channel. 01156 * @note On this STM32 serie, output connection depends on output mode (normal or 01157 * sample and hold) and output buffer state. 01158 * - if output connection is set to internal path and output buffer 01159 * is enabled (whatever output mode): 01160 * output connection is also connected to GPIO pin 01161 * (both connections to GPIO pin and internal path). 01162 * - if output connection is set to GPIO pin, output buffer 01163 * is disabled, output mode set to sample and hold: 01164 * output connection is also connected to internal path 01165 * (both connections to GPIO pin and internal path). 01166 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n 01167 * CR MODE2 LL_DAC_GetOutputConnection 01168 * @param DACx DAC instance 01169 * @param DAC_Channel This parameter can be one of the following values: 01170 * @arg @ref LL_DAC_CHANNEL_1 01171 * @arg @ref LL_DAC_CHANNEL_2 (1) 01172 * 01173 * (1) On this STM32 serie, parameter not available on all devices. 01174 * Refer to device datasheet for channels availability. 01175 * @retval Returned value can be one of the following values: 01176 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO 01177 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL 01178 */ 01179 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01180 { 01181 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01182 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01183 ); 01184 } 01185 01186 /** 01187 * @brief Set the sample-and-hold timing for the selected DAC channel: 01188 * sample time 01189 * @note Sample time must be set when DAC channel is disabled 01190 * or during DAC operation when DAC channel flag BWSTx is reset, 01191 * otherwise the setting is ignored. 01192 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()". 01193 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n 01194 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime 01195 * @param DACx DAC instance 01196 * @param DAC_Channel This parameter can be one of the following values: 01197 * @arg @ref LL_DAC_CHANNEL_1 01198 * @arg @ref LL_DAC_CHANNEL_2 (1) 01199 * 01200 * (1) On this STM32 serie, parameter not available on all devices. 01201 * Refer to device datasheet for channels availability. 01202 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF 01203 * @retval None 01204 */ 01205 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime) 01206 { 01207 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); 01208 01209 MODIFY_REG(*preg, 01210 DAC_SHSR1_TSAMPLE1, 01211 SampleTime); 01212 } 01213 01214 /** 01215 * @brief Get the sample-and-hold timing for the selected DAC channel: 01216 * sample time 01217 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n 01218 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime 01219 * @param DACx DAC instance 01220 * @param DAC_Channel This parameter can be one of the following values: 01221 * @arg @ref LL_DAC_CHANNEL_1 01222 * @arg @ref LL_DAC_CHANNEL_2 (1) 01223 * 01224 * (1) On this STM32 serie, parameter not available on all devices. 01225 * Refer to device datasheet for channels availability. 01226 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 01227 */ 01228 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01229 { 01230 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); 01231 01232 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1); 01233 } 01234 01235 /** 01236 * @brief Set the sample-and-hold timing for the selected DAC channel: 01237 * hold time 01238 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n 01239 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime 01240 * @param DACx DAC instance 01241 * @param DAC_Channel This parameter can be one of the following values: 01242 * @arg @ref LL_DAC_CHANNEL_1 01243 * @arg @ref LL_DAC_CHANNEL_2 (1) 01244 * 01245 * (1) On this STM32 serie, parameter not available on all devices. 01246 * Refer to device datasheet for channels availability. 01247 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF 01248 * @retval None 01249 */ 01250 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime) 01251 { 01252 MODIFY_REG(DACx->SHHR, 01253 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01254 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01255 } 01256 01257 /** 01258 * @brief Get the sample-and-hold timing for the selected DAC channel: 01259 * hold time 01260 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n 01261 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime 01262 * @param DACx DAC instance 01263 * @param DAC_Channel This parameter can be one of the following values: 01264 * @arg @ref LL_DAC_CHANNEL_1 01265 * @arg @ref LL_DAC_CHANNEL_2 (1) 01266 * 01267 * (1) On this STM32 serie, parameter not available on all devices. 01268 * Refer to device datasheet for channels availability. 01269 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 01270 */ 01271 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01272 { 01273 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01274 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01275 ); 01276 } 01277 01278 /** 01279 * @brief Set the sample-and-hold timing for the selected DAC channel: 01280 * refresh time 01281 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n 01282 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime 01283 * @param DACx DAC instance 01284 * @param DAC_Channel This parameter can be one of the following values: 01285 * @arg @ref LL_DAC_CHANNEL_1 01286 * @arg @ref LL_DAC_CHANNEL_2 (1) 01287 * 01288 * (1) On this STM32 serie, parameter not available on all devices. 01289 * Refer to device datasheet for channels availability. 01290 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF 01291 * @retval None 01292 */ 01293 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime) 01294 { 01295 MODIFY_REG(DACx->SHRR, 01296 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01297 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01298 } 01299 01300 /** 01301 * @brief Get the sample-and-hold timing for the selected DAC channel: 01302 * refresh time 01303 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n 01304 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime 01305 * @param DACx DAC instance 01306 * @param DAC_Channel This parameter can be one of the following values: 01307 * @arg @ref LL_DAC_CHANNEL_1 01308 * @arg @ref LL_DAC_CHANNEL_2 (1) 01309 * 01310 * (1) On this STM32 serie, parameter not available on all devices. 01311 * Refer to device datasheet for channels availability. 01312 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 01313 */ 01314 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01315 { 01316 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01317 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01318 ); 01319 } 01320 01321 /** 01322 * @} 01323 */ 01324 01325 /** @defgroup DAC_LL_EF_DMA_Management DMA Management 01326 * @{ 01327 */ 01328 01329 /** 01330 * @brief Enable DAC DMA transfer request of the selected channel. 01331 * @note To configure DMA source address (peripheral address), 01332 * use function @ref LL_DAC_DMA_GetRegAddr(). 01333 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n 01334 * CR DMAEN2 LL_DAC_EnableDMAReq 01335 * @param DACx DAC instance 01336 * @param DAC_Channel This parameter can be one of the following values: 01337 * @arg @ref LL_DAC_CHANNEL_1 01338 * @arg @ref LL_DAC_CHANNEL_2 (1) 01339 * 01340 * (1) On this STM32 serie, parameter not available on all devices. 01341 * Refer to device datasheet for channels availability. 01342 * @retval None 01343 */ 01344 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01345 { 01346 SET_BIT(DACx->CR, 01347 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01348 } 01349 01350 /** 01351 * @brief Disable DAC DMA transfer request of the selected channel. 01352 * @note To configure DMA source address (peripheral address), 01353 * use function @ref LL_DAC_DMA_GetRegAddr(). 01354 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n 01355 * CR DMAEN2 LL_DAC_DisableDMAReq 01356 * @param DACx DAC instance 01357 * @param DAC_Channel This parameter can be one of the following values: 01358 * @arg @ref LL_DAC_CHANNEL_1 01359 * @arg @ref LL_DAC_CHANNEL_2 (1) 01360 * 01361 * (1) On this STM32 serie, parameter not available on all devices. 01362 * Refer to device datasheet for channels availability. 01363 * @retval None 01364 */ 01365 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01366 { 01367 CLEAR_BIT(DACx->CR, 01368 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01369 } 01370 01371 /** 01372 * @brief Get DAC DMA transfer request state of the selected channel. 01373 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) 01374 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n 01375 * CR DMAEN2 LL_DAC_IsDMAReqEnabled 01376 * @param DACx DAC instance 01377 * @param DAC_Channel This parameter can be one of the following values: 01378 * @arg @ref LL_DAC_CHANNEL_1 01379 * @arg @ref LL_DAC_CHANNEL_2 (1) 01380 * 01381 * (1) On this STM32 serie, parameter not available on all devices. 01382 * Refer to device datasheet for channels availability. 01383 * @retval State of bit (1 or 0). 01384 */ 01385 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01386 { 01387 return ((READ_BIT(DACx->CR, 01388 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01389 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 01390 } 01391 01392 /** 01393 * @brief Function to help to configure DMA transfer to DAC: retrieve the 01394 * DAC register address from DAC instance and a list of DAC registers 01395 * intended to be used (most commonly) with DMA transfer. 01396 * @note These DAC registers are data holding registers: 01397 * when DAC conversion is requested, DAC generates a DMA transfer 01398 * request to have data available in DAC data holding registers. 01399 * @note This macro is intended to be used with LL DMA driver, refer to 01400 * function "LL_DMA_ConfigAddresses()". 01401 * Example: 01402 * LL_DMA_ConfigAddresses(DMA1, 01403 * LL_DMA_CHANNEL_1, 01404 * (uint32_t)&< array or variable >, 01405 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), 01406 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); 01407 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 01408 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 01409 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 01410 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 01411 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 01412 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr 01413 * @param DACx DAC instance 01414 * @param DAC_Channel This parameter can be one of the following values: 01415 * @arg @ref LL_DAC_CHANNEL_1 01416 * @arg @ref LL_DAC_CHANNEL_2 (1) 01417 * 01418 * (1) On this STM32 serie, parameter not available on all devices. 01419 * Refer to device datasheet for channels availability. 01420 * @param Register This parameter can be one of the following values: 01421 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED 01422 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED 01423 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED 01424 * @retval DAC register address 01425 */ 01426 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) 01427 { 01428 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ 01429 /* DAC channel selected. */ 01430 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, 01431 ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); 01432 } 01433 /** 01434 * @} 01435 */ 01436 01437 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels 01438 * @{ 01439 */ 01440 01441 /** 01442 * @brief Enable DAC selected channel. 01443 * @rmtoll CR EN1 LL_DAC_Enable\n 01444 * CR EN2 LL_DAC_Enable 01445 * @note After enable from off state, DAC channel requires a delay 01446 * for output voltage to reach accuracy +/- 1 LSB. 01447 * Refer to device datasheet, parameter "tWAKEUP". 01448 * @param DACx DAC instance 01449 * @param DAC_Channel This parameter can be one of the following values: 01450 * @arg @ref LL_DAC_CHANNEL_1 01451 * @arg @ref LL_DAC_CHANNEL_2 (1) 01452 * 01453 * (1) On this STM32 serie, parameter not available on all devices. 01454 * Refer to device datasheet for channels availability. 01455 * @retval None 01456 */ 01457 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01458 { 01459 SET_BIT(DACx->CR, 01460 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01461 } 01462 01463 /** 01464 * @brief Disable DAC selected channel. 01465 * @rmtoll CR EN1 LL_DAC_Disable\n 01466 * CR EN2 LL_DAC_Disable 01467 * @param DACx DAC instance 01468 * @param DAC_Channel This parameter can be one of the following values: 01469 * @arg @ref LL_DAC_CHANNEL_1 01470 * @arg @ref LL_DAC_CHANNEL_2 (1) 01471 * 01472 * (1) On this STM32 serie, parameter not available on all devices. 01473 * Refer to device datasheet for channels availability. 01474 * @retval None 01475 */ 01476 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01477 { 01478 CLEAR_BIT(DACx->CR, 01479 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01480 } 01481 01482 /** 01483 * @brief Get DAC enable state of the selected channel. 01484 * (0: DAC channel is disabled, 1: DAC channel is enabled) 01485 * @rmtoll CR EN1 LL_DAC_IsEnabled\n 01486 * CR EN2 LL_DAC_IsEnabled 01487 * @param DACx DAC instance 01488 * @param DAC_Channel This parameter can be one of the following values: 01489 * @arg @ref LL_DAC_CHANNEL_1 01490 * @arg @ref LL_DAC_CHANNEL_2 (1) 01491 * 01492 * (1) On this STM32 serie, parameter not available on all devices. 01493 * Refer to device datasheet for channels availability. 01494 * @retval State of bit (1 or 0). 01495 */ 01496 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01497 { 01498 return ((READ_BIT(DACx->CR, 01499 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01500 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 01501 } 01502 01503 /** 01504 * @brief Enable DAC trigger of the selected channel. 01505 * @note - If DAC trigger is disabled, DAC conversion is performed 01506 * automatically once the data holding register is updated, 01507 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 01508 * @ref LL_DAC_ConvertData12RightAligned(), ... 01509 * - If DAC trigger is enabled, DAC conversion is performed 01510 * only when a hardware of software trigger event is occurring. 01511 * Select trigger source using 01512 * function @ref LL_DAC_SetTriggerSource(). 01513 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n 01514 * CR TEN2 LL_DAC_EnableTrigger 01515 * @param DACx DAC instance 01516 * @param DAC_Channel This parameter can be one of the following values: 01517 * @arg @ref LL_DAC_CHANNEL_1 01518 * @arg @ref LL_DAC_CHANNEL_2 (1) 01519 * 01520 * (1) On this STM32 serie, parameter not available on all devices. 01521 * Refer to device datasheet for channels availability. 01522 * @retval None 01523 */ 01524 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01525 { 01526 SET_BIT(DACx->CR, 01527 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01528 } 01529 01530 /** 01531 * @brief Disable DAC trigger of the selected channel. 01532 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n 01533 * CR TEN2 LL_DAC_DisableTrigger 01534 * @param DACx DAC instance 01535 * @param DAC_Channel This parameter can be one of the following values: 01536 * @arg @ref LL_DAC_CHANNEL_1 01537 * @arg @ref LL_DAC_CHANNEL_2 (1) 01538 * 01539 * (1) On this STM32 serie, parameter not available on all devices. 01540 * Refer to device datasheet for channels availability. 01541 * @retval None 01542 */ 01543 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01544 { 01545 CLEAR_BIT(DACx->CR, 01546 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01547 } 01548 01549 /** 01550 * @brief Get DAC trigger state of the selected channel. 01551 * (0: DAC trigger is disabled, 1: DAC trigger is enabled) 01552 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n 01553 * CR TEN2 LL_DAC_IsTriggerEnabled 01554 * @param DACx DAC instance 01555 * @param DAC_Channel This parameter can be one of the following values: 01556 * @arg @ref LL_DAC_CHANNEL_1 01557 * @arg @ref LL_DAC_CHANNEL_2 (1) 01558 * 01559 * (1) On this STM32 serie, parameter not available on all devices. 01560 * Refer to device datasheet for channels availability. 01561 * @retval State of bit (1 or 0). 01562 */ 01563 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01564 { 01565 return ((READ_BIT(DACx->CR, 01566 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01567 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 01568 } 01569 01570 /** 01571 * @brief Trig DAC conversion by software for the selected DAC channel. 01572 * @note Preliminarily, DAC trigger must be set to software trigger 01573 * using function 01574 * @ref LL_DAC_Init() 01575 * @ref LL_DAC_SetTriggerSource() 01576 * with parameter "LL_DAC_TRIGGER_SOFTWARE". 01577 * and DAC trigger must be enabled using 01578 * function @ref LL_DAC_EnableTrigger(). 01579 * @note For devices featuring DAC with 2 channels: this function 01580 * can perform a SW start of both DAC channels simultaneously. 01581 * Two channels can be selected as parameter. 01582 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) 01583 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n 01584 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion 01585 * @param DACx DAC instance 01586 * @param DAC_Channel This parameter can a combination of the following values: 01587 * @arg @ref LL_DAC_CHANNEL_1 01588 * @arg @ref LL_DAC_CHANNEL_2 (1) 01589 * 01590 * (1) On this STM32 serie, parameter not available on all devices. 01591 * Refer to device datasheet for channels availability. 01592 * @retval None 01593 */ 01594 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01595 { 01596 SET_BIT(DACx->SWTRIGR, 01597 (DAC_Channel & DAC_SWTR_CHX_MASK)); 01598 } 01599 01600 /** 01601 * @brief Set the data to be loaded in the data holding register 01602 * in format 12 bits left alignment (LSB aligned on bit 0), 01603 * for the selected DAC channel. 01604 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n 01605 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned 01606 * @param DACx DAC instance 01607 * @param DAC_Channel This parameter can be one of the following values: 01608 * @arg @ref LL_DAC_CHANNEL_1 01609 * @arg @ref LL_DAC_CHANNEL_2 (1) 01610 * 01611 * (1) On this STM32 serie, parameter not available on all devices. 01612 * Refer to device datasheet for channels availability. 01613 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 01614 * @retval None 01615 */ 01616 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01617 { 01618 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 01619 01620 MODIFY_REG(*preg, 01621 DAC_DHR12R1_DACC1DHR, 01622 Data); 01623 } 01624 01625 /** 01626 * @brief Set the data to be loaded in the data holding register 01627 * in format 12 bits left alignment (MSB aligned on bit 15), 01628 * for the selected DAC channel. 01629 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n 01630 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned 01631 * @param DACx DAC instance 01632 * @param DAC_Channel This parameter can be one of the following values: 01633 * @arg @ref LL_DAC_CHANNEL_1 01634 * @arg @ref LL_DAC_CHANNEL_2 (1) 01635 * 01636 * (1) On this STM32 serie, parameter not available on all devices. 01637 * Refer to device datasheet for channels availability. 01638 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 01639 * @retval None 01640 */ 01641 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01642 { 01643 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 01644 01645 MODIFY_REG(*preg, 01646 DAC_DHR12L1_DACC1DHR, 01647 Data); 01648 } 01649 01650 /** 01651 * @brief Set the data to be loaded in the data holding register 01652 * in format 8 bits left alignment (LSB aligned on bit 0), 01653 * for the selected DAC channel. 01654 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n 01655 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned 01656 * @param DACx DAC instance 01657 * @param DAC_Channel This parameter can be one of the following values: 01658 * @arg @ref LL_DAC_CHANNEL_1 01659 * @arg @ref LL_DAC_CHANNEL_2 (1) 01660 * 01661 * (1) On this STM32 serie, parameter not available on all devices. 01662 * Refer to device datasheet for channels availability. 01663 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF 01664 * @retval None 01665 */ 01666 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01667 { 01668 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 01669 01670 MODIFY_REG(*preg, 01671 DAC_DHR8R1_DACC1DHR, 01672 Data); 01673 } 01674 01675 #if defined(DAC_CHANNEL2_SUPPORT) 01676 /** 01677 * @brief Set the data to be loaded in the data holding register 01678 * in format 12 bits left alignment (LSB aligned on bit 0), 01679 * for both DAC channels. 01680 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n 01681 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned 01682 * @param DACx DAC instance 01683 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 01684 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 01685 * @retval None 01686 */ 01687 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 01688 uint32_t DataChannel2) 01689 { 01690 MODIFY_REG(DACx->DHR12RD, 01691 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), 01692 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 01693 } 01694 01695 /** 01696 * @brief Set the data to be loaded in the data holding register 01697 * in format 12 bits left alignment (MSB aligned on bit 15), 01698 * for both DAC channels. 01699 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n 01700 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned 01701 * @param DACx DAC instance 01702 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 01703 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 01704 * @retval None 01705 */ 01706 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) 01707 { 01708 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ 01709 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ 01710 /* the 4 LSB must be taken into account for the shift value. */ 01711 MODIFY_REG(DACx->DHR12LD, 01712 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), 01713 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); 01714 } 01715 01716 /** 01717 * @brief Set the data to be loaded in the data holding register 01718 * in format 8 bits left alignment (LSB aligned on bit 0), 01719 * for both DAC channels. 01720 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n 01721 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned 01722 * @param DACx DAC instance 01723 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF 01724 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF 01725 * @retval None 01726 */ 01727 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) 01728 { 01729 MODIFY_REG(DACx->DHR8RD, 01730 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), 01731 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 01732 } 01733 01734 #endif /* DAC_CHANNEL2_SUPPORT */ 01735 /** 01736 * @brief Retrieve output data currently generated for the selected DAC channel. 01737 * @note Whatever alignment and resolution settings 01738 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 01739 * @ref LL_DAC_ConvertData12RightAligned(), ...), 01740 * output data format is 12 bits right aligned (LSB aligned on bit 0). 01741 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n 01742 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData 01743 * @param DACx DAC instance 01744 * @param DAC_Channel This parameter can be one of the following values: 01745 * @arg @ref LL_DAC_CHANNEL_1 01746 * @arg @ref LL_DAC_CHANNEL_2 (1) 01747 * 01748 * (1) On this STM32 serie, parameter not available on all devices. 01749 * Refer to device datasheet for channels availability. 01750 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01751 */ 01752 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01753 { 01754 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); 01755 01756 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); 01757 } 01758 01759 /** 01760 * @} 01761 */ 01762 01763 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management 01764 * @{ 01765 */ 01766 /** 01767 * @brief Get DAC calibration offset flag for DAC channel 1 01768 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1 01769 * @param DACx DAC instance 01770 * @retval State of bit (1 or 0). 01771 */ 01772 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) 01773 { 01774 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL); 01775 } 01776 01777 #if defined(DAC_CHANNEL2_SUPPORT) 01778 /** 01779 * @brief Get DAC calibration offset flag for DAC channel 2 01780 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2 01781 * @param DACx DAC instance 01782 * @retval State of bit (1 or 0). 01783 */ 01784 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) 01785 { 01786 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL); 01787 } 01788 01789 #endif /* DAC_CHANNEL2_SUPPORT */ 01790 /** 01791 * @brief Get DAC busy writing sample time flag for DAC channel 1 01792 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1 01793 * @param DACx DAC instance 01794 * @retval State of bit (1 or 0). 01795 */ 01796 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) 01797 { 01798 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); 01799 } 01800 01801 #if defined(DAC_CHANNEL2_SUPPORT) 01802 /** 01803 * @brief Get DAC busy writing sample time flag for DAC channel 2 01804 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2 01805 * @param DACx DAC instance 01806 * @retval State of bit (1 or 0). 01807 */ 01808 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) 01809 { 01810 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL); 01811 } 01812 01813 #endif /* DAC_CHANNEL2_SUPPORT */ 01814 /** 01815 * @brief Get DAC underrun flag for DAC channel 1 01816 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 01817 * @param DACx DAC instance 01818 * @retval State of bit (1 or 0). 01819 */ 01820 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) 01821 { 01822 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); 01823 } 01824 01825 #if defined(DAC_CHANNEL2_SUPPORT) 01826 /** 01827 * @brief Get DAC underrun flag for DAC channel 2 01828 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 01829 * @param DACx DAC instance 01830 * @retval State of bit (1 or 0). 01831 */ 01832 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) 01833 { 01834 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); 01835 } 01836 #endif /* DAC_CHANNEL2_SUPPORT */ 01837 01838 /** 01839 * @brief Clear DAC underrun flag for DAC channel 1 01840 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 01841 * @param DACx DAC instance 01842 * @retval None 01843 */ 01844 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) 01845 { 01846 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); 01847 } 01848 01849 #if defined(DAC_CHANNEL2_SUPPORT) 01850 /** 01851 * @brief Clear DAC underrun flag for DAC channel 2 01852 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 01853 * @param DACx DAC instance 01854 * @retval None 01855 */ 01856 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) 01857 { 01858 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); 01859 } 01860 #endif /* DAC_CHANNEL2_SUPPORT */ 01861 01862 /** 01863 * @} 01864 */ 01865 01866 /** @defgroup DAC_LL_EF_IT_Management IT management 01867 * @{ 01868 */ 01869 01870 /** 01871 * @brief Enable DMA underrun interrupt for DAC channel 1 01872 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 01873 * @param DACx DAC instance 01874 * @retval None 01875 */ 01876 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) 01877 { 01878 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 01879 } 01880 01881 #if defined(DAC_CHANNEL2_SUPPORT) 01882 /** 01883 * @brief Enable DMA underrun interrupt for DAC channel 2 01884 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 01885 * @param DACx DAC instance 01886 * @retval None 01887 */ 01888 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) 01889 { 01890 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 01891 } 01892 #endif /* DAC_CHANNEL2_SUPPORT */ 01893 01894 /** 01895 * @brief Disable DMA underrun interrupt for DAC channel 1 01896 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 01897 * @param DACx DAC instance 01898 * @retval None 01899 */ 01900 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) 01901 { 01902 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 01903 } 01904 01905 #if defined(DAC_CHANNEL2_SUPPORT) 01906 /** 01907 * @brief Disable DMA underrun interrupt for DAC channel 2 01908 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 01909 * @param DACx DAC instance 01910 * @retval None 01911 */ 01912 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) 01913 { 01914 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 01915 } 01916 #endif /* DAC_CHANNEL2_SUPPORT */ 01917 01918 /** 01919 * @brief Get DMA underrun interrupt for DAC channel 1 01920 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 01921 * @param DACx DAC instance 01922 * @retval State of bit (1 or 0). 01923 */ 01924 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) 01925 { 01926 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); 01927 } 01928 01929 #if defined(DAC_CHANNEL2_SUPPORT) 01930 /** 01931 * @brief Get DMA underrun interrupt for DAC channel 2 01932 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 01933 * @param DACx DAC instance 01934 * @retval State of bit (1 or 0). 01935 */ 01936 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) 01937 { 01938 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); 01939 } 01940 #endif /* DAC_CHANNEL2_SUPPORT */ 01941 01942 /** 01943 * @} 01944 */ 01945 01946 #if defined(USE_FULL_LL_DRIVER) 01947 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions 01948 * @{ 01949 */ 01950 01951 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); 01952 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); 01953 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); 01954 01955 /** 01956 * @} 01957 */ 01958 #endif /* USE_FULL_LL_DRIVER */ 01959 01960 /** 01961 * @} 01962 */ 01963 01964 /** 01965 * @} 01966 */ 01967 01968 #endif /* DAC1 */ 01969 01970 /** 01971 * @} 01972 */ 01973 01974 #ifdef __cplusplus 01975 } 01976 #endif 01977 01978 #endif /* STM32L4xx_LL_DAC_H */ 01979
1.7.6.1