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STM32L443xx HAL User Manual
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Defines | |
| #define | DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ |
| #define | DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ |
| #define | DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) |
| #define | DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ |
| #define | DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ |
| #define | DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) |
| #define | DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ |
| #define | DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
| #define | DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
| #define | DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ |
| #define | DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
| #define | DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
| #define | DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U |
| #define | DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U |
| #define | DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U |
| #define | DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) |
| #define | DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ |
| #define | DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */ |
| #define | DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) |
| #define | DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */ |
| #define | DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */ |
| #define | DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) |
| #define | DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ |
| #define | DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */ |
| #define | DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */ |
| #define | DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ |
| #define | DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
| #define | DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
| #define | DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */ |
| #define | DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */ |
| #define | DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos |
| #define | DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos |
| #define | DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos |
| #define | DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ |
| #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ |
Definition at line 55 of file stm32l4xx_ll_dac.h.
| #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ |
Definition at line 56 of file stm32l4xx_ll_dac.h.
Definition at line 57 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_ConfigOutput(), LL_DAC_Disable(), LL_DAC_DisableDMAReq(), LL_DAC_DisableTrigger(), LL_DAC_Enable(), LL_DAC_EnableDMAReq(), LL_DAC_EnableTrigger(), LL_DAC_GetMode(), LL_DAC_GetOutputBuffer(), LL_DAC_GetOutputConnection(), LL_DAC_GetOutputMode(), LL_DAC_GetSampleAndHoldHoldTime(), LL_DAC_GetSampleAndHoldRefreshTime(), LL_DAC_GetTriggerSource(), LL_DAC_GetTrimmingValue(), LL_DAC_GetWaveAutoGeneration(), LL_DAC_GetWaveNoiseLFSR(), LL_DAC_GetWaveTriangleAmplitude(), LL_DAC_Init(), LL_DAC_IsDMAReqEnabled(), LL_DAC_IsEnabled(), LL_DAC_IsTriggerEnabled(), LL_DAC_SetMode(), LL_DAC_SetOutputBuffer(), LL_DAC_SetOutputConnection(), LL_DAC_SetOutputMode(), LL_DAC_SetSampleAndHoldHoldTime(), LL_DAC_SetSampleAndHoldRefreshTime(), LL_DAC_SetTriggerSource(), LL_DAC_SetTrimmingValue(), LL_DAC_SetWaveAutoGeneration(), LL_DAC_SetWaveNoiseLFSR(), and LL_DAC_SetWaveTriangleAmplitude().
| #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos |
Definition at line 109 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_ConvertDualData12LeftAligned().
| #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos |
Definition at line 108 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_ConvertDualData12RightAligned().
| #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos |
Definition at line 110 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_ConvertDualData8RightAligned().
| #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ |
Definition at line 114 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
Definition at line 68 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
Definition at line 72 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
Definition at line 101 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_ConvertData12LeftAligned().
| #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U |
Definition at line 76 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ |
Definition at line 67 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ |
Definition at line 71 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ |
Definition at line 100 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_ConvertData12RightAligned().
| #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U |
Definition at line 75 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
Definition at line 69 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
Definition at line 73 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
Definition at line 102 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_ConvertData8RightAligned().
| #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U |
Definition at line 77 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ |
Definition at line 96 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_ConvertData12LeftAligned(), LL_DAC_ConvertData12RightAligned(), LL_DAC_ConvertData8RightAligned(), and LL_DAC_DMA_GetRegAddr().
| #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) |
Definition at line 78 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ |
Definition at line 80 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */ |
Definition at line 82 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */ |
Definition at line 103 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_RetrieveOutputData().
Definition at line 83 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */ |
Definition at line 97 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_RetrieveOutputData().
| #define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */ |
Definition at line 88 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */ |
Definition at line 90 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */ |
Definition at line 104 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_GetSampleAndHoldSampleTime(), and LL_DAC_SetSampleAndHoldSampleTime().
Definition at line 91 of file stm32l4xx_ll_dac.h.
| #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */ |
Definition at line 98 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_GetSampleAndHoldSampleTime(), and LL_DAC_SetSampleAndHoldSampleTime().
| #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ |
Definition at line 59 of file stm32l4xx_ll_dac.h.
| #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ |
Definition at line 61 of file stm32l4xx_ll_dac.h.
| #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) |
Definition at line 62 of file stm32l4xx_ll_dac.h.
Referenced by LL_DAC_TrigSWConversion().
1.7.6.1