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STM32F103xB HAL User Manual
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Defines | |
| #define | LL_ADC_MULTI_INDEPENDENT 0x00000000U |
| #define | LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ) |
| #define | LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) |
| #define | LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 ) |
| #define | LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0) |
| #define | LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0) |
| #define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0) |
| #define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 ) |
| #define | LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) |
| #define | LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 ) |
| #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0) |
ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start)
Definition at line 855 of file stm32f1xx_ll_adc.h.
| #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0) |
ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices))
Definition at line 854 of file stm32f1xx_ll_adc.h.
| #define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) |
ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices))
Definition at line 852 of file stm32f1xx_ll_adc.h.
| #define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 ) |
ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices))
Definition at line 853 of file stm32f1xx_ll_adc.h.
| #define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) |
ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous
Definition at line 858 of file stm32f1xx_ll_adc.h.
| #define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 ) |
ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous
Definition at line 859 of file stm32f1xx_ll_adc.h.
| #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 ) |
ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger
Definition at line 857 of file stm32f1xx_ll_adc.h.
| #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0) |
ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous
Definition at line 856 of file stm32f1xx_ll_adc.h.
| #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ) |
ADC dual mode enabled: group regular simultaneous
Definition at line 851 of file stm32f1xx_ll_adc.h.
| #define LL_ADC_MULTI_INDEPENDENT 0x00000000U |
ADC dual mode disabled (ADC independent mode)
Definition at line 850 of file stm32f1xx_ll_adc.h.
Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().
1.7.6.1