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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_ll_adc.h 00004 * @author MCD Application Team 00005 * @brief Header file of ADC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F1xx_LL_ADC_H 00022 #define __STM32F1xx_LL_ADC_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f1xx.h" 00030 00031 /** @addtogroup STM32F1xx_LL_Driver 00032 * @{ 00033 */ 00034 00035 #if defined (ADC1) || defined (ADC2) || defined (ADC3) 00036 00037 /** @defgroup ADC_LL ADC 00038 * @{ 00039 */ 00040 00041 /* Private types -------------------------------------------------------------*/ 00042 /* Private variables ---------------------------------------------------------*/ 00043 00044 /* Private constants ---------------------------------------------------------*/ 00045 /** @defgroup ADC_LL_Private_Constants ADC Private Constants 00046 * @{ 00047 */ 00048 00049 /* Internal mask for ADC group regular sequencer: */ 00050 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ 00051 /* - sequencer register offset */ 00052 /* - sequencer rank bits position into the selected register */ 00053 00054 /* Internal register offset for ADC group regular sequencer configuration */ 00055 /* (offset placed into a spare area of literal definition) */ 00056 #define ADC_SQR1_REGOFFSET 0x00000000U 00057 #define ADC_SQR2_REGOFFSET 0x00000100U 00058 #define ADC_SQR3_REGOFFSET 0x00000200U 00059 #define ADC_SQR4_REGOFFSET 0x00000300U 00060 00061 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) 00062 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 00063 00064 /* Definition of ADC group regular sequencer bits information to be inserted */ 00065 /* into ADC group regular sequencer ranks literals definition. */ 00066 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ 00067 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ 00068 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ 00069 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ 00070 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ 00071 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ 00072 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ 00073 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ 00074 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ 00075 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ 00076 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ 00077 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ 00078 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ 00079 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ 00080 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ 00081 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ 00082 00083 /* Internal mask for ADC group injected sequencer: */ 00084 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ 00085 /* - data register offset */ 00086 /* - offset register offset */ 00087 /* - sequencer rank bits position into the selected register */ 00088 00089 /* Internal register offset for ADC group injected data register */ 00090 /* (offset placed into a spare area of literal definition) */ 00091 #define ADC_JDR1_REGOFFSET 0x00000000U 00092 #define ADC_JDR2_REGOFFSET 0x00000100U 00093 #define ADC_JDR3_REGOFFSET 0x00000200U 00094 #define ADC_JDR4_REGOFFSET 0x00000300U 00095 00096 /* Internal register offset for ADC group injected offset configuration */ 00097 /* (offset placed into a spare area of literal definition) */ 00098 #define ADC_JOFR1_REGOFFSET 0x00000000U 00099 #define ADC_JOFR2_REGOFFSET 0x00001000U 00100 #define ADC_JOFR3_REGOFFSET 0x00002000U 00101 #define ADC_JOFR4_REGOFFSET 0x00003000U 00102 00103 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) 00104 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) 00105 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 00106 00107 /* Internal mask for ADC channel: */ 00108 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ 00109 /* - channel identifier defined by number */ 00110 /* - channel differentiation between external channels (connected to */ 00111 /* GPIO pins) and internal channels (connected to internal paths) */ 00112 /* - channel sampling time defined by SMPRx register offset */ 00113 /* and SMPx bits positions into SMPRx register */ 00114 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) 00115 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ 00116 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) 00117 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ 00118 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ 00119 00120 /* Channel differentiation between external and internal channels */ 00121 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */ 00122 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ 00123 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) 00124 00125 /* Internal register offset for ADC channel sampling time configuration */ 00126 /* (offset placed into a spare area of literal definition) */ 00127 #define ADC_SMPR1_REGOFFSET 0x00000000U 00128 #define ADC_SMPR2_REGOFFSET 0x02000000U 00129 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) 00130 00131 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U 00132 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ 00133 00134 /* Definition of channels ID number information to be inserted into */ 00135 /* channels literals definition. */ 00136 #define ADC_CHANNEL_0_NUMBER 0x00000000U 00137 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) 00138 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) 00139 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 00140 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) 00141 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) 00142 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) 00143 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 00144 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) 00145 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) 00146 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) 00147 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 00148 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) 00149 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) 00150 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) 00151 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 00152 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) 00153 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) 00154 00155 /* Definition of channels sampling time information to be inserted into */ 00156 /* channels literals definition. */ 00157 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ 00158 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ 00159 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ 00160 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ 00161 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ 00162 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ 00163 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ 00164 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ 00165 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ 00166 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ 00167 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ 00168 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ 00169 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ 00170 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ 00171 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ 00172 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ 00173 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ 00174 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ 00175 00176 /* Internal mask for ADC analog watchdog: */ 00177 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ 00178 /* (concatenation of multiple bits used in different analog watchdogs, */ 00179 /* (feature of several watchdogs not available on all STM32 families)). */ 00180 /* - analog watchdog 1: monitored channel defined by number, */ 00181 /* selection of ADC group (ADC groups regular and-or injected). */ 00182 00183 /* Internal register offset for ADC analog watchdog channel configuration */ 00184 #define ADC_AWD_CR1_REGOFFSET 0x00000000U 00185 00186 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) 00187 00188 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) 00189 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) 00190 00191 /* Internal register offset for ADC analog watchdog threshold configuration */ 00192 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U 00193 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U 00194 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) 00195 00196 /* ADC registers bits positions */ 00197 #define ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */ 00198 00199 /** 00200 * @} 00201 */ 00202 00203 00204 /* Private macros ------------------------------------------------------------*/ 00205 /** @defgroup ADC_LL_Private_Macros ADC Private Macros 00206 * @{ 00207 */ 00208 00209 /** 00210 * @brief Driver macro reserved for internal use: isolate bits with the 00211 * selected mask and shift them to the register LSB 00212 * (shift mask on register position bit 0). 00213 * @param __BITS__ Bits in register 32 bits 00214 * @param __MASK__ Mask in register 32 bits 00215 * @retval Bits in register 32 bits 00216 */ 00217 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ 00218 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) 00219 00220 /** 00221 * @brief Driver macro reserved for internal use: set a pointer to 00222 * a register from a register basis from which an offset 00223 * is applied. 00224 * @param __REG__ Register basis from which the offset is applied. 00225 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). 00226 * @retval Pointer to register address 00227 */ 00228 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 00229 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) 00230 00231 /** 00232 * @} 00233 */ 00234 00235 00236 /* Exported types ------------------------------------------------------------*/ 00237 #if defined(USE_FULL_LL_DRIVER) 00238 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure 00239 * @{ 00240 */ 00241 00242 /** 00243 * @brief Structure definition of some features of ADC common parameters 00244 * and multimode 00245 * (all ADC instances belonging to the same ADC common instance). 00246 * @note The setting of these parameters by function @ref LL_ADC_CommonInit() 00247 * is conditioned to ADC instances state (all ADC instances 00248 * sharing the same ADC common instance): 00249 * All ADC instances sharing the same ADC common instance must be 00250 * disabled. 00251 */ 00252 typedef struct 00253 { 00254 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). 00255 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE 00256 00257 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ 00258 } LL_ADC_CommonInitTypeDef; 00259 /** 00260 * @brief Structure definition of some features of ADC instance. 00261 * @note These parameters have an impact on ADC scope: ADC instance. 00262 * Affects both group regular and group injected (availability 00263 * of ADC group injected depends on STM32 families). 00264 * Refer to corresponding unitary functions into 00265 * @ref ADC_LL_EF_Configuration_ADC_Instance . 00266 * @note The setting of these parameters by function @ref LL_ADC_Init() 00267 * is conditioned to ADC state: 00268 * ADC instance must be disabled. 00269 * This condition is applied to all ADC features, for efficiency 00270 * and compatibility over all STM32 families. However, the different 00271 * features can be set under different ADC state conditions 00272 * (setting possible with ADC enabled without conversion on going, 00273 * ADC enabled with conversion on going, ...) 00274 * Each feature can be updated afterwards with a unitary function 00275 * and potentially with ADC in a different state than disabled, 00276 * refer to description of each function for setting 00277 * conditioned to ADC state. 00278 */ 00279 typedef struct 00280 { 00281 uint32_t DataAlignment; /*!< Set ADC conversion data alignment. 00282 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN 00283 00284 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ 00285 00286 uint32_t SequencersScanMode; /*!< Set ADC scan selection. 00287 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION 00288 00289 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ 00290 00291 } LL_ADC_InitTypeDef; 00292 00293 /** 00294 * @brief Structure definition of some features of ADC group regular. 00295 * @note These parameters have an impact on ADC scope: ADC group regular. 00296 * Refer to corresponding unitary functions into 00297 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00298 * (functions with prefix "REG"). 00299 * @note The setting of these parameters by function @ref LL_ADC_REG_Init() 00300 * is conditioned to ADC state: 00301 * ADC instance must be disabled. 00302 * This condition is applied to all ADC features, for efficiency 00303 * and compatibility over all STM32 families. However, the different 00304 * features can be set under different ADC state conditions 00305 * (setting possible with ADC enabled without conversion on going, 00306 * ADC enabled with conversion on going, ...) 00307 * Each feature can be updated afterwards with a unitary function 00308 * and potentially with ADC in a different state than disabled, 00309 * refer to description of each function for setting 00310 * conditioned to ADC state. 00311 */ 00312 typedef struct 00313 { 00314 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 00315 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE 00316 @note On this STM32 serie, external trigger is set with trigger polarity: rising edge 00317 (only trigger polarity available on this STM32 serie). 00318 00319 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ 00320 00321 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. 00322 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH 00323 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). 00324 00325 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ 00326 00327 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 00328 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE 00329 @note This parameter has an effect only if group regular sequencer is enabled 00330 (scan length of 2 ranks or more). 00331 00332 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ 00333 00334 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). 00335 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE 00336 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. 00337 00338 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ 00339 00340 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. 00341 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER 00342 00343 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ 00344 00345 } LL_ADC_REG_InitTypeDef; 00346 00347 /** 00348 * @brief Structure definition of some features of ADC group injected. 00349 * @note These parameters have an impact on ADC scope: ADC group injected. 00350 * Refer to corresponding unitary functions into 00351 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00352 * (functions with prefix "INJ"). 00353 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() 00354 * is conditioned to ADC state: 00355 * ADC instance must be disabled. 00356 * This condition is applied to all ADC features, for efficiency 00357 * and compatibility over all STM32 families. However, the different 00358 * features can be set under different ADC state conditions 00359 * (setting possible with ADC enabled without conversion on going, 00360 * ADC enabled with conversion on going, ...) 00361 * Each feature can be updated afterwards with a unitary function 00362 * and potentially with ADC in a different state than disabled, 00363 * refer to description of each function for setting 00364 * conditioned to ADC state. 00365 */ 00366 typedef struct 00367 { 00368 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 00369 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE 00370 @note On this STM32 serie, external trigger is set with trigger polarity: rising edge 00371 (only trigger polarity available on this STM32 serie). 00372 00373 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ 00374 00375 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. 00376 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH 00377 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). 00378 00379 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ 00380 00381 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 00382 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE 00383 @note This parameter has an effect only if group injected sequencer is enabled 00384 (scan length of 2 ranks or more). 00385 00386 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ 00387 00388 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. 00389 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO 00390 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. 00391 00392 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ 00393 00394 } LL_ADC_INJ_InitTypeDef; 00395 00396 /** 00397 * @} 00398 */ 00399 #endif /* USE_FULL_LL_DRIVER */ 00400 00401 /* Exported constants --------------------------------------------------------*/ 00402 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants 00403 * @{ 00404 */ 00405 00406 /** @defgroup ADC_LL_EC_FLAG ADC flags 00407 * @brief Flags defines which can be used with LL_ADC_ReadReg function 00408 * @{ 00409 */ 00410 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ 00411 #define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ 00412 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ 00413 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00414 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ 00415 #if defined(ADC_MULTIMODE_SUPPORT) 00416 #define LL_ADC_FLAG_EOS_MST ADC_SR_EOC /*!< ADC flag ADC multimode master group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ 00417 #define LL_ADC_FLAG_EOS_SLV ADC_SR_EOC /*!< ADC flag ADC multimode slave group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ 00418 #define LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00419 #define LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC /*!< ADC flag ADC multimode slave group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ 00420 #define LL_ADC_FLAG_AWD1_MST ADC_SR_AWD /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ 00421 #define LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ 00422 #endif 00423 /** 00424 * @} 00425 */ 00426 00427 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) 00428 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions 00429 * @{ 00430 */ 00431 #define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ 00432 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00433 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ 00434 /** 00435 * @} 00436 */ 00437 00438 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose 00439 * @{ 00440 */ 00441 /* List of ADC registers intended to be used (most commonly) with */ 00442 /* DMA transfer. */ 00443 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ 00444 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ 00445 #if defined(ADC_MULTIMODE_SUPPORT) 00446 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ 00447 #endif 00448 /** 00449 * @} 00450 */ 00451 00452 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels 00453 * @{ 00454 */ 00455 /* Note: Other measurement paths to internal channels may be available */ 00456 /* (connections to other peripherals). */ 00457 /* If they are not listed below, they do not require any specific */ 00458 /* path enable. In this case, Access to measurement path is done */ 00459 /* only by selecting the corresponding ADC internal channel. */ 00460 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */ 00461 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ 00462 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ 00463 /** 00464 * @} 00465 */ 00466 00467 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution 00468 * @{ 00469 */ 00470 #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */ 00471 /** 00472 * @} 00473 */ 00474 00475 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment 00476 * @{ 00477 */ 00478 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 00479 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ 00480 /** 00481 * @} 00482 */ 00483 00484 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection 00485 * @{ 00486 */ 00487 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ 00488 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ 00489 /** 00490 * @} 00491 */ 00492 00493 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups 00494 * @{ 00495 */ 00496 #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */ 00497 #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/ 00498 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */ 00499 /** 00500 * @} 00501 */ 00502 00503 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number 00504 * @{ 00505 */ 00506 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 00507 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 00508 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 00509 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 00510 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 00511 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 00512 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 00513 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 00514 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 00515 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 00516 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 00517 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 00518 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 00519 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 00520 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 00521 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 00522 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 00523 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 00524 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F1, ADC channel available only on ADC instance: ADC1. */ 00525 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */ 00526 /** 00527 * @} 00528 */ 00529 00530 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source 00531 * @{ 00532 */ 00533 /* ADC group regular external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */ 00534 #define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal: SW start. */ 00535 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00536 /* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */ 00537 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00538 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00539 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00540 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 00541 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00542 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 00543 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) 00544 /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ 00545 /* XL-density devices. */ 00546 /* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */ 00547 /* A remap of trigger must be done at top level (refer to */ 00548 /* AFIO peripheral). */ 00549 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).*/ 00550 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00551 #if defined (STM32F103xE) || defined (STM32F103xG) 00552 /* ADC group regular external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */ 00553 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00554 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00555 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00556 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 00557 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00558 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00559 #endif 00560 /** 00561 * @} 00562 */ 00563 00564 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge 00565 * @{ 00566 */ 00567 #define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG /*!< ADC group regular conversion trigger polarity set to rising edge */ 00568 /** 00569 * @} 00570 */ 00571 00572 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode 00573 * @{ 00574 */ 00575 #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */ 00576 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ 00577 /** 00578 * @} 00579 */ 00580 00581 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data 00582 * @{ 00583 */ 00584 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */ 00585 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ 00586 /** 00587 * @} 00588 */ 00589 00590 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length 00591 * @{ 00592 */ 00593 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 00594 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ 00595 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ 00596 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ 00597 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ 00598 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ 00599 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ 00600 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ 00601 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ 00602 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ 00603 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ 00604 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ 00605 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ 00606 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ 00607 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ 00608 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ 00609 /** 00610 * @} 00611 */ 00612 00613 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode 00614 * @{ 00615 */ 00616 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */ 00617 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ 00618 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ 00619 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ 00620 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ 00621 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ 00622 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ 00623 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ 00624 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ 00625 /** 00626 * @} 00627 */ 00628 00629 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 00630 * @{ 00631 */ 00632 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ 00633 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ 00634 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ 00635 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ 00636 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ 00637 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ 00638 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ 00639 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ 00640 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ 00641 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ 00642 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ 00643 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ 00644 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ 00645 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ 00646 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ 00647 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ 00648 /** 00649 * @} 00650 */ 00651 00652 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source 00653 * @{ 00654 */ 00655 /* ADC group injected external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */ 00656 #define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal: SW start. */ 00657 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 00658 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00659 /* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */ 00660 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00661 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00662 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00663 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 00664 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 00665 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) 00666 /* Note: TIM8_CH4 is available on ADC1 and ADC2 only in high-density and */ 00667 /* XL-density devices. */ 00668 /* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */ 00669 /* A remap of trigger must be done at top level (refer to */ 00670 /* AFIO peripheral). */ 00671 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). */ 00672 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00673 #if defined (STM32F103xE) || defined (STM32F103xG) 00674 /* ADC group injected external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */ 00675 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00676 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00677 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00678 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ 00679 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00680 #endif 00681 /** 00682 * @} 00683 */ 00684 00685 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge 00686 * @{ 00687 */ 00688 #define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG /*!< ADC group injected conversion trigger polarity set to rising edge */ 00689 /** 00690 * @} 00691 */ 00692 00693 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode 00694 * @{ 00695 */ 00696 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ 00697 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ 00698 /** 00699 * @} 00700 */ 00701 00702 00703 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length 00704 * @{ 00705 */ 00706 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 00707 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ 00708 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ 00709 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ 00710 /** 00711 * @} 00712 */ 00713 00714 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode 00715 * @{ 00716 */ 00717 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */ 00718 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ 00719 /** 00720 * @} 00721 */ 00722 00723 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 00724 * @{ 00725 */ 00726 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */ 00727 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */ 00728 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */ 00729 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */ 00730 /** 00731 * @} 00732 */ 00733 00734 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 00735 * @{ 00736 */ 00737 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ 00738 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */ 00739 #define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */ 00740 #define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */ 00741 #define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */ 00742 #define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */ 00743 #define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */ 00744 #define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */ 00745 /** 00746 * @} 00747 */ 00748 00749 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 00750 * @{ 00751 */ 00752 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ 00753 /** 00754 * @} 00755 */ 00756 00757 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels 00758 * @{ 00759 */ 00760 #define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */ 00761 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ 00762 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ 00763 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ 00764 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ 00765 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ 00766 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ 00767 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ 00768 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ 00769 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ 00770 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ 00771 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ 00772 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ 00773 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ 00774 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ 00775 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ 00776 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ 00777 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ 00778 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ 00779 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ 00780 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ 00781 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ 00782 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ 00783 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ 00784 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ 00785 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ 00786 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ 00787 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ 00788 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ 00789 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ 00790 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ 00791 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ 00792 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ 00793 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ 00794 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ 00795 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ 00796 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ 00797 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ 00798 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ 00799 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ 00800 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ 00801 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ 00802 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ 00803 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ 00804 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ 00805 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ 00806 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ 00807 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ 00808 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ 00809 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ 00810 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ 00811 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ 00812 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ 00813 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ 00814 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ 00815 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ 00816 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ 00817 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ 00818 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ 00819 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ 00820 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ 00821 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ 00822 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ 00823 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ 00824 /** 00825 * @} 00826 */ 00827 00828 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds 00829 * @{ 00830 */ 00831 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ 00832 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ 00833 /** 00834 * @} 00835 */ 00836 00837 #if !defined(ADC_MULTIMODE_SUPPORT) 00838 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode 00839 * @{ 00840 */ 00841 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ 00842 /** 00843 * @} 00844 */ 00845 #endif 00846 #if defined(ADC_MULTIMODE_SUPPORT) 00847 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode 00848 * @{ 00849 */ 00850 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ 00851 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ 00852 #define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices)) */ 00853 #define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */ 00854 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */ 00855 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 00856 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 00857 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 00858 #define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous */ 00859 #define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous */ 00860 00861 /** 00862 * @} 00863 */ 00864 00865 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave 00866 * @{ 00867 */ 00868 #define LL_ADC_MULTI_MASTER ( ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: ADC master */ 00869 #define LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA ) /*!< In multimode, selection among several ADC instances: ADC slave */ 00870 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ 00871 /** 00872 * @} 00873 */ 00874 00875 #endif /* ADC_MULTIMODE_SUPPORT */ 00876 00877 00878 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays 00879 * @note Only ADC IP HW delays are defined in ADC LL driver driver, 00880 * not timeout values. 00881 * For details on delays values, refer to descriptions in source code 00882 * above each literal definition. 00883 * @{ 00884 */ 00885 00886 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ 00887 /* not timeout values. */ 00888 /* Timeout values for ADC operations are dependent to device clock */ 00889 /* configuration (system clock versus ADC clock), */ 00890 /* and therefore must be defined in user application. */ 00891 /* Indications for estimation of ADC timeout delays, for this */ 00892 /* STM32 serie: */ 00893 /* - ADC enable time: maximum delay is 1us */ 00894 /* (refer to device datasheet, parameter "tSTAB") */ 00895 /* - ADC conversion time: duration depending on ADC clock and ADC */ 00896 /* configuration. */ 00897 /* (refer to device reference manual, section "Timing") */ 00898 00899 /* Delay for temperature sensor stabilization time. */ 00900 /* Literal set to maximum value (refer to device datasheet, */ 00901 /* parameter "tSTART"). */ 00902 /* Unit: us */ 00903 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U) /*!< Delay for internal voltage reference stabilization time */ 00904 00905 /* Delay required between ADC disable and ADC calibration start. */ 00906 /* Note: On this STM32 serie, before starting a calibration, */ 00907 /* ADC must be disabled. */ 00908 /* A minimum number of ADC clock cycles are required */ 00909 /* between ADC disable state and calibration start. */ 00910 /* Refer to literal @ref LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES. */ 00911 /* Wait time can be computed in user application by waiting for the */ 00912 /* equivalent number of CPU cycles, by taking into account */ 00913 /* ratio of CPU clock versus ADC clock prescalers. */ 00914 /* Unit: ADC clock cycles. */ 00915 #define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between ADC disable and ADC calibration start */ 00916 00917 /* Delay required between end of ADC Enable and the start of ADC calibration. */ 00918 /* Note: On this STM32 serie, a minimum number of ADC clock cycles */ 00919 /* are required between the end of ADC enable and the start of ADC */ 00920 /* calibration. */ 00921 /* Wait time can be computed in user application by waiting for the */ 00922 /* equivalent number of CPU cycles, by taking into account */ 00923 /* ratio of CPU clock versus ADC clock prescalers. */ 00924 /* Unit: ADC clock cycles. */ 00925 #define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between end of ADC enable and the start of ADC calibration */ 00926 00927 /** 00928 * @} 00929 */ 00930 00931 /** 00932 * @} 00933 */ 00934 00935 00936 /* Exported macro ------------------------------------------------------------*/ 00937 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros 00938 * @{ 00939 */ 00940 00941 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros 00942 * @{ 00943 */ 00944 00945 /** 00946 * @brief Write a value in ADC register 00947 * @param __INSTANCE__ ADC Instance 00948 * @param __REG__ Register to be written 00949 * @param __VALUE__ Value to be written in the register 00950 * @retval None 00951 */ 00952 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00953 00954 /** 00955 * @brief Read a value in ADC register 00956 * @param __INSTANCE__ ADC Instance 00957 * @param __REG__ Register to be read 00958 * @retval Register value 00959 */ 00960 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00961 /** 00962 * @} 00963 */ 00964 00965 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro 00966 * @{ 00967 */ 00968 00969 /** 00970 * @brief Helper macro to get ADC channel number in decimal format 00971 * from literals LL_ADC_CHANNEL_x. 00972 * @note Example: 00973 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) 00974 * will return decimal number "4". 00975 * @note The input can be a value from functions where a channel 00976 * number is returned, either defined with number 00977 * or with bitfield (only one bit must be set). 00978 * @param __CHANNEL__ This parameter can be one of the following values: 00979 * @arg @ref LL_ADC_CHANNEL_0 00980 * @arg @ref LL_ADC_CHANNEL_1 00981 * @arg @ref LL_ADC_CHANNEL_2 00982 * @arg @ref LL_ADC_CHANNEL_3 00983 * @arg @ref LL_ADC_CHANNEL_4 00984 * @arg @ref LL_ADC_CHANNEL_5 00985 * @arg @ref LL_ADC_CHANNEL_6 00986 * @arg @ref LL_ADC_CHANNEL_7 00987 * @arg @ref LL_ADC_CHANNEL_8 00988 * @arg @ref LL_ADC_CHANNEL_9 00989 * @arg @ref LL_ADC_CHANNEL_10 00990 * @arg @ref LL_ADC_CHANNEL_11 00991 * @arg @ref LL_ADC_CHANNEL_12 00992 * @arg @ref LL_ADC_CHANNEL_13 00993 * @arg @ref LL_ADC_CHANNEL_14 00994 * @arg @ref LL_ADC_CHANNEL_15 00995 * @arg @ref LL_ADC_CHANNEL_16 00996 * @arg @ref LL_ADC_CHANNEL_17 00997 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 00998 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 00999 * 01000 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 01001 * @retval Value between Min_Data=0 and Max_Data=18 01002 */ 01003 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 01004 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) 01005 01006 /** 01007 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x 01008 * from number in decimal format. 01009 * @note Example: 01010 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) 01011 * will return a data equivalent to "LL_ADC_CHANNEL_4". 01012 * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 01013 * @retval Returned value can be one of the following values: 01014 * @arg @ref LL_ADC_CHANNEL_0 01015 * @arg @ref LL_ADC_CHANNEL_1 01016 * @arg @ref LL_ADC_CHANNEL_2 01017 * @arg @ref LL_ADC_CHANNEL_3 01018 * @arg @ref LL_ADC_CHANNEL_4 01019 * @arg @ref LL_ADC_CHANNEL_5 01020 * @arg @ref LL_ADC_CHANNEL_6 01021 * @arg @ref LL_ADC_CHANNEL_7 01022 * @arg @ref LL_ADC_CHANNEL_8 01023 * @arg @ref LL_ADC_CHANNEL_9 01024 * @arg @ref LL_ADC_CHANNEL_10 01025 * @arg @ref LL_ADC_CHANNEL_11 01026 * @arg @ref LL_ADC_CHANNEL_12 01027 * @arg @ref LL_ADC_CHANNEL_13 01028 * @arg @ref LL_ADC_CHANNEL_14 01029 * @arg @ref LL_ADC_CHANNEL_15 01030 * @arg @ref LL_ADC_CHANNEL_16 01031 * @arg @ref LL_ADC_CHANNEL_17 01032 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01033 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 01034 * 01035 * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n 01036 * (1) For ADC channel read back from ADC register, 01037 * comparison with internal channel parameter to be done 01038 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01039 */ 01040 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 01041 (((__DECIMAL_NB__) <= 9U) \ 01042 ? ( \ 01043 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 01044 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 01045 ) \ 01046 : \ 01047 ( \ 01048 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 01049 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 01050 ) \ 01051 ) 01052 01053 /** 01054 * @brief Helper macro to determine whether the selected channel 01055 * corresponds to literal definitions of driver. 01056 * @note The different literal definitions of ADC channels are: 01057 * - ADC internal channel: 01058 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... 01059 * - ADC external channel (channel connected to a GPIO pin): 01060 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... 01061 * @note The channel parameter must be a value defined from literal 01062 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01063 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01064 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), 01065 * must not be a value from functions where a channel number is 01066 * returned from ADC registers, 01067 * because internal and external channels share the same channel 01068 * number in ADC registers. The differentiation is made only with 01069 * parameters definitions of driver. 01070 * @param __CHANNEL__ This parameter can be one of the following values: 01071 * @arg @ref LL_ADC_CHANNEL_0 01072 * @arg @ref LL_ADC_CHANNEL_1 01073 * @arg @ref LL_ADC_CHANNEL_2 01074 * @arg @ref LL_ADC_CHANNEL_3 01075 * @arg @ref LL_ADC_CHANNEL_4 01076 * @arg @ref LL_ADC_CHANNEL_5 01077 * @arg @ref LL_ADC_CHANNEL_6 01078 * @arg @ref LL_ADC_CHANNEL_7 01079 * @arg @ref LL_ADC_CHANNEL_8 01080 * @arg @ref LL_ADC_CHANNEL_9 01081 * @arg @ref LL_ADC_CHANNEL_10 01082 * @arg @ref LL_ADC_CHANNEL_11 01083 * @arg @ref LL_ADC_CHANNEL_12 01084 * @arg @ref LL_ADC_CHANNEL_13 01085 * @arg @ref LL_ADC_CHANNEL_14 01086 * @arg @ref LL_ADC_CHANNEL_15 01087 * @arg @ref LL_ADC_CHANNEL_16 01088 * @arg @ref LL_ADC_CHANNEL_17 01089 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01090 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 01091 * 01092 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 01093 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 01094 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 01095 */ 01096 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 01097 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) 01098 01099 /** 01100 * @brief Helper macro to convert a channel defined from parameter 01101 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01102 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01103 * to its equivalent parameter definition of a ADC external channel 01104 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). 01105 * @note The channel parameter can be, additionally to a value 01106 * defined from parameter definition of a ADC internal channel 01107 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), 01108 * a value defined from parameter definition of 01109 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 01110 * or a value from functions where a channel number is returned 01111 * from ADC registers. 01112 * @param __CHANNEL__ This parameter can be one of the following values: 01113 * @arg @ref LL_ADC_CHANNEL_0 01114 * @arg @ref LL_ADC_CHANNEL_1 01115 * @arg @ref LL_ADC_CHANNEL_2 01116 * @arg @ref LL_ADC_CHANNEL_3 01117 * @arg @ref LL_ADC_CHANNEL_4 01118 * @arg @ref LL_ADC_CHANNEL_5 01119 * @arg @ref LL_ADC_CHANNEL_6 01120 * @arg @ref LL_ADC_CHANNEL_7 01121 * @arg @ref LL_ADC_CHANNEL_8 01122 * @arg @ref LL_ADC_CHANNEL_9 01123 * @arg @ref LL_ADC_CHANNEL_10 01124 * @arg @ref LL_ADC_CHANNEL_11 01125 * @arg @ref LL_ADC_CHANNEL_12 01126 * @arg @ref LL_ADC_CHANNEL_13 01127 * @arg @ref LL_ADC_CHANNEL_14 01128 * @arg @ref LL_ADC_CHANNEL_15 01129 * @arg @ref LL_ADC_CHANNEL_16 01130 * @arg @ref LL_ADC_CHANNEL_17 01131 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01132 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 01133 * 01134 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 01135 * @retval Returned value can be one of the following values: 01136 * @arg @ref LL_ADC_CHANNEL_0 01137 * @arg @ref LL_ADC_CHANNEL_1 01138 * @arg @ref LL_ADC_CHANNEL_2 01139 * @arg @ref LL_ADC_CHANNEL_3 01140 * @arg @ref LL_ADC_CHANNEL_4 01141 * @arg @ref LL_ADC_CHANNEL_5 01142 * @arg @ref LL_ADC_CHANNEL_6 01143 * @arg @ref LL_ADC_CHANNEL_7 01144 * @arg @ref LL_ADC_CHANNEL_8 01145 * @arg @ref LL_ADC_CHANNEL_9 01146 * @arg @ref LL_ADC_CHANNEL_10 01147 * @arg @ref LL_ADC_CHANNEL_11 01148 * @arg @ref LL_ADC_CHANNEL_12 01149 * @arg @ref LL_ADC_CHANNEL_13 01150 * @arg @ref LL_ADC_CHANNEL_14 01151 * @arg @ref LL_ADC_CHANNEL_15 01152 * @arg @ref LL_ADC_CHANNEL_16 01153 * @arg @ref LL_ADC_CHANNEL_17 01154 */ 01155 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 01156 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) 01157 01158 /** 01159 * @brief Helper macro to determine whether the internal channel 01160 * selected is available on the ADC instance selected. 01161 * @note The channel parameter must be a value defined from parameter 01162 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01163 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01164 * must not be a value defined from parameter definition of 01165 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 01166 * or a value from functions where a channel number is 01167 * returned from ADC registers, 01168 * because internal and external channels share the same channel 01169 * number in ADC registers. The differentiation is made only with 01170 * parameters definitions of driver. 01171 * @param __ADC_INSTANCE__ ADC instance 01172 * @param __CHANNEL__ This parameter can be one of the following values: 01173 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01174 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 01175 * 01176 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 01177 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 01178 * Value "1" if the internal channel selected is available on the ADC instance selected. 01179 */ 01180 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 01181 (((__ADC_INSTANCE__) == ADC1) \ 01182 ? ( \ 01183 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01184 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \ 01185 ) \ 01186 : \ 01187 (0U) \ 01188 ) 01189 01190 /** 01191 * @brief Helper macro to define ADC analog watchdog parameter: 01192 * define a single channel to monitor with analog watchdog 01193 * from sequencer channel and groups definition. 01194 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). 01195 * Example: 01196 * LL_ADC_SetAnalogWDMonitChannels( 01197 * ADC1, LL_ADC_AWD1, 01198 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) 01199 * @param __CHANNEL__ This parameter can be one of the following values: 01200 * @arg @ref LL_ADC_CHANNEL_0 01201 * @arg @ref LL_ADC_CHANNEL_1 01202 * @arg @ref LL_ADC_CHANNEL_2 01203 * @arg @ref LL_ADC_CHANNEL_3 01204 * @arg @ref LL_ADC_CHANNEL_4 01205 * @arg @ref LL_ADC_CHANNEL_5 01206 * @arg @ref LL_ADC_CHANNEL_6 01207 * @arg @ref LL_ADC_CHANNEL_7 01208 * @arg @ref LL_ADC_CHANNEL_8 01209 * @arg @ref LL_ADC_CHANNEL_9 01210 * @arg @ref LL_ADC_CHANNEL_10 01211 * @arg @ref LL_ADC_CHANNEL_11 01212 * @arg @ref LL_ADC_CHANNEL_12 01213 * @arg @ref LL_ADC_CHANNEL_13 01214 * @arg @ref LL_ADC_CHANNEL_14 01215 * @arg @ref LL_ADC_CHANNEL_15 01216 * @arg @ref LL_ADC_CHANNEL_16 01217 * @arg @ref LL_ADC_CHANNEL_17 01218 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01219 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 01220 * 01221 * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n 01222 * (1) For ADC channel read back from ADC register, 01223 * comparison with internal channel parameter to be done 01224 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01225 * @param __GROUP__ This parameter can be one of the following values: 01226 * @arg @ref LL_ADC_GROUP_REGULAR 01227 * @arg @ref LL_ADC_GROUP_INJECTED 01228 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED 01229 * @retval Returned value can be one of the following values: 01230 * @arg @ref LL_ADC_AWD_DISABLE 01231 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 01232 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 01233 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 01234 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 01235 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 01236 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 01237 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 01238 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 01239 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 01240 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 01241 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 01242 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 01243 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 01244 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 01245 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 01246 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 01247 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 01248 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 01249 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 01250 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 01251 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 01252 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 01253 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 01254 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 01255 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 01256 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 01257 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 01258 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 01259 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 01260 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 01261 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 01262 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 01263 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 01264 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 01265 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 01266 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 01267 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 01268 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 01269 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 01270 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 01271 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 01272 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 01273 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 01274 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 01275 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 01276 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 01277 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 01278 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 01279 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 01280 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 01281 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 01282 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 01283 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 01284 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 01285 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 01286 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 01287 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 01288 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) 01289 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) 01290 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 01291 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1) 01292 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1) 01293 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) 01294 * 01295 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 01296 */ 01297 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ 01298 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ 01299 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ 01300 : \ 01301 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ 01302 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ 01303 : \ 01304 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ 01305 ) 01306 01307 /** 01308 * @brief Helper macro to set the value of ADC analog watchdog threshold high 01309 * or low in function of ADC resolution, when ADC resolution is 01310 * different of 12 bits. 01311 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). 01312 * Example, with a ADC resolution of 8 bits, to set the value of 01313 * analog watchdog threshold high (on 8 bits): 01314 * LL_ADC_SetAnalogWDThresholds 01315 * (< ADCx param >, 01316 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) 01317 * ); 01318 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01319 * @arg @ref LL_ADC_RESOLUTION_12B 01320 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF 01321 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01322 */ 01323 /* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */ 01324 /* This macro has been kept anyway for compatibility with other */ 01325 /* STM32 families featuring different ADC resolutions. */ 01326 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ 01327 ((__AWD_THRESHOLD__) << (0U)) 01328 01329 /** 01330 * @brief Helper macro to get the value of ADC analog watchdog threshold high 01331 * or low in function of ADC resolution, when ADC resolution is 01332 * different of 12 bits. 01333 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). 01334 * Example, with a ADC resolution of 8 bits, to get the value of 01335 * analog watchdog threshold high (on 8 bits): 01336 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION 01337 * (LL_ADC_RESOLUTION_8B, 01338 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) 01339 * ); 01340 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01341 * @arg @ref LL_ADC_RESOLUTION_12B 01342 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF 01343 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01344 */ 01345 /* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */ 01346 /* This macro has been kept anyway for compatibility with other */ 01347 /* STM32 families featuring different ADC resolutions. */ 01348 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ 01349 (__AWD_THRESHOLD_12_BITS__) 01350 01351 #if defined(ADC_MULTIMODE_SUPPORT) 01352 /** 01353 * @brief Helper macro to get the ADC multimode conversion data of ADC master 01354 * or ADC slave from raw value with both ADC conversion data concatenated. 01355 * @note This macro is intended to be used when multimode transfer by DMA 01356 * is enabled. 01357 * In this case the transferred data need to processed with this macro 01358 * to separate the conversion data of ADC master and ADC slave. 01359 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 01360 * @arg @ref LL_ADC_MULTI_MASTER 01361 * @arg @ref LL_ADC_MULTI_SLAVE 01362 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 01363 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01364 */ 01365 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 01366 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA) 01367 #endif 01368 01369 /** 01370 * @brief Helper macro to select the ADC common instance 01371 * to which is belonging the selected ADC instance. 01372 * @note ADC common register instance can be used for: 01373 * - Set parameters common to several ADC instances 01374 * - Multimode (for devices with several ADC instances) 01375 * Refer to functions having argument "ADCxy_COMMON" as parameter. 01376 * @note On STM32F1, there is no common ADC instance. 01377 * However, ADC instance ADC1 has a role of common ADC instance 01378 * for ADC1 and ADC2: 01379 * this instance is used to manage internal channels 01380 * and multimode (these features are managed in ADC common 01381 * instances on some other STM32 devices). 01382 * ADC instance ADC3 (if available on the selected device) 01383 * has no ADC common instance. 01384 * @param __ADCx__ ADC instance 01385 * @retval ADC common register instance 01386 */ 01387 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 01388 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 01389 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \ 01390 ? ( \ 01391 (ADC12_COMMON) \ 01392 ) \ 01393 : \ 01394 ( \ 01395 (0U) \ 01396 ) \ 01397 ) 01398 #elif defined(ADC1) && defined(ADC2) 01399 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 01400 (ADC12_COMMON) 01401 #else 01402 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 01403 (ADC1_COMMON) 01404 #endif 01405 01406 /** 01407 * @brief Helper macro to check if all ADC instances sharing the same 01408 * ADC common instance are disabled. 01409 * @note This check is required by functions with setting conditioned to 01410 * ADC state: 01411 * All ADC instances of the ADC common group must be disabled. 01412 * Refer to functions having argument "ADCxy_COMMON" as parameter. 01413 * @note On devices with only 1 ADC common instance, parameter of this macro 01414 * is useless and can be ignored (parameter kept for compatibility 01415 * with devices featuring several ADC common instances). 01416 * @note On STM32F1, there is no common ADC instance. 01417 * However, ADC instance ADC1 has a role of common ADC instance 01418 * for ADC1 and ADC2: 01419 * this instance is used to manage internal channels 01420 * and multimode (these features are managed in ADC common 01421 * instances on some other STM32 devices). 01422 * ADC instance ADC3 (if available on the selected device) 01423 * has no ADC common instance. 01424 * @param __ADCXY_COMMON__ ADC common instance 01425 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01426 * @retval Value "0" if all ADC instances sharing the same ADC common instance 01427 * are disabled. 01428 * Value "1" if at least one ADC instance sharing the same ADC common instance 01429 * is enabled. 01430 */ 01431 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 01432 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 01433 (((__ADCXY_COMMON__) == ADC12_COMMON) \ 01434 ? ( \ 01435 (LL_ADC_IsEnabled(ADC1) | \ 01436 LL_ADC_IsEnabled(ADC2) ) \ 01437 ) \ 01438 : \ 01439 ( \ 01440 LL_ADC_IsEnabled(ADC3) \ 01441 ) \ 01442 ) 01443 #elif defined(ADC1) && defined(ADC2) 01444 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 01445 (LL_ADC_IsEnabled(ADC1) | \ 01446 LL_ADC_IsEnabled(ADC2) ) 01447 #else 01448 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 01449 LL_ADC_IsEnabled(ADC1) 01450 #endif 01451 01452 /** 01453 * @brief Helper macro to define the ADC conversion data full-scale digital 01454 * value corresponding to the selected ADC resolution. 01455 * @note ADC conversion data full-scale corresponds to voltage range 01456 * determined by analog voltage references Vref+ and Vref- 01457 * (refer to reference manual). 01458 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01459 * @arg @ref LL_ADC_RESOLUTION_12B 01460 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 01461 */ 01462 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 01463 (0xFFFU) 01464 01465 01466 /** 01467 * @brief Helper macro to calculate the voltage (unit: mVolt) 01468 * corresponding to a ADC conversion data (unit: digital value). 01469 * @note Analog reference voltage (Vref+) must be known from 01470 * user board environment or can be calculated using ADC measurement. 01471 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 01472 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 01473 * (unit: digital value). 01474 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01475 * @arg @ref LL_ADC_RESOLUTION_12B 01476 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 01477 */ 01478 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 01479 __ADC_DATA__,\ 01480 __ADC_RESOLUTION__) \ 01481 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ 01482 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 01483 ) 01484 01485 01486 /** 01487 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 01488 * from ADC conversion data of internal temperature sensor. 01489 * @note Computation is using temperature sensor typical values 01490 * (refer to device datasheet). 01491 * @note Calculation formula: 01492 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 01493 * / Avg_Slope + CALx_TEMP 01494 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 01495 * (unit: digital value) 01496 * Avg_Slope = temperature sensor slope 01497 * (unit: uV/Degree Celsius) 01498 * TS_TYP_CALx_VOLT = temperature sensor digital value at 01499 * temperature CALx_TEMP (unit: mV) 01500 * Caution: Calculation relevancy under reserve the temperature sensor 01501 * of the current device has characteristics in line with 01502 * datasheet typical values. 01503 * If temperature sensor calibration values are available on 01504 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 01505 * temperature calculation will be more accurate using 01506 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 01507 * @note As calculation input, the analog reference voltage (Vref+) must be 01508 * defined as it impacts the ADC LSB equivalent voltage. 01509 * @note Analog reference voltage (Vref+) must be known from 01510 * user board environment or can be calculated using ADC measurement. 01511 * @note ADC measurement data must correspond to a resolution of 12bits 01512 * (full scale digital value 4095). If not the case, the data must be 01513 * preliminarily rescaled to an equivalent resolution of 12 bits. 01514 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 01515 * On STM32F1, refer to device datasheet parameter "Avg_Slope". 01516 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 01517 * On STM32F1, refer to device datasheet parameter "V25". 01518 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 01519 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 01520 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 01521 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 01522 * This parameter can be one of the following values: 01523 * @arg @ref LL_ADC_RESOLUTION_12B 01524 * @retval Temperature (unit: degree Celsius) 01525 */ 01526 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 01527 __TEMPSENSOR_TYP_CALX_V__,\ 01528 __TEMPSENSOR_CALX_TEMP__,\ 01529 __VREFANALOG_VOLTAGE__,\ 01530 __TEMPSENSOR_ADC_DATA__,\ 01531 __ADC_RESOLUTION__) \ 01532 ((( ( \ 01533 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ 01534 * 1000) \ 01535 - \ 01536 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ 01537 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ 01538 * 1000) \ 01539 ) \ 01540 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ 01541 ) + (__TEMPSENSOR_CALX_TEMP__) \ 01542 ) 01543 01544 /** 01545 * @} 01546 */ 01547 01548 /** 01549 * @} 01550 */ 01551 01552 01553 /* Exported functions --------------------------------------------------------*/ 01554 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions 01555 * @{ 01556 */ 01557 01558 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management 01559 * @{ 01560 */ 01561 /* Note: LL ADC functions to set DMA transfer are located into sections of */ 01562 /* configuration of ADC instance, groups and multimode (if available): */ 01563 /* @ref LL_ADC_REG_SetDMATransfer(), ... */ 01564 01565 /** 01566 * @brief Function to help to configure DMA transfer from ADC: retrieve the 01567 * ADC register address from ADC instance and a list of ADC registers 01568 * intended to be used (most commonly) with DMA transfer. 01569 * @note These ADC registers are data registers: 01570 * when ADC conversion data is available in ADC data registers, 01571 * ADC generates a DMA transfer request. 01572 * @note This macro is intended to be used with LL DMA driver, refer to 01573 * function "LL_DMA_ConfigAddresses()". 01574 * Example: 01575 * LL_DMA_ConfigAddresses(DMA1, 01576 * LL_DMA_CHANNEL_1, 01577 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), 01578 * (uint32_t)&< array or variable >, 01579 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); 01580 * @note For devices with several ADC: in multimode, some devices 01581 * use a different data register outside of ADC instance scope 01582 * (common data register). This macro manages this register difference, 01583 * only ADC instance has to be set as parameter. 01584 * @note On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer 01585 * capability, not ADC2 (ADC2 and ADC3 instances not available on 01586 * all devices). 01587 * @note On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3. 01588 * Therefore, the corresponding parameter of data transfer 01589 * for multimode can be used only with ADC1 and ADC2. 01590 * (ADC2 and ADC3 instances not available on all devices). 01591 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr 01592 * @param ADCx ADC instance 01593 * @param Register This parameter can be one of the following values: 01594 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA 01595 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) 01596 * 01597 * (1) Available on devices with several ADC instances. 01598 * @retval ADC register address 01599 */ 01600 #if defined(ADC_MULTIMODE_SUPPORT) 01601 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 01602 { 01603 uint32_t data_reg_addr = 0U; 01604 01605 if (Register == LL_ADC_DMA_REG_REGULAR_DATA) 01606 { 01607 /* Retrieve address of register DR */ 01608 data_reg_addr = (uint32_t)&(ADCx->DR); 01609 } 01610 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ 01611 { 01612 /* Retrieve address of register of multimode data */ 01613 data_reg_addr = (uint32_t)&(ADC12_COMMON->DR); 01614 } 01615 01616 return data_reg_addr; 01617 } 01618 #else 01619 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 01620 { 01621 /* Retrieve address of register DR */ 01622 return (uint32_t)&(ADCx->DR); 01623 } 01624 #endif 01625 01626 /** 01627 * @} 01628 */ 01629 01630 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances 01631 * @{ 01632 */ 01633 01634 /** 01635 * @brief Set parameter common to several ADC: measurement path to internal 01636 * channels (VrefInt, temperature sensor, ...). 01637 * @note One or several values can be selected. 01638 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 01639 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 01640 * @note Stabilization time of measurement path to internal channel: 01641 * After enabling internal paths, before starting ADC conversion, 01642 * a delay is required for internal voltage reference and 01643 * temperature sensor stabilization time. 01644 * Refer to device datasheet. 01645 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. 01646 * @note ADC internal channel sampling time constraint: 01647 * For ADC conversion of internal channels, 01648 * a sampling time minimum value is required. 01649 * Refer to device datasheet. 01650 * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh 01651 * @param ADCxy_COMMON ADC common instance 01652 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01653 * @param PathInternal This parameter can be a combination of the following values: 01654 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 01655 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 01656 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 01657 * @retval None 01658 */ 01659 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) 01660 { 01661 MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal); 01662 } 01663 01664 /** 01665 * @brief Get parameter common to several ADC: measurement path to internal 01666 * channels (VrefInt, temperature sensor, ...). 01667 * @note One or several values can be selected. 01668 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 01669 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 01670 * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh 01671 * @param ADCxy_COMMON ADC common instance 01672 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01673 * @retval Returned value can be a combination of the following values: 01674 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 01675 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 01676 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 01677 */ 01678 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) 01679 { 01680 return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE)); 01681 } 01682 01683 /** 01684 * @} 01685 */ 01686 01687 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance 01688 * @{ 01689 */ 01690 01691 /** 01692 * @brief Set ADC conversion data alignment. 01693 * @note Refer to reference manual for alignments formats 01694 * dependencies to ADC resolutions. 01695 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment 01696 * @param ADCx ADC instance 01697 * @param DataAlignment This parameter can be one of the following values: 01698 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 01699 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 01700 * @retval None 01701 */ 01702 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) 01703 { 01704 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); 01705 } 01706 01707 /** 01708 * @brief Get ADC conversion data alignment. 01709 * @note Refer to reference manual for alignments formats 01710 * dependencies to ADC resolutions. 01711 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment 01712 * @param ADCx ADC instance 01713 * @retval Returned value can be one of the following values: 01714 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 01715 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 01716 */ 01717 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) 01718 { 01719 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); 01720 } 01721 01722 /** 01723 * @brief Set ADC sequencers scan mode, for all ADC groups 01724 * (group regular, group injected). 01725 * @note According to sequencers scan mode : 01726 * - If disabled: ADC conversion is performed in unitary conversion 01727 * mode (one channel converted, that defined in rank 1). 01728 * Configuration of sequencers of all ADC groups 01729 * (sequencer scan length, ...) is discarded: equivalent to 01730 * scan length of 1 rank. 01731 * - If enabled: ADC conversions are performed in sequence conversions 01732 * mode, according to configuration of sequencers of 01733 * each ADC group (sequencer scan length, ...). 01734 * Refer to function @ref LL_ADC_REG_SetSequencerLength() 01735 * and to function @ref LL_ADC_INJ_SetSequencerLength(). 01736 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode 01737 * @param ADCx ADC instance 01738 * @param ScanMode This parameter can be one of the following values: 01739 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE 01740 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE 01741 * @retval None 01742 */ 01743 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) 01744 { 01745 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); 01746 } 01747 01748 /** 01749 * @brief Get ADC sequencers scan mode, for all ADC groups 01750 * (group regular, group injected). 01751 * @note According to sequencers scan mode : 01752 * - If disabled: ADC conversion is performed in unitary conversion 01753 * mode (one channel converted, that defined in rank 1). 01754 * Configuration of sequencers of all ADC groups 01755 * (sequencer scan length, ...) is discarded: equivalent to 01756 * scan length of 1 rank. 01757 * - If enabled: ADC conversions are performed in sequence conversions 01758 * mode, according to configuration of sequencers of 01759 * each ADC group (sequencer scan length, ...). 01760 * Refer to function @ref LL_ADC_REG_SetSequencerLength() 01761 * and to function @ref LL_ADC_INJ_SetSequencerLength(). 01762 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode 01763 * @param ADCx ADC instance 01764 * @retval Returned value can be one of the following values: 01765 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE 01766 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE 01767 */ 01768 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) 01769 { 01770 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); 01771 } 01772 01773 /** 01774 * @} 01775 */ 01776 01777 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular 01778 * @{ 01779 */ 01780 01781 /** 01782 * @brief Set ADC group regular conversion trigger source: 01783 * internal (SW start) or from external IP (timer event, 01784 * external interrupt line). 01785 * @note On this STM32 serie, external trigger is set with trigger polarity: 01786 * rising edge (only trigger polarity available on this STM32 serie). 01787 * @note Availability of parameters of trigger sources from timer 01788 * depends on timers availability on the selected device. 01789 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource 01790 * @param ADCx ADC instance 01791 * @param TriggerSource This parameter can be one of the following values: 01792 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 01793 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) 01794 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2) 01795 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2) 01796 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2) 01797 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2) 01798 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2) 01799 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2) 01800 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4) 01801 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3) 01802 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3) 01803 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3) 01804 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3) 01805 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3) 01806 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3) 01807 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3) 01808 * 01809 * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n 01810 * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n 01811 * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n 01812 * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). 01813 * @retval None 01814 */ 01815 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 01816 { 01817 /* Note: On this STM32 serie, ADC group regular external trigger edge */ 01818 /* is used to perform a ADC conversion start. */ 01819 /* This function does not set external trigger edge. */ 01820 /* This feature is set using function */ 01821 /* @ref LL_ADC_REG_StartConversionExtTrig(). */ 01822 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); 01823 } 01824 01825 /** 01826 * @brief Get ADC group regular conversion trigger source: 01827 * internal (SW start) or from external IP (timer event, 01828 * external interrupt line). 01829 * @note To determine whether group regular trigger source is 01830 * internal (SW start) or external, without detail 01831 * of which peripheral is selected as external trigger, 01832 * (equivalent to 01833 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") 01834 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. 01835 * @note Availability of parameters of trigger sources from timer 01836 * depends on timers availability on the selected device. 01837 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource 01838 * @param ADCx ADC instance 01839 * @retval Returned value can be one of the following values: 01840 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 01841 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) 01842 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2) 01843 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2) 01844 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2) 01845 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2) 01846 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2) 01847 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2) 01848 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4) 01849 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3) 01850 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3) 01851 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3) 01852 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3) 01853 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3) 01854 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3) 01855 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3) 01856 * 01857 * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n 01858 * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n 01859 * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n 01860 * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). 01861 */ 01862 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) 01863 { 01864 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL)); 01865 } 01866 01867 /** 01868 * @brief Get ADC group regular conversion trigger source internal (SW start) 01869 or external. 01870 * @note In case of group regular trigger source set to external trigger, 01871 * to determine which peripheral is selected as external trigger, 01872 * use function @ref LL_ADC_REG_GetTriggerSource(). 01873 * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart 01874 * @param ADCx ADC instance 01875 * @retval Value "0" if trigger source external trigger 01876 * Value "1" if trigger source SW start. 01877 */ 01878 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 01879 { 01880 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE)); 01881 } 01882 01883 01884 /** 01885 * @brief Set ADC group regular sequencer length and scan direction. 01886 * @note Description of ADC group regular sequencer features: 01887 * - For devices with sequencer fully configurable 01888 * (function "LL_ADC_REG_SetSequencerRanks()" available): 01889 * sequencer length and each rank affectation to a channel 01890 * are configurable. 01891 * This function performs configuration of: 01892 * - Sequence length: Number of ranks in the scan sequence. 01893 * - Sequence direction: Unless specified in parameters, sequencer 01894 * scan direction is forward (from rank 1 to rank n). 01895 * Sequencer ranks are selected using 01896 * function "LL_ADC_REG_SetSequencerRanks()". 01897 * - For devices with sequencer not fully configurable 01898 * (function "LL_ADC_REG_SetSequencerChannels()" available): 01899 * sequencer length and each rank affectation to a channel 01900 * are defined by channel number. 01901 * This function performs configuration of: 01902 * - Sequence length: Number of ranks in the scan sequence is 01903 * defined by number of channels set in the sequence, 01904 * rank of each channel is fixed by channel HW number. 01905 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 01906 * - Sequence direction: Unless specified in parameters, sequencer 01907 * scan direction is forward (from lowest channel number to 01908 * highest channel number). 01909 * Sequencer ranks are selected using 01910 * function "LL_ADC_REG_SetSequencerChannels()". 01911 * @note On this STM32 serie, group regular sequencer configuration 01912 * is conditioned to ADC instance sequencer mode. 01913 * If ADC instance sequencer mode is disabled, sequencers of 01914 * all groups (group regular, group injected) can be configured 01915 * but their execution is disabled (limited to rank 1). 01916 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 01917 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 01918 * ADC conversion on only 1 channel. 01919 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength 01920 * @param ADCx ADC instance 01921 * @param SequencerNbRanks This parameter can be one of the following values: 01922 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 01923 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 01924 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 01925 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 01926 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 01927 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 01928 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 01929 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 01930 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 01931 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 01932 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 01933 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 01934 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 01935 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 01936 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 01937 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 01938 * @retval None 01939 */ 01940 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 01941 { 01942 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); 01943 } 01944 01945 /** 01946 * @brief Get ADC group regular sequencer length and scan direction. 01947 * @note Description of ADC group regular sequencer features: 01948 * - For devices with sequencer fully configurable 01949 * (function "LL_ADC_REG_SetSequencerRanks()" available): 01950 * sequencer length and each rank affectation to a channel 01951 * are configurable. 01952 * This function retrieves: 01953 * - Sequence length: Number of ranks in the scan sequence. 01954 * - Sequence direction: Unless specified in parameters, sequencer 01955 * scan direction is forward (from rank 1 to rank n). 01956 * Sequencer ranks are selected using 01957 * function "LL_ADC_REG_SetSequencerRanks()". 01958 * - For devices with sequencer not fully configurable 01959 * (function "LL_ADC_REG_SetSequencerChannels()" available): 01960 * sequencer length and each rank affectation to a channel 01961 * are defined by channel number. 01962 * This function retrieves: 01963 * - Sequence length: Number of ranks in the scan sequence is 01964 * defined by number of channels set in the sequence, 01965 * rank of each channel is fixed by channel HW number. 01966 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 01967 * - Sequence direction: Unless specified in parameters, sequencer 01968 * scan direction is forward (from lowest channel number to 01969 * highest channel number). 01970 * Sequencer ranks are selected using 01971 * function "LL_ADC_REG_SetSequencerChannels()". 01972 * @note On this STM32 serie, group regular sequencer configuration 01973 * is conditioned to ADC instance sequencer mode. 01974 * If ADC instance sequencer mode is disabled, sequencers of 01975 * all groups (group regular, group injected) can be configured 01976 * but their execution is disabled (limited to rank 1). 01977 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 01978 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 01979 * ADC conversion on only 1 channel. 01980 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength 01981 * @param ADCx ADC instance 01982 * @retval Returned value can be one of the following values: 01983 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 01984 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 01985 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 01986 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 01987 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 01988 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 01989 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 01990 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 01991 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 01992 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 01993 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 01994 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 01995 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 01996 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 01997 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 01998 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 01999 */ 02000 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) 02001 { 02002 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); 02003 } 02004 02005 /** 02006 * @brief Set ADC group regular sequencer discontinuous mode: 02007 * sequence subdivided and scan conversions interrupted every selected 02008 * number of ranks. 02009 * @note It is not possible to enable both ADC group regular 02010 * continuous mode and sequencer discontinuous mode. 02011 * @note It is not possible to enable both ADC auto-injected mode 02012 * and ADC group regular sequencer discontinuous mode. 02013 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n 02014 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont 02015 * @param ADCx ADC instance 02016 * @param SeqDiscont This parameter can be one of the following values: 02017 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 02018 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 02019 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 02020 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 02021 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 02022 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 02023 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 02024 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 02025 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 02026 * @retval None 02027 */ 02028 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 02029 { 02030 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); 02031 } 02032 02033 /** 02034 * @brief Get ADC group regular sequencer discontinuous mode: 02035 * sequence subdivided and scan conversions interrupted every selected 02036 * number of ranks. 02037 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n 02038 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont 02039 * @param ADCx ADC instance 02040 * @retval Returned value can be one of the following values: 02041 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 02042 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 02043 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 02044 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 02045 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 02046 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 02047 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 02048 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 02049 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 02050 */ 02051 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) 02052 { 02053 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); 02054 } 02055 02056 /** 02057 * @brief Set ADC group regular sequence: channel on the selected 02058 * scan sequence rank. 02059 * @note This function performs configuration of: 02060 * - Channels ordering into each rank of scan sequence: 02061 * whatever channel can be placed into whatever rank. 02062 * @note On this STM32 serie, ADC group regular sequencer is 02063 * fully configurable: sequencer length and each rank 02064 * affectation to a channel are configurable. 02065 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 02066 * @note Depending on devices and packages, some channels may not be available. 02067 * Refer to device datasheet for channels availability. 02068 * @note On this STM32 serie, to measure internal channels (VrefInt, 02069 * TempSensor, ...), measurement paths to internal channels must be 02070 * enabled separately. 02071 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 02072 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n 02073 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n 02074 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n 02075 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n 02076 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n 02077 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n 02078 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n 02079 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n 02080 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n 02081 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n 02082 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n 02083 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n 02084 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n 02085 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n 02086 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n 02087 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks 02088 * @param ADCx ADC instance 02089 * @param Rank This parameter can be one of the following values: 02090 * @arg @ref LL_ADC_REG_RANK_1 02091 * @arg @ref LL_ADC_REG_RANK_2 02092 * @arg @ref LL_ADC_REG_RANK_3 02093 * @arg @ref LL_ADC_REG_RANK_4 02094 * @arg @ref LL_ADC_REG_RANK_5 02095 * @arg @ref LL_ADC_REG_RANK_6 02096 * @arg @ref LL_ADC_REG_RANK_7 02097 * @arg @ref LL_ADC_REG_RANK_8 02098 * @arg @ref LL_ADC_REG_RANK_9 02099 * @arg @ref LL_ADC_REG_RANK_10 02100 * @arg @ref LL_ADC_REG_RANK_11 02101 * @arg @ref LL_ADC_REG_RANK_12 02102 * @arg @ref LL_ADC_REG_RANK_13 02103 * @arg @ref LL_ADC_REG_RANK_14 02104 * @arg @ref LL_ADC_REG_RANK_15 02105 * @arg @ref LL_ADC_REG_RANK_16 02106 * @param Channel This parameter can be one of the following values: 02107 * @arg @ref LL_ADC_CHANNEL_0 02108 * @arg @ref LL_ADC_CHANNEL_1 02109 * @arg @ref LL_ADC_CHANNEL_2 02110 * @arg @ref LL_ADC_CHANNEL_3 02111 * @arg @ref LL_ADC_CHANNEL_4 02112 * @arg @ref LL_ADC_CHANNEL_5 02113 * @arg @ref LL_ADC_CHANNEL_6 02114 * @arg @ref LL_ADC_CHANNEL_7 02115 * @arg @ref LL_ADC_CHANNEL_8 02116 * @arg @ref LL_ADC_CHANNEL_9 02117 * @arg @ref LL_ADC_CHANNEL_10 02118 * @arg @ref LL_ADC_CHANNEL_11 02119 * @arg @ref LL_ADC_CHANNEL_12 02120 * @arg @ref LL_ADC_CHANNEL_13 02121 * @arg @ref LL_ADC_CHANNEL_14 02122 * @arg @ref LL_ADC_CHANNEL_15 02123 * @arg @ref LL_ADC_CHANNEL_16 02124 * @arg @ref LL_ADC_CHANNEL_17 02125 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02126 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 02127 * 02128 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 02129 * @retval None 02130 */ 02131 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 02132 { 02133 /* Set bits with content of parameter "Channel" with bits position */ 02134 /* in register and register position depending on parameter "Rank". */ 02135 /* Parameters "Rank" and "Channel" are used with masks because containing */ 02136 /* other bits reserved for other purpose. */ 02137 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 02138 02139 MODIFY_REG(*preg, 02140 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), 02141 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); 02142 } 02143 02144 /** 02145 * @brief Get ADC group regular sequence: channel on the selected 02146 * scan sequence rank. 02147 * @note On this STM32 serie, ADC group regular sequencer is 02148 * fully configurable: sequencer length and each rank 02149 * affectation to a channel are configurable. 02150 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 02151 * @note Depending on devices and packages, some channels may not be available. 02152 * Refer to device datasheet for channels availability. 02153 * @note Usage of the returned channel number: 02154 * - To reinject this channel into another function LL_ADC_xxx: 02155 * the returned channel number is only partly formatted on definition 02156 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 02157 * with parts of literals LL_ADC_CHANNEL_x or using 02158 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02159 * Then the selected literal LL_ADC_CHANNEL_x can be used 02160 * as parameter for another function. 02161 * - To get the channel number in decimal format: 02162 * process the returned value with the helper macro 02163 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02164 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n 02165 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n 02166 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n 02167 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n 02168 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n 02169 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n 02170 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n 02171 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n 02172 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n 02173 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n 02174 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n 02175 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n 02176 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n 02177 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n 02178 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n 02179 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks 02180 * @param ADCx ADC instance 02181 * @param Rank This parameter can be one of the following values: 02182 * @arg @ref LL_ADC_REG_RANK_1 02183 * @arg @ref LL_ADC_REG_RANK_2 02184 * @arg @ref LL_ADC_REG_RANK_3 02185 * @arg @ref LL_ADC_REG_RANK_4 02186 * @arg @ref LL_ADC_REG_RANK_5 02187 * @arg @ref LL_ADC_REG_RANK_6 02188 * @arg @ref LL_ADC_REG_RANK_7 02189 * @arg @ref LL_ADC_REG_RANK_8 02190 * @arg @ref LL_ADC_REG_RANK_9 02191 * @arg @ref LL_ADC_REG_RANK_10 02192 * @arg @ref LL_ADC_REG_RANK_11 02193 * @arg @ref LL_ADC_REG_RANK_12 02194 * @arg @ref LL_ADC_REG_RANK_13 02195 * @arg @ref LL_ADC_REG_RANK_14 02196 * @arg @ref LL_ADC_REG_RANK_15 02197 * @arg @ref LL_ADC_REG_RANK_16 02198 * @retval Returned value can be one of the following values: 02199 * @arg @ref LL_ADC_CHANNEL_0 02200 * @arg @ref LL_ADC_CHANNEL_1 02201 * @arg @ref LL_ADC_CHANNEL_2 02202 * @arg @ref LL_ADC_CHANNEL_3 02203 * @arg @ref LL_ADC_CHANNEL_4 02204 * @arg @ref LL_ADC_CHANNEL_5 02205 * @arg @ref LL_ADC_CHANNEL_6 02206 * @arg @ref LL_ADC_CHANNEL_7 02207 * @arg @ref LL_ADC_CHANNEL_8 02208 * @arg @ref LL_ADC_CHANNEL_9 02209 * @arg @ref LL_ADC_CHANNEL_10 02210 * @arg @ref LL_ADC_CHANNEL_11 02211 * @arg @ref LL_ADC_CHANNEL_12 02212 * @arg @ref LL_ADC_CHANNEL_13 02213 * @arg @ref LL_ADC_CHANNEL_14 02214 * @arg @ref LL_ADC_CHANNEL_15 02215 * @arg @ref LL_ADC_CHANNEL_16 02216 * @arg @ref LL_ADC_CHANNEL_17 02217 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02218 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 02219 * 02220 * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n 02221 * (1) For ADC channel read back from ADC register, 02222 * comparison with internal channel parameter to be done 02223 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 02224 */ 02225 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 02226 { 02227 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 02228 02229 return (uint32_t) (READ_BIT(*preg, 02230 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) 02231 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) 02232 ); 02233 } 02234 02235 /** 02236 * @brief Set ADC continuous conversion mode on ADC group regular. 02237 * @note Description of ADC continuous conversion mode: 02238 * - single mode: one conversion per trigger 02239 * - continuous mode: after the first trigger, following 02240 * conversions launched successively automatically. 02241 * @note It is not possible to enable both ADC group regular 02242 * continuous mode and sequencer discontinuous mode. 02243 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode 02244 * @param ADCx ADC instance 02245 * @param Continuous This parameter can be one of the following values: 02246 * @arg @ref LL_ADC_REG_CONV_SINGLE 02247 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 02248 * @retval None 02249 */ 02250 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) 02251 { 02252 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); 02253 } 02254 02255 /** 02256 * @brief Get ADC continuous conversion mode on ADC group regular. 02257 * @note Description of ADC continuous conversion mode: 02258 * - single mode: one conversion per trigger 02259 * - continuous mode: after the first trigger, following 02260 * conversions launched successively automatically. 02261 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode 02262 * @param ADCx ADC instance 02263 * @retval Returned value can be one of the following values: 02264 * @arg @ref LL_ADC_REG_CONV_SINGLE 02265 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 02266 */ 02267 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) 02268 { 02269 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); 02270 } 02271 02272 /** 02273 * @brief Set ADC group regular conversion data transfer: no transfer or 02274 * transfer by DMA, and DMA requests mode. 02275 * @note If transfer by DMA selected, specifies the DMA requests 02276 * mode: 02277 * - Limited mode (One shot mode): DMA transfer requests are stopped 02278 * when number of DMA data transfers (number of 02279 * ADC conversions) is reached. 02280 * This ADC mode is intended to be used with DMA mode non-circular. 02281 * - Unlimited mode: DMA transfer requests are unlimited, 02282 * whatever number of DMA data transfers (number of 02283 * ADC conversions). 02284 * This ADC mode is intended to be used with DMA mode circular. 02285 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 02286 * mode non-circular: 02287 * when DMA transfers size will be reached, DMA will stop transfers of 02288 * ADC conversions data ADC will raise an overrun error 02289 * (overrun flag and interruption if enabled). 02290 * @note To configure DMA source address (peripheral address), 02291 * use function @ref LL_ADC_DMA_GetRegAddr(). 02292 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer 02293 * @param ADCx ADC instance 02294 * @param DMATransfer This parameter can be one of the following values: 02295 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 02296 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 02297 * @retval None 02298 */ 02299 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) 02300 { 02301 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer); 02302 } 02303 02304 /** 02305 * @brief Get ADC group regular conversion data transfer: no transfer or 02306 * transfer by DMA, and DMA requests mode. 02307 * @note If transfer by DMA selected, specifies the DMA requests 02308 * mode: 02309 * - Limited mode (One shot mode): DMA transfer requests are stopped 02310 * when number of DMA data transfers (number of 02311 * ADC conversions) is reached. 02312 * This ADC mode is intended to be used with DMA mode non-circular. 02313 * - Unlimited mode: DMA transfer requests are unlimited, 02314 * whatever number of DMA data transfers (number of 02315 * ADC conversions). 02316 * This ADC mode is intended to be used with DMA mode circular. 02317 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 02318 * mode non-circular: 02319 * when DMA transfers size will be reached, DMA will stop transfers of 02320 * ADC conversions data ADC will raise an overrun error 02321 * (overrun flag and interruption if enabled). 02322 * @note To configure DMA source address (peripheral address), 02323 * use function @ref LL_ADC_DMA_GetRegAddr(). 02324 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer 02325 * @param ADCx ADC instance 02326 * @retval Returned value can be one of the following values: 02327 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 02328 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 02329 */ 02330 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) 02331 { 02332 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA)); 02333 } 02334 02335 /** 02336 * @} 02337 */ 02338 02339 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected 02340 * @{ 02341 */ 02342 02343 /** 02344 * @brief Set ADC group injected conversion trigger source: 02345 * internal (SW start) or from external IP (timer event, 02346 * external interrupt line). 02347 * @note On this STM32 serie, external trigger is set with trigger polarity: 02348 * rising edge (only trigger polarity available on this STM32 serie). 02349 * @note Availability of parameters of trigger sources from timer 02350 * depends on timers availability on the selected device. 02351 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource 02352 * @param ADCx ADC instance 02353 * @param TriggerSource This parameter can be one of the following values: 02354 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 02355 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1) 02356 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1) 02357 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2) 02358 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2) 02359 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2) 02360 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2) 02361 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2) 02362 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4) 02363 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3) 02364 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3) 02365 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3) 02366 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3) 02367 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3) 02368 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3) 02369 * 02370 * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n 02371 * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n 02372 * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n 02373 * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). 02374 * @retval None 02375 */ 02376 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 02377 { 02378 /* Note: On this STM32 serie, ADC group injected external trigger edge */ 02379 /* is used to perform a ADC conversion start. */ 02380 /* This function does not set external trigger edge. */ 02381 /* This feature is set using function */ 02382 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */ 02383 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); 02384 } 02385 02386 /** 02387 * @brief Get ADC group injected conversion trigger source: 02388 * internal (SW start) or from external IP (timer event, 02389 * external interrupt line). 02390 * @note To determine whether group injected trigger source is 02391 * internal (SW start) or external, without detail 02392 * of which peripheral is selected as external trigger, 02393 * (equivalent to 02394 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") 02395 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. 02396 * @note Availability of parameters of trigger sources from timer 02397 * depends on timers availability on the selected device. 02398 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource 02399 * @param ADCx ADC instance 02400 * @retval Returned value can be one of the following values: 02401 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 02402 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1) 02403 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1) 02404 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2) 02405 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2) 02406 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2) 02407 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2) 02408 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2) 02409 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4) 02410 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3) 02411 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3) 02412 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3) 02413 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3) 02414 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3) 02415 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3) 02416 * 02417 * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n 02418 * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n 02419 * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n 02420 * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). 02421 */ 02422 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) 02423 { 02424 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL)); 02425 } 02426 02427 /** 02428 * @brief Get ADC group injected conversion trigger source internal (SW start) 02429 or external 02430 * @note In case of group injected trigger source set to external trigger, 02431 * to determine which peripheral is selected as external trigger, 02432 * use function @ref LL_ADC_INJ_GetTriggerSource. 02433 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart 02434 * @param ADCx ADC instance 02435 * @retval Value "0" if trigger source external trigger 02436 * Value "1" if trigger source SW start. 02437 */ 02438 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 02439 { 02440 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE); 02441 } 02442 02443 /** 02444 * @brief Set ADC group injected sequencer length and scan direction. 02445 * @note This function performs configuration of: 02446 * - Sequence length: Number of ranks in the scan sequence. 02447 * - Sequence direction: Unless specified in parameters, sequencer 02448 * scan direction is forward (from rank 1 to rank n). 02449 * @note On this STM32 serie, group injected sequencer configuration 02450 * is conditioned to ADC instance sequencer mode. 02451 * If ADC instance sequencer mode is disabled, sequencers of 02452 * all groups (group regular, group injected) can be configured 02453 * but their execution is disabled (limited to rank 1). 02454 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 02455 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 02456 * ADC conversion on only 1 channel. 02457 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength 02458 * @param ADCx ADC instance 02459 * @param SequencerNbRanks This parameter can be one of the following values: 02460 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 02461 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 02462 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 02463 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 02464 * @retval None 02465 */ 02466 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 02467 { 02468 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); 02469 } 02470 02471 /** 02472 * @brief Get ADC group injected sequencer length and scan direction. 02473 * @note This function retrieves: 02474 * - Sequence length: Number of ranks in the scan sequence. 02475 * - Sequence direction: Unless specified in parameters, sequencer 02476 * scan direction is forward (from rank 1 to rank n). 02477 * @note On this STM32 serie, group injected sequencer configuration 02478 * is conditioned to ADC instance sequencer mode. 02479 * If ADC instance sequencer mode is disabled, sequencers of 02480 * all groups (group regular, group injected) can be configured 02481 * but their execution is disabled (limited to rank 1). 02482 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 02483 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 02484 * ADC conversion on only 1 channel. 02485 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength 02486 * @param ADCx ADC instance 02487 * @retval Returned value can be one of the following values: 02488 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 02489 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 02490 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 02491 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 02492 */ 02493 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) 02494 { 02495 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); 02496 } 02497 02498 /** 02499 * @brief Set ADC group injected sequencer discontinuous mode: 02500 * sequence subdivided and scan conversions interrupted every selected 02501 * number of ranks. 02502 * @note It is not possible to enable both ADC group injected 02503 * auto-injected mode and sequencer discontinuous mode. 02504 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont 02505 * @param ADCx ADC instance 02506 * @param SeqDiscont This parameter can be one of the following values: 02507 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 02508 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 02509 * @retval None 02510 */ 02511 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 02512 { 02513 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); 02514 } 02515 02516 /** 02517 * @brief Get ADC group injected sequencer discontinuous mode: 02518 * sequence subdivided and scan conversions interrupted every selected 02519 * number of ranks. 02520 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont 02521 * @param ADCx ADC instance 02522 * @retval Returned value can be one of the following values: 02523 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 02524 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 02525 */ 02526 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) 02527 { 02528 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); 02529 } 02530 02531 /** 02532 * @brief Set ADC group injected sequence: channel on the selected 02533 * sequence rank. 02534 * @note Depending on devices and packages, some channels may not be available. 02535 * Refer to device datasheet for channels availability. 02536 * @note On this STM32 serie, to measure internal channels (VrefInt, 02537 * TempSensor, ...), measurement paths to internal channels must be 02538 * enabled separately. 02539 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 02540 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n 02541 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n 02542 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n 02543 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks 02544 * @param ADCx ADC instance 02545 * @param Rank This parameter can be one of the following values: 02546 * @arg @ref LL_ADC_INJ_RANK_1 02547 * @arg @ref LL_ADC_INJ_RANK_2 02548 * @arg @ref LL_ADC_INJ_RANK_3 02549 * @arg @ref LL_ADC_INJ_RANK_4 02550 * @param Channel This parameter can be one of the following values: 02551 * @arg @ref LL_ADC_CHANNEL_0 02552 * @arg @ref LL_ADC_CHANNEL_1 02553 * @arg @ref LL_ADC_CHANNEL_2 02554 * @arg @ref LL_ADC_CHANNEL_3 02555 * @arg @ref LL_ADC_CHANNEL_4 02556 * @arg @ref LL_ADC_CHANNEL_5 02557 * @arg @ref LL_ADC_CHANNEL_6 02558 * @arg @ref LL_ADC_CHANNEL_7 02559 * @arg @ref LL_ADC_CHANNEL_8 02560 * @arg @ref LL_ADC_CHANNEL_9 02561 * @arg @ref LL_ADC_CHANNEL_10 02562 * @arg @ref LL_ADC_CHANNEL_11 02563 * @arg @ref LL_ADC_CHANNEL_12 02564 * @arg @ref LL_ADC_CHANNEL_13 02565 * @arg @ref LL_ADC_CHANNEL_14 02566 * @arg @ref LL_ADC_CHANNEL_15 02567 * @arg @ref LL_ADC_CHANNEL_16 02568 * @arg @ref LL_ADC_CHANNEL_17 02569 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02570 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 02571 * 02572 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 02573 * @retval None 02574 */ 02575 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 02576 { 02577 /* Set bits with content of parameter "Channel" with bits position */ 02578 /* in register depending on parameter "Rank". */ 02579 /* Parameters "Rank" and "Channel" are used with masks because containing */ 02580 /* other bits reserved for other purpose. */ 02581 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; 02582 02583 MODIFY_REG(ADCx->JSQR, 02584 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))), 02585 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))); 02586 } 02587 02588 /** 02589 * @brief Get ADC group injected sequence: channel on the selected 02590 * sequence rank. 02591 * @note Depending on devices and packages, some channels may not be available. 02592 * Refer to device datasheet for channels availability. 02593 * @note Usage of the returned channel number: 02594 * - To reinject this channel into another function LL_ADC_xxx: 02595 * the returned channel number is only partly formatted on definition 02596 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 02597 * with parts of literals LL_ADC_CHANNEL_x or using 02598 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02599 * Then the selected literal LL_ADC_CHANNEL_x can be used 02600 * as parameter for another function. 02601 * - To get the channel number in decimal format: 02602 * process the returned value with the helper macro 02603 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02604 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n 02605 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n 02606 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n 02607 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks 02608 * @param ADCx ADC instance 02609 * @param Rank This parameter can be one of the following values: 02610 * @arg @ref LL_ADC_INJ_RANK_1 02611 * @arg @ref LL_ADC_INJ_RANK_2 02612 * @arg @ref LL_ADC_INJ_RANK_3 02613 * @arg @ref LL_ADC_INJ_RANK_4 02614 * @retval Returned value can be one of the following values: 02615 * @arg @ref LL_ADC_CHANNEL_0 02616 * @arg @ref LL_ADC_CHANNEL_1 02617 * @arg @ref LL_ADC_CHANNEL_2 02618 * @arg @ref LL_ADC_CHANNEL_3 02619 * @arg @ref LL_ADC_CHANNEL_4 02620 * @arg @ref LL_ADC_CHANNEL_5 02621 * @arg @ref LL_ADC_CHANNEL_6 02622 * @arg @ref LL_ADC_CHANNEL_7 02623 * @arg @ref LL_ADC_CHANNEL_8 02624 * @arg @ref LL_ADC_CHANNEL_9 02625 * @arg @ref LL_ADC_CHANNEL_10 02626 * @arg @ref LL_ADC_CHANNEL_11 02627 * @arg @ref LL_ADC_CHANNEL_12 02628 * @arg @ref LL_ADC_CHANNEL_13 02629 * @arg @ref LL_ADC_CHANNEL_14 02630 * @arg @ref LL_ADC_CHANNEL_15 02631 * @arg @ref LL_ADC_CHANNEL_16 02632 * @arg @ref LL_ADC_CHANNEL_17 02633 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02634 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 02635 * 02636 * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n 02637 * (1) For ADC channel read back from ADC register, 02638 * comparison with internal channel parameter to be done 02639 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 02640 */ 02641 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 02642 { 02643 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; 02644 02645 return (uint32_t)(READ_BIT(ADCx->JSQR, 02646 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))) 02647 >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))) 02648 ); 02649 } 02650 02651 /** 02652 * @brief Set ADC group injected conversion trigger: 02653 * independent or from ADC group regular. 02654 * @note This mode can be used to extend number of data registers 02655 * updated after one ADC conversion trigger and with data 02656 * permanently kept (not erased by successive conversions of scan of 02657 * ADC sequencer ranks), up to 5 data registers: 02658 * 1 data register on ADC group regular, 4 data registers 02659 * on ADC group injected. 02660 * @note If ADC group injected injected trigger source is set to an 02661 * external trigger, this feature must be must be set to 02662 * independent trigger. 02663 * ADC group injected automatic trigger is compliant only with 02664 * group injected trigger source set to SW start, without any 02665 * further action on ADC group injected conversion start or stop: 02666 * in this case, ADC group injected is controlled only 02667 * from ADC group regular. 02668 * @note It is not possible to enable both ADC group injected 02669 * auto-injected mode and sequencer discontinuous mode. 02670 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto 02671 * @param ADCx ADC instance 02672 * @param TrigAuto This parameter can be one of the following values: 02673 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 02674 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 02675 * @retval None 02676 */ 02677 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) 02678 { 02679 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); 02680 } 02681 02682 /** 02683 * @brief Get ADC group injected conversion trigger: 02684 * independent or from ADC group regular. 02685 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto 02686 * @param ADCx ADC instance 02687 * @retval Returned value can be one of the following values: 02688 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 02689 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 02690 */ 02691 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) 02692 { 02693 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); 02694 } 02695 02696 /** 02697 * @brief Set ADC group injected offset. 02698 * @note It sets: 02699 * - ADC group injected rank to which the offset programmed 02700 * will be applied 02701 * - Offset level (offset to be subtracted from the raw 02702 * converted data). 02703 * Caution: Offset format is dependent to ADC resolution: 02704 * offset has to be left-aligned on bit 11, the LSB (right bits) 02705 * are set to 0. 02706 * @note Offset cannot be enabled or disabled. 02707 * To emulate offset disabled, set an offset value equal to 0. 02708 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n 02709 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n 02710 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n 02711 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset 02712 * @param ADCx ADC instance 02713 * @param Rank This parameter can be one of the following values: 02714 * @arg @ref LL_ADC_INJ_RANK_1 02715 * @arg @ref LL_ADC_INJ_RANK_2 02716 * @arg @ref LL_ADC_INJ_RANK_3 02717 * @arg @ref LL_ADC_INJ_RANK_4 02718 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF 02719 * @retval None 02720 */ 02721 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) 02722 { 02723 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); 02724 02725 MODIFY_REG(*preg, 02726 ADC_JOFR1_JOFFSET1, 02727 OffsetLevel); 02728 } 02729 02730 /** 02731 * @brief Get ADC group injected offset. 02732 * @note It gives offset level (offset to be subtracted from the raw converted data). 02733 * Caution: Offset format is dependent to ADC resolution: 02734 * offset has to be left-aligned on bit 11, the LSB (right bits) 02735 * are set to 0. 02736 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n 02737 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n 02738 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n 02739 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset 02740 * @param ADCx ADC instance 02741 * @param Rank This parameter can be one of the following values: 02742 * @arg @ref LL_ADC_INJ_RANK_1 02743 * @arg @ref LL_ADC_INJ_RANK_2 02744 * @arg @ref LL_ADC_INJ_RANK_3 02745 * @arg @ref LL_ADC_INJ_RANK_4 02746 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 02747 */ 02748 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) 02749 { 02750 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); 02751 02752 return (uint32_t)(READ_BIT(*preg, 02753 ADC_JOFR1_JOFFSET1) 02754 ); 02755 } 02756 02757 /** 02758 * @} 02759 */ 02760 02761 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels 02762 * @{ 02763 */ 02764 02765 /** 02766 * @brief Set sampling time of the selected ADC channel 02767 * Unit: ADC clock cycles. 02768 * @note On this device, sampling time is on channel scope: independently 02769 * of channel mapped on ADC group regular or injected. 02770 * @note In case of internal channel (VrefInt, TempSensor, ...) to be 02771 * converted: 02772 * sampling time constraints must be respected (sampling time can be 02773 * adjusted in function of ADC clock frequency and sampling time 02774 * setting). 02775 * Refer to device datasheet for timings values (parameters TS_vrefint, 02776 * TS_temp, ...). 02777 * @note Conversion time is the addition of sampling time and processing time. 02778 * Refer to reference manual for ADC processing time of 02779 * this STM32 serie. 02780 * @note In case of ADC conversion of internal channel (VrefInt, 02781 * temperature sensor, ...), a sampling time minimum value 02782 * is required. 02783 * Refer to device datasheet. 02784 * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n 02785 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n 02786 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n 02787 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n 02788 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n 02789 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n 02790 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n 02791 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n 02792 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n 02793 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n 02794 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n 02795 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n 02796 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n 02797 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n 02798 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n 02799 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n 02800 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n 02801 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime 02802 * @param ADCx ADC instance 02803 * @param Channel This parameter can be one of the following values: 02804 * @arg @ref LL_ADC_CHANNEL_0 02805 * @arg @ref LL_ADC_CHANNEL_1 02806 * @arg @ref LL_ADC_CHANNEL_2 02807 * @arg @ref LL_ADC_CHANNEL_3 02808 * @arg @ref LL_ADC_CHANNEL_4 02809 * @arg @ref LL_ADC_CHANNEL_5 02810 * @arg @ref LL_ADC_CHANNEL_6 02811 * @arg @ref LL_ADC_CHANNEL_7 02812 * @arg @ref LL_ADC_CHANNEL_8 02813 * @arg @ref LL_ADC_CHANNEL_9 02814 * @arg @ref LL_ADC_CHANNEL_10 02815 * @arg @ref LL_ADC_CHANNEL_11 02816 * @arg @ref LL_ADC_CHANNEL_12 02817 * @arg @ref LL_ADC_CHANNEL_13 02818 * @arg @ref LL_ADC_CHANNEL_14 02819 * @arg @ref LL_ADC_CHANNEL_15 02820 * @arg @ref LL_ADC_CHANNEL_16 02821 * @arg @ref LL_ADC_CHANNEL_17 02822 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02823 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 02824 * 02825 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 02826 * @param SamplingTime This parameter can be one of the following values: 02827 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 02828 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 02829 * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 02830 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 02831 * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 02832 * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5 02833 * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 02834 * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 02835 * @retval None 02836 */ 02837 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) 02838 { 02839 /* Set bits with content of parameter "SamplingTime" with bits position */ 02840 /* in register and register position depending on parameter "Channel". */ 02841 /* Parameter "Channel" is used with masks because containing */ 02842 /* other bits reserved for other purpose. */ 02843 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 02844 02845 MODIFY_REG(*preg, 02846 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), 02847 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); 02848 } 02849 02850 /** 02851 * @brief Get sampling time of the selected ADC channel 02852 * Unit: ADC clock cycles. 02853 * @note On this device, sampling time is on channel scope: independently 02854 * of channel mapped on ADC group regular or injected. 02855 * @note Conversion time is the addition of sampling time and processing time. 02856 * Refer to reference manual for ADC processing time of 02857 * this STM32 serie. 02858 * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n 02859 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n 02860 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n 02861 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n 02862 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n 02863 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n 02864 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n 02865 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n 02866 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n 02867 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n 02868 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n 02869 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n 02870 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n 02871 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n 02872 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n 02873 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n 02874 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n 02875 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime 02876 * @param ADCx ADC instance 02877 * @param Channel This parameter can be one of the following values: 02878 * @arg @ref LL_ADC_CHANNEL_0 02879 * @arg @ref LL_ADC_CHANNEL_1 02880 * @arg @ref LL_ADC_CHANNEL_2 02881 * @arg @ref LL_ADC_CHANNEL_3 02882 * @arg @ref LL_ADC_CHANNEL_4 02883 * @arg @ref LL_ADC_CHANNEL_5 02884 * @arg @ref LL_ADC_CHANNEL_6 02885 * @arg @ref LL_ADC_CHANNEL_7 02886 * @arg @ref LL_ADC_CHANNEL_8 02887 * @arg @ref LL_ADC_CHANNEL_9 02888 * @arg @ref LL_ADC_CHANNEL_10 02889 * @arg @ref LL_ADC_CHANNEL_11 02890 * @arg @ref LL_ADC_CHANNEL_12 02891 * @arg @ref LL_ADC_CHANNEL_13 02892 * @arg @ref LL_ADC_CHANNEL_14 02893 * @arg @ref LL_ADC_CHANNEL_15 02894 * @arg @ref LL_ADC_CHANNEL_16 02895 * @arg @ref LL_ADC_CHANNEL_17 02896 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02897 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 02898 * 02899 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 02900 * @retval Returned value can be one of the following values: 02901 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 02902 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 02903 * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 02904 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 02905 * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 02906 * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5 02907 * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 02908 * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 02909 */ 02910 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) 02911 { 02912 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 02913 02914 return (uint32_t)(READ_BIT(*preg, 02915 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) 02916 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) 02917 ); 02918 } 02919 02920 /** 02921 * @} 02922 */ 02923 02924 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog 02925 * @{ 02926 */ 02927 02928 /** 02929 * @brief Set ADC analog watchdog monitored channels: 02930 * a single channel or all channels, 02931 * on ADC groups regular and-or injected. 02932 * @note Once monitored channels are selected, analog watchdog 02933 * is enabled. 02934 * @note In case of need to define a single channel to monitor 02935 * with analog watchdog from sequencer channel definition, 02936 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). 02937 * @note On this STM32 serie, there is only 1 kind of analog watchdog 02938 * instance: 02939 * - AWD standard (instance AWD1): 02940 * - channels monitored: can monitor 1 channel or all channels. 02941 * - groups monitored: ADC groups regular and-or injected. 02942 * - resolution: resolution is not limited (corresponds to 02943 * ADC resolution configured). 02944 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n 02945 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n 02946 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels 02947 * @param ADCx ADC instance 02948 * @param AWDChannelGroup This parameter can be one of the following values: 02949 * @arg @ref LL_ADC_AWD_DISABLE 02950 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 02951 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 02952 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 02953 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 02954 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 02955 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 02956 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 02957 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 02958 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 02959 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 02960 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 02961 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 02962 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 02963 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 02964 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 02965 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 02966 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 02967 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 02968 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 02969 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 02970 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 02971 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 02972 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 02973 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 02974 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 02975 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 02976 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 02977 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 02978 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 02979 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 02980 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 02981 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 02982 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 02983 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 02984 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 02985 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 02986 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 02987 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 02988 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 02989 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 02990 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 02991 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 02992 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 02993 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 02994 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 02995 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 02996 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 02997 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 02998 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 02999 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 03000 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 03001 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 03002 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 03003 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 03004 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 03005 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 03006 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 03007 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) 03008 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) 03009 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 03010 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1) 03011 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1) 03012 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) 03013 * 03014 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 03015 * @retval None 03016 */ 03017 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) 03018 { 03019 MODIFY_REG(ADCx->CR1, 03020 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), 03021 AWDChannelGroup); 03022 } 03023 03024 /** 03025 * @brief Get ADC analog watchdog monitored channel. 03026 * @note Usage of the returned channel number: 03027 * - To reinject this channel into another function LL_ADC_xxx: 03028 * the returned channel number is only partly formatted on definition 03029 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 03030 * with parts of literals LL_ADC_CHANNEL_x or using 03031 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 03032 * Then the selected literal LL_ADC_CHANNEL_x can be used 03033 * as parameter for another function. 03034 * - To get the channel number in decimal format: 03035 * process the returned value with the helper macro 03036 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 03037 * Applicable only when the analog watchdog is set to monitor 03038 * one channel. 03039 * @note On this STM32 serie, there is only 1 kind of analog watchdog 03040 * instance: 03041 * - AWD standard (instance AWD1): 03042 * - channels monitored: can monitor 1 channel or all channels. 03043 * - groups monitored: ADC groups regular and-or injected. 03044 * - resolution: resolution is not limited (corresponds to 03045 * ADC resolution configured). 03046 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n 03047 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n 03048 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels 03049 * @param ADCx ADC instance 03050 * @retval Returned value can be one of the following values: 03051 * @arg @ref LL_ADC_AWD_DISABLE 03052 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 03053 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 03054 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 03055 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 03056 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 03057 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 03058 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 03059 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 03060 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 03061 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 03062 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 03063 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 03064 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 03065 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 03066 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 03067 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 03068 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 03069 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 03070 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 03071 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 03072 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 03073 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 03074 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 03075 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 03076 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 03077 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 03078 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 03079 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 03080 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 03081 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 03082 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 03083 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 03084 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 03085 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 03086 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 03087 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 03088 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 03089 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 03090 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 03091 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 03092 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 03093 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 03094 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 03095 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 03096 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 03097 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 03098 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 03099 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 03100 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 03101 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 03102 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 03103 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 03104 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 03105 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 03106 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 03107 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 03108 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 03109 */ 03110 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) 03111 { 03112 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); 03113 } 03114 03115 /** 03116 * @brief Set ADC analog watchdog threshold value of threshold 03117 * high or low. 03118 * @note On this STM32 serie, there is only 1 kind of analog watchdog 03119 * instance: 03120 * - AWD standard (instance AWD1): 03121 * - channels monitored: can monitor 1 channel or all channels. 03122 * - groups monitored: ADC groups regular and-or injected. 03123 * - resolution: resolution is not limited (corresponds to 03124 * ADC resolution configured). 03125 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n 03126 * LTR LT LL_ADC_SetAnalogWDThresholds 03127 * @param ADCx ADC instance 03128 * @param AWDThresholdsHighLow This parameter can be one of the following values: 03129 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 03130 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 03131 * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF 03132 * @retval None 03133 */ 03134 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) 03135 { 03136 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); 03137 03138 MODIFY_REG(*preg, 03139 ADC_HTR_HT, 03140 AWDThresholdValue); 03141 } 03142 03143 /** 03144 * @brief Get ADC analog watchdog threshold value of threshold high or 03145 * threshold low. 03146 * @note In case of ADC resolution different of 12 bits, 03147 * analog watchdog thresholds data require a specific shift. 03148 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). 03149 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n 03150 * LTR LT LL_ADC_GetAnalogWDThresholds 03151 * @param ADCx ADC instance 03152 * @param AWDThresholdsHighLow This parameter can be one of the following values: 03153 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 03154 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 03155 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 03156 */ 03157 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) 03158 { 03159 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); 03160 03161 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); 03162 } 03163 03164 /** 03165 * @} 03166 */ 03167 03168 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode 03169 * @{ 03170 */ 03171 03172 #if defined(ADC_MULTIMODE_SUPPORT) 03173 /** 03174 * @brief Set ADC multimode configuration to operate in independent mode 03175 * or multimode (for devices with several ADC instances). 03176 * @note If multimode configuration: the selected ADC instance is 03177 * either master or slave depending on hardware. 03178 * Refer to reference manual. 03179 * @rmtoll CR1 DUALMOD LL_ADC_SetMultimode 03180 * @param ADCxy_COMMON ADC common instance 03181 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03182 * @param Multimode This parameter can be one of the following values: 03183 * @arg @ref LL_ADC_MULTI_INDEPENDENT 03184 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 03185 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST 03186 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW 03187 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 03188 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 03189 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 03190 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 03191 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM 03192 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM 03193 * @retval None 03194 */ 03195 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) 03196 { 03197 MODIFY_REG(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD, Multimode); 03198 } 03199 03200 /** 03201 * @brief Get ADC multimode configuration to operate in independent mode 03202 * or multimode (for devices with several ADC instances). 03203 * @note If multimode configuration: the selected ADC instance is 03204 * either master or slave depending on hardware. 03205 * Refer to reference manual. 03206 * @rmtoll CR1 DUALMOD LL_ADC_GetMultimode 03207 * @param ADCxy_COMMON ADC common instance 03208 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03209 * @retval Returned value can be one of the following values: 03210 * @arg @ref LL_ADC_MULTI_INDEPENDENT 03211 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 03212 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST 03213 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW 03214 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 03215 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 03216 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 03217 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 03218 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM 03219 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM 03220 */ 03221 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) 03222 { 03223 return (uint32_t)(READ_BIT(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD)); 03224 } 03225 03226 #endif /* ADC_MULTIMODE_SUPPORT */ 03227 03228 /** 03229 * @} 03230 */ 03231 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance 03232 * @{ 03233 */ 03234 03235 /** 03236 * @brief Enable the selected ADC instance. 03237 * @note On this STM32 serie, after ADC enable, a delay for 03238 * ADC internal analog stabilization is required before performing a 03239 * ADC conversion start. 03240 * Refer to device datasheet, parameter tSTAB. 03241 * @rmtoll CR2 ADON LL_ADC_Enable 03242 * @param ADCx ADC instance 03243 * @retval None 03244 */ 03245 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) 03246 { 03247 SET_BIT(ADCx->CR2, ADC_CR2_ADON); 03248 } 03249 03250 /** 03251 * @brief Disable the selected ADC instance. 03252 * @rmtoll CR2 ADON LL_ADC_Disable 03253 * @param ADCx ADC instance 03254 * @retval None 03255 */ 03256 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) 03257 { 03258 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); 03259 } 03260 03261 /** 03262 * @brief Get the selected ADC instance enable state. 03263 * @rmtoll CR2 ADON LL_ADC_IsEnabled 03264 * @param ADCx ADC instance 03265 * @retval 0: ADC is disabled, 1: ADC is enabled. 03266 */ 03267 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) 03268 { 03269 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); 03270 } 03271 03272 /** 03273 * @brief Start ADC calibration in the mode single-ended 03274 * or differential (for devices with differential mode available). 03275 * @note On this STM32 serie, before starting a calibration, 03276 * ADC must be disabled. 03277 * A minimum number of ADC clock cycles are required 03278 * between ADC disable state and calibration start. 03279 * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES. 03280 * @note On this STM32 serie, hardware prerequisite before starting a calibration: 03281 the ADC must have been in power-on state for at least 03282 two ADC clock cycles. 03283 * @rmtoll CR2 CAL LL_ADC_StartCalibration 03284 * @param ADCx ADC instance 03285 * @retval None 03286 */ 03287 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) 03288 { 03289 SET_BIT(ADCx->CR2, ADC_CR2_CAL); 03290 } 03291 03292 /** 03293 * @brief Get ADC calibration state. 03294 * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing 03295 * @param ADCx ADC instance 03296 * @retval 0: calibration complete, 1: calibration in progress. 03297 */ 03298 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) 03299 { 03300 return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL)); 03301 } 03302 03303 /** 03304 * @} 03305 */ 03306 03307 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular 03308 * @{ 03309 */ 03310 03311 /** 03312 * @brief Start ADC group regular conversion. 03313 * @note On this STM32 serie, this function is relevant only for 03314 * internal trigger (SW start), not for external trigger: 03315 * - If ADC trigger has been set to software start, ADC conversion 03316 * starts immediately. 03317 * - If ADC trigger has been set to external trigger, ADC conversion 03318 * start must be performed using function 03319 * @ref LL_ADC_REG_StartConversionExtTrig(). 03320 * (if external trigger edge would have been set during ADC other 03321 * settings, ADC conversion would start at trigger event 03322 * as soon as ADC is enabled). 03323 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart 03324 * @param ADCx ADC instance 03325 * @retval None 03326 */ 03327 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) 03328 { 03329 SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 03330 } 03331 03332 /** 03333 * @brief Start ADC group regular conversion from external trigger. 03334 * @note ADC conversion will start at next trigger event (on the selected 03335 * trigger edge) following the ADC start conversion command. 03336 * @note On this STM32 serie, this function is relevant for 03337 * ADC conversion start from external trigger. 03338 * If internal trigger (SW start) is needed, perform ADC conversion 03339 * start using function @ref LL_ADC_REG_StartConversionSWStart(). 03340 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig 03341 * @param ExternalTriggerEdge This parameter can be one of the following values: 03342 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING 03343 * @param ADCx ADC instance 03344 * @retval None 03345 */ 03346 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 03347 { 03348 SET_BIT(ADCx->CR2, ExternalTriggerEdge); 03349 } 03350 03351 /** 03352 * @brief Stop ADC group regular conversion from external trigger. 03353 * @note No more ADC conversion will start at next trigger event 03354 * following the ADC stop conversion command. 03355 * If a conversion is on-going, it will be completed. 03356 * @note On this STM32 serie, there is no specific command 03357 * to stop a conversion on-going or to stop ADC converting 03358 * in continuous mode. These actions can be performed 03359 * using function @ref LL_ADC_Disable(). 03360 * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig 03361 * @param ADCx ADC instance 03362 * @retval None 03363 */ 03364 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) 03365 { 03366 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTTRIG); 03367 } 03368 03369 /** 03370 * @brief Get ADC group regular conversion data, range fit for 03371 * all ADC configurations: all ADC resolutions and 03372 * all oversampling increased data width (for devices 03373 * with feature oversampling). 03374 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 03375 * @param ADCx ADC instance 03376 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 03377 */ 03378 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) 03379 { 03380 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 03381 } 03382 03383 /** 03384 * @brief Get ADC group regular conversion data, range fit for 03385 * ADC resolution 12 bits. 03386 * @note For devices with feature oversampling: Oversampling 03387 * can increase data width, function for extended range 03388 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 03389 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 03390 * @param ADCx ADC instance 03391 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 03392 */ 03393 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) 03394 { 03395 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 03396 } 03397 03398 #if defined(ADC_MULTIMODE_SUPPORT) 03399 /** 03400 * @brief Get ADC multimode conversion data of ADC master, ADC slave 03401 * or raw data with ADC master and slave concatenated. 03402 * @note If raw data with ADC master and slave concatenated is retrieved, 03403 * a macro is available to get the conversion data of 03404 * ADC master or ADC slave: see helper macro 03405 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 03406 * (however this macro is mainly intended for multimode 03407 * transfer by DMA, because this function can do the same 03408 * by getting multimode conversion data of ADC master or ADC slave 03409 * separately). 03410 * @rmtoll DR DATA LL_ADC_REG_ReadMultiConversionData32\n 03411 * DR ADC2DATA LL_ADC_REG_ReadMultiConversionData32 03412 * @param ADCx ADC instance 03413 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03414 * @param ConversionData This parameter can be one of the following values: 03415 * @arg @ref LL_ADC_MULTI_MASTER 03416 * @arg @ref LL_ADC_MULTI_SLAVE 03417 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE 03418 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 03419 */ 03420 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_TypeDef *ADCx, uint32_t ConversionData) 03421 { 03422 return (uint32_t)(READ_BIT(ADCx->DR, 03423 ADC_DR_ADC2DATA) 03424 >> POSITION_VAL(ConversionData) 03425 ); 03426 } 03427 #endif /* ADC_MULTIMODE_SUPPORT */ 03428 03429 /** 03430 * @} 03431 */ 03432 03433 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected 03434 * @{ 03435 */ 03436 03437 /** 03438 * @brief Start ADC group injected conversion. 03439 * @note On this STM32 serie, this function is relevant only for 03440 * internal trigger (SW start), not for external trigger: 03441 * - If ADC trigger has been set to software start, ADC conversion 03442 * starts immediately. 03443 * - If ADC trigger has been set to external trigger, ADC conversion 03444 * start must be performed using function 03445 * @ref LL_ADC_INJ_StartConversionExtTrig(). 03446 * (if external trigger edge would have been set during ADC other 03447 * settings, ADC conversion would start at trigger event 03448 * as soon as ADC is enabled). 03449 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart 03450 * @param ADCx ADC instance 03451 * @retval None 03452 */ 03453 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) 03454 { 03455 SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); 03456 } 03457 03458 /** 03459 * @brief Start ADC group injected conversion from external trigger. 03460 * @note ADC conversion will start at next trigger event (on the selected 03461 * trigger edge) following the ADC start conversion command. 03462 * @note On this STM32 serie, this function is relevant for 03463 * ADC conversion start from external trigger. 03464 * If internal trigger (SW start) is needed, perform ADC conversion 03465 * start using function @ref LL_ADC_INJ_StartConversionSWStart(). 03466 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig 03467 * @param ExternalTriggerEdge This parameter can be one of the following values: 03468 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 03469 * @param ADCx ADC instance 03470 * @retval None 03471 */ 03472 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 03473 { 03474 SET_BIT(ADCx->CR2, ExternalTriggerEdge); 03475 } 03476 03477 /** 03478 * @brief Stop ADC group injected conversion from external trigger. 03479 * @note No more ADC conversion will start at next trigger event 03480 * following the ADC stop conversion command. 03481 * If a conversion is on-going, it will be completed. 03482 * @note On this STM32 serie, there is no specific command 03483 * to stop a conversion on-going or to stop ADC converting 03484 * in continuous mode. These actions can be performed 03485 * using function @ref LL_ADC_Disable(). 03486 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig 03487 * @param ADCx ADC instance 03488 * @retval None 03489 */ 03490 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) 03491 { 03492 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTTRIG); 03493 } 03494 03495 /** 03496 * @brief Get ADC group regular conversion data, range fit for 03497 * all ADC configurations: all ADC resolutions and 03498 * all oversampling increased data width (for devices 03499 * with feature oversampling). 03500 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n 03501 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n 03502 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n 03503 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 03504 * @param ADCx ADC instance 03505 * @param Rank This parameter can be one of the following values: 03506 * @arg @ref LL_ADC_INJ_RANK_1 03507 * @arg @ref LL_ADC_INJ_RANK_2 03508 * @arg @ref LL_ADC_INJ_RANK_3 03509 * @arg @ref LL_ADC_INJ_RANK_4 03510 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 03511 */ 03512 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) 03513 { 03514 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 03515 03516 return (uint32_t)(READ_BIT(*preg, 03517 ADC_JDR1_JDATA) 03518 ); 03519 } 03520 03521 /** 03522 * @brief Get ADC group injected conversion data, range fit for 03523 * ADC resolution 12 bits. 03524 * @note For devices with feature oversampling: Oversampling 03525 * can increase data width, function for extended range 03526 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 03527 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n 03528 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n 03529 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n 03530 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 03531 * @param ADCx ADC instance 03532 * @param Rank This parameter can be one of the following values: 03533 * @arg @ref LL_ADC_INJ_RANK_1 03534 * @arg @ref LL_ADC_INJ_RANK_2 03535 * @arg @ref LL_ADC_INJ_RANK_3 03536 * @arg @ref LL_ADC_INJ_RANK_4 03537 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 03538 */ 03539 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) 03540 { 03541 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 03542 03543 return (uint16_t)(READ_BIT(*preg, 03544 ADC_JDR1_JDATA) 03545 ); 03546 } 03547 03548 /** 03549 * @} 03550 */ 03551 03552 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management 03553 * @{ 03554 */ 03555 03556 /** 03557 * @brief Get flag ADC group regular end of sequence conversions. 03558 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS 03559 * @param ADCx ADC instance 03560 * @retval State of bit (1 or 0). 03561 */ 03562 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) 03563 { 03564 /* Note: on this STM32 serie, there is no flag ADC group regular */ 03565 /* end of unitary conversion. */ 03566 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 03567 /* in other STM32 families). */ 03568 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); 03569 } 03570 03571 03572 /** 03573 * @brief Get flag ADC group injected end of sequence conversions. 03574 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS 03575 * @param ADCx ADC instance 03576 * @retval State of bit (1 or 0). 03577 */ 03578 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) 03579 { 03580 /* Note: on this STM32 serie, there is no flag ADC group injected */ 03581 /* end of unitary conversion. */ 03582 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 03583 /* in other STM32 families). */ 03584 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); 03585 } 03586 03587 /** 03588 * @brief Get flag ADC analog watchdog 1 flag 03589 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 03590 * @param ADCx ADC instance 03591 * @retval State of bit (1 or 0). 03592 */ 03593 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) 03594 { 03595 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); 03596 } 03597 03598 /** 03599 * @brief Clear flag ADC group regular end of sequence conversions. 03600 * @rmtoll SR EOC LL_ADC_ClearFlag_EOS 03601 * @param ADCx ADC instance 03602 * @retval None 03603 */ 03604 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) 03605 { 03606 /* Note: on this STM32 serie, there is no flag ADC group regular */ 03607 /* end of unitary conversion. */ 03608 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 03609 /* in other STM32 families). */ 03610 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS); 03611 } 03612 03613 03614 /** 03615 * @brief Clear flag ADC group injected end of sequence conversions. 03616 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS 03617 * @param ADCx ADC instance 03618 * @retval None 03619 */ 03620 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) 03621 { 03622 /* Note: on this STM32 serie, there is no flag ADC group injected */ 03623 /* end of unitary conversion. */ 03624 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 03625 /* in other STM32 families). */ 03626 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); 03627 } 03628 03629 /** 03630 * @brief Clear flag ADC analog watchdog 1. 03631 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 03632 * @param ADCx ADC instance 03633 * @retval None 03634 */ 03635 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) 03636 { 03637 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); 03638 } 03639 03640 #if defined(ADC_MULTIMODE_SUPPORT) 03641 /** 03642 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master. 03643 * @rmtoll SR EOC LL_ADC_IsActiveFlag_MST_EOS 03644 * @param ADCxy_COMMON ADC common instance 03645 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03646 * @retval State of bit (1 or 0). 03647 */ 03648 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) 03649 { 03650 /* Note: on this STM32 serie, there is no flag ADC group regular */ 03651 /* end of unitary conversion. */ 03652 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 03653 /* in other STM32 families). */ 03654 return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_EOC) == (ADC_SR_EOC)); 03655 } 03656 03657 /** 03658 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave. 03659 * @rmtoll SR EOC LL_ADC_IsActiveFlag_SLV_EOS 03660 * @param ADCxy_COMMON ADC common instance 03661 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03662 * @retval State of bit (1 or 0). 03663 */ 03664 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) 03665 { 03666 /* Note: on this STM32 serie, there is no flag ADC group regular */ 03667 /* end of unitary conversion. */ 03668 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 03669 /* in other STM32 families). */ 03670 03671 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); 03672 03673 return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)); 03674 } 03675 03676 03677 /** 03678 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. 03679 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_MST_JEOS 03680 * @param ADCxy_COMMON ADC common instance 03681 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03682 * @retval State of bit (1 or 0). 03683 */ 03684 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 03685 { 03686 /* Note: on this STM32 serie, there is no flag ADC group injected */ 03687 /* end of unitary conversion. */ 03688 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 03689 /* in other STM32 families). */ 03690 return (READ_BIT(ADC1->SR, ADC_SR_JEOC) == (ADC_SR_JEOC)); 03691 } 03692 03693 /** 03694 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave. 03695 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_SLV_JEOS 03696 * @param ADCxy_COMMON ADC common instance 03697 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03698 * @retval State of bit (1 or 0). 03699 */ 03700 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 03701 { 03702 /* Note: on this STM32 serie, there is no flag ADC group injected */ 03703 /* end of unitary conversion. */ 03704 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 03705 /* in other STM32 families). */ 03706 03707 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); 03708 03709 return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)); 03710 } 03711 03712 /** 03713 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. 03714 * @rmtoll SR AWD LL_ADC_IsActiveFlag_MST_AWD1 03715 * @param ADCxy_COMMON ADC common instance 03716 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03717 * @retval State of bit (1 or 0). 03718 */ 03719 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 03720 { 03721 return (READ_BIT(ADC1->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); 03722 } 03723 03724 /** 03725 * @brief Get flag multimode analog watchdog 1 of the ADC slave. 03726 * @rmtoll SR AWD LL_ADC_IsActiveFlag_SLV_AWD1 03727 * @param ADCxy_COMMON ADC common instance 03728 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03729 * @retval State of bit (1 or 0). 03730 */ 03731 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 03732 { 03733 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); 03734 03735 return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); 03736 } 03737 03738 #endif /* ADC_MULTIMODE_SUPPORT */ 03739 03740 /** 03741 * @} 03742 */ 03743 03744 /** @defgroup ADC_LL_EF_IT_Management ADC IT management 03745 * @{ 03746 */ 03747 03748 /** 03749 * @brief Enable interruption ADC group regular end of sequence conversions. 03750 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS 03751 * @param ADCx ADC instance 03752 * @retval None 03753 */ 03754 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) 03755 { 03756 /* Note: on this STM32 serie, there is no flag ADC group regular */ 03757 /* end of unitary conversion. */ 03758 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 03759 /* in other STM32 families). */ 03760 SET_BIT(ADCx->CR1, ADC_CR1_EOCIE); 03761 } 03762 03763 03764 /** 03765 * @brief Enable interruption ADC group injected end of sequence conversions. 03766 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 03767 * @param ADCx ADC instance 03768 * @retval None 03769 */ 03770 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) 03771 { 03772 /* Note: on this STM32 serie, there is no flag ADC group injected */ 03773 /* end of unitary conversion. */ 03774 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 03775 /* in other STM32 families). */ 03776 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); 03777 } 03778 03779 /** 03780 * @brief Enable interruption ADC analog watchdog 1. 03781 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 03782 * @param ADCx ADC instance 03783 * @retval None 03784 */ 03785 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) 03786 { 03787 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); 03788 } 03789 03790 /** 03791 * @brief Disable interruption ADC group regular end of sequence conversions. 03792 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS 03793 * @param ADCx ADC instance 03794 * @retval None 03795 */ 03796 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) 03797 { 03798 /* Note: on this STM32 serie, there is no flag ADC group regular */ 03799 /* end of unitary conversion. */ 03800 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 03801 /* in other STM32 families). */ 03802 CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE); 03803 } 03804 03805 03806 /** 03807 * @brief Disable interruption ADC group injected end of sequence conversions. 03808 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 03809 * @param ADCx ADC instance 03810 * @retval None 03811 */ 03812 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) 03813 { 03814 /* Note: on this STM32 serie, there is no flag ADC group injected */ 03815 /* end of unitary conversion. */ 03816 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 03817 /* in other STM32 families). */ 03818 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); 03819 } 03820 03821 /** 03822 * @brief Disable interruption ADC analog watchdog 1. 03823 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 03824 * @param ADCx ADC instance 03825 * @retval None 03826 */ 03827 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) 03828 { 03829 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); 03830 } 03831 03832 /** 03833 * @brief Get state of interruption ADC group regular end of sequence conversions 03834 * (0: interrupt disabled, 1: interrupt enabled). 03835 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS 03836 * @param ADCx ADC instance 03837 * @retval State of bit (1 or 0). 03838 */ 03839 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) 03840 { 03841 /* Note: on this STM32 serie, there is no flag ADC group regular */ 03842 /* end of unitary conversion. */ 03843 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 03844 /* in other STM32 families). */ 03845 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); 03846 } 03847 03848 03849 /** 03850 * @brief Get state of interruption ADC group injected end of sequence conversions 03851 * (0: interrupt disabled, 1: interrupt enabled). 03852 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 03853 * @param ADCx ADC instance 03854 * @retval State of bit (1 or 0). 03855 */ 03856 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) 03857 { 03858 /* Note: on this STM32 serie, there is no flag ADC group injected */ 03859 /* end of unitary conversion. */ 03860 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 03861 /* in other STM32 families). */ 03862 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); 03863 } 03864 03865 /** 03866 * @brief Get state of interruption ADC analog watchdog 1 03867 * (0: interrupt disabled, 1: interrupt enabled). 03868 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 03869 * @param ADCx ADC instance 03870 * @retval State of bit (1 or 0). 03871 */ 03872 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) 03873 { 03874 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); 03875 } 03876 03877 /** 03878 * @} 03879 */ 03880 03881 #if defined(USE_FULL_LL_DRIVER) 03882 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions 03883 * @{ 03884 */ 03885 03886 /* Initialization of some features of ADC common parameters and multimode */ 03887 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); 03888 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 03889 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 03890 03891 /* De-initialization of ADC instance, ADC group regular and ADC group injected */ 03892 /* (availability of ADC group injected depends on STM32 families) */ 03893 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); 03894 03895 /* Initialization of some features of ADC instance */ 03896 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); 03897 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); 03898 03899 /* Initialization of some features of ADC instance and ADC group regular */ 03900 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 03901 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 03902 03903 /* Initialization of some features of ADC instance and ADC group injected */ 03904 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 03905 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 03906 03907 /** 03908 * @} 03909 */ 03910 #endif /* USE_FULL_LL_DRIVER */ 03911 03912 /** 03913 * @} 03914 */ 03915 03916 /** 03917 * @} 03918 */ 03919 03920 #endif /* ADC1 || ADC2 || ADC3 */ 03921 03922 /** 03923 * @} 03924 */ 03925 03926 #ifdef __cplusplus 03927 } 03928 #endif 03929 03930 #endif /* __STM32F1xx_LL_ADC_H */ 03931 03932 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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