STM32F103xB HAL User Manual
Defines
ADC group regular - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define LL_ADC_REG_SEQ_DISCONT_DISABLE   0x00000000U
#define LL_ADC_REG_SEQ_DISCONT_1RANK   ( ADC_CR1_DISCEN)
#define LL_ADC_REG_SEQ_DISCONT_2RANKS   ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define LL_ADC_REG_SEQ_DISCONT_3RANKS   ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)
#define LL_ADC_REG_SEQ_DISCONT_4RANKS   ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define LL_ADC_REG_SEQ_DISCONT_5RANKS   (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN)
#define LL_ADC_REG_SEQ_DISCONT_6RANKS   (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define LL_ADC_REG_SEQ_DISCONT_7RANKS   (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)
#define LL_ADC_REG_SEQ_DISCONT_8RANKS   (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

Define Documentation

#define LL_ADC_REG_SEQ_DISCONT_1RANK   ( ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 617 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_2RANKS   ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks

Definition at line 618 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_3RANKS   ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks

Definition at line 619 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_4RANKS   ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks

Definition at line 620 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_5RANKS   (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks

Definition at line 621 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_6RANKS   (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks

Definition at line 622 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_7RANKS   (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks

Definition at line 623 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_8RANKS   (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks

Definition at line 624 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_DISABLE   0x00000000U

ADC group regular sequencer discontinuous mode disable

Definition at line 616 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().