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STM32F103xB HAL User Manual
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Modules | |
| ADC range verification | |
For a unique ADC resolution: 12 bits. | |
| ADC regular nb conv verification | |
| ADC regular discontinuous mode number verification | |
Defines | |
| #define | ADC_IS_ENABLE(__HANDLE__) |
| Verification of ADC state: enabled or disabled. | |
| #define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) |
| Test if conversion trigger of regular group is software start or external trigger. | |
| #define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) |
| Test if conversion trigger of injected group is software start or external trigger. | |
| #define | ADC_STATE_CLR_SET MODIFY_REG |
| Simultaneously clears and sets specific bits of the handle State. | |
| #define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) |
| Clear ADC error code (set it to error code: "no error") | |
| #define | ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos) |
| Set ADC number of conversions into regular channel sequence length. | |
| #define | ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10))) |
| Set the ADC's sample time for channel numbers between 10 and 18. | |
| #define | ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_))) |
| Set the ADC's sample time for channel numbers between 0 and 9. | |
| #define | ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1))) |
| Set the selected regular channel rank for rank between 1 and 6. | |
| #define | ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7))) |
| Set the selected regular channel rank for rank between 7 and 12. | |
| #define | ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13))) |
| Set the selected regular channel rank for rank between 13 and 16. | |
| #define | ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos) |
| Set the injected sequence length. | |
| #define | ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) |
| Set the selected injected channel rank Note: on STM32F1 devices, channel rank position in JSQR register is depending on total number of ranks selected into injected sequencer (ranks sequence starting from 4-JL) | |
| #define | ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos) |
| Enable ADC continuous conversion mode. | |
| #define | ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos) |
| Configures the number of discontinuous conversions for the regular group channels. | |
| #define | ADC_CR1_SCAN_SET(_SCAN_MODE_) |
| Enable ADC scan mode to convert multiple ranks with sequencer. | |
| #define | ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) |
| Get the maximum ADC conversion cycles on all channels. | |
| #define | IS_ADC_DATA_ALIGN(ALIGN) |
| #define | IS_ADC_SCAN_MODE(SCAN_MODE) |
| #define | IS_ADC_EXTTRIG_EDGE(EDGE) |
| #define | IS_ADC_CHANNEL(CHANNEL) |
| #define | IS_ADC_SAMPLE_TIME(TIME) |
| #define | IS_ADC_REGULAR_RANK(CHANNEL) |
| #define | IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) |
| #define | IS_ADC_CONVERSION_GROUP(CONVERSION) |
| #define | IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) |
| #define ADC_CLEAR_ERRORCODE | ( | __HANDLE__ | ) | ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) |
Clear ADC error code (set it to error code: "no error")
| __HANDLE__,: | ADC handle |
| None |
Definition at line 656 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().
| #define ADC_CONVCYCLES_MAX_RANGE | ( | __HANDLE__ | ) |
(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ \ (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ : \ ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \ )
Get the maximum ADC conversion cycles on all channels.
Returns the selected sampling time + conversion time (12.5 ADC clock cycles) Approximation of sampling time within 4 ranges, returns the highest value: below 7.5 cycles {1.5 cycle; 7.5 cycles}, between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} equal to 239.5 cycles Unit: ADC clock cycles
| __HANDLE__,: | ADC handle |
| ADC | conversion cycles on all channels |
Definition at line 773 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_PollForConversion(), and HAL_ADCEx_InjectedPollForConversion().
| #define ADC_CR1_DISCONTINUOUS_NUM | ( | _NBR_DISCONTINUOUS_CONV_ | ) | (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos) |
Configures the number of discontinuous conversions for the regular group channels.
| _NBR_DISCONTINUOUS_CONV_,: | Number of discontinuous conversions. |
| None |
Definition at line 746 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_Init().
| #define ADC_CR1_SCAN_SET | ( | _SCAN_MODE_ | ) |
(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ )
Enable ADC scan mode to convert multiple ranks with sequencer.
| _SCAN_MODE_,: | Scan conversion mode. |
| None |
Definition at line 756 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_Init().
| #define ADC_CR2_CONTINUOUS | ( | _CONTINUOUS_MODE_ | ) | ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos) |
Enable ADC continuous conversion mode.
| _CONTINUOUS_MODE_,: | Continuous mode. |
| None |
Definition at line 738 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_Init().
| #define ADC_IS_ENABLE | ( | __HANDLE__ | ) |
((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \ ) ? SET : RESET)
Verification of ADC state: enabled or disabled.
| __HANDLE__,: | ADC handle |
| SET | (ADC enabled) or RESET (ADC disabled) |
Definition at line 620 of file stm32f1xx_hal_adc.h.
Referenced by ADC_ConversionStop_Disable(), ADC_Enable(), HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_MultiModeConfigChannel().
| #define ADC_IS_SOFTWARE_START_INJECTED | ( | __HANDLE__ | ) | (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) |
Test if conversion trigger of injected group is software start or external trigger.
| __HANDLE__,: | ADC handle |
| SET | (software start) or RESET (external trigger) |
Definition at line 639 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().
| #define ADC_IS_SOFTWARE_START_REGULAR | ( | __HANDLE__ | ) | (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) |
Test if conversion trigger of regular group is software start or external trigger.
| __HANDLE__,: | ADC handle |
| SET | (software start) or RESET (external trigger) |
Definition at line 630 of file stm32f1xx_hal_adc.h.
Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().
| #define ADC_JSQR_JL_SHIFT | ( | _JSQR_JL_ | ) | (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos) |
Set the injected sequence length.
| _JSQR_JL_,: | Sequence length. |
| None |
Definition at line 717 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADCEx_InjectedConfigChannel().
| #define ADC_JSQR_RK_JL | ( | _CHANNELNB_, | |
| _RANKNB_, | |||
| _JSQR_JL_ | |||
| ) | ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) |
Set the selected injected channel rank Note: on STM32F1 devices, channel rank position in JSQR register is depending on total number of ranks selected into injected sequencer (ranks sequence starting from 4-JL)
| _CHANNELNB_,: | Channel number. |
| _RANKNB_,: | Rank number. |
| _JSQR_JL_,: | Sequence length. |
| None |
Definition at line 730 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADCEx_InjectedConfigChannel().
| #define ADC_SMPR1 | ( | _SAMPLETIME_, | |
| _CHANNELNB_ | |||
| ) | ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10))) |
Set the ADC's sample time for channel numbers between 10 and 18.
| _SAMPLETIME_,: | Sample time parameter. |
| _CHANNELNB_,: | Channel number. |
| None |
Definition at line 673 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().
| #define ADC_SMPR2 | ( | _SAMPLETIME_, | |
| _CHANNELNB_ | |||
| ) | ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_))) |
Set the ADC's sample time for channel numbers between 0 and 9.
| _SAMPLETIME_,: | Sample time parameter. |
| _CHANNELNB_,: | Channel number. |
| None |
Definition at line 682 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().
| #define ADC_SQR1_L_SHIFT | ( | _NbrOfConversion_ | ) | (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos) |
Set ADC number of conversions into regular channel sequence length.
| _NbrOfConversion_,: | Regular channel sequence length |
| None |
Definition at line 664 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_Init().
| #define ADC_SQR1_RK | ( | _CHANNELNB_, | |
| _RANKNB_ | |||
| ) | ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13))) |
Set the selected regular channel rank for rank between 13 and 16.
| _CHANNELNB_,: | Channel number. |
| _RANKNB_,: | Rank number. |
| None |
Definition at line 709 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_ConfigChannel().
| #define ADC_SQR2_RK | ( | _CHANNELNB_, | |
| _RANKNB_ | |||
| ) | ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7))) |
Set the selected regular channel rank for rank between 7 and 12.
| _CHANNELNB_,: | Channel number. |
| _RANKNB_,: | Rank number. |
| None |
Definition at line 700 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_ConfigChannel().
| #define ADC_SQR3_RK | ( | _CHANNELNB_, | |
| _RANKNB_ | |||
| ) | ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1))) |
Set the selected regular channel rank for rank between 1 and 6.
| _CHANNELNB_,: | Channel number. |
| _RANKNB_,: | Rank number. |
| None |
Definition at line 691 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_ConfigChannel().
| #define ADC_STATE_CLR_SET MODIFY_REG |
Simultaneously clears and sets specific bits of the handle State.
| None |
Definition at line 649 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().
| #define IS_ADC_ANALOG_WATCHDOG_MODE | ( | WATCHDOG | ) |
(((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
Definition at line 842 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_AnalogWDGConfig().
| #define IS_ADC_CHANNEL | ( | CHANNEL | ) |
(((CHANNEL) == ADC_CHANNEL_0) || \ ((CHANNEL) == ADC_CHANNEL_1) || \ ((CHANNEL) == ADC_CHANNEL_2) || \ ((CHANNEL) == ADC_CHANNEL_3) || \ ((CHANNEL) == ADC_CHANNEL_4) || \ ((CHANNEL) == ADC_CHANNEL_5) || \ ((CHANNEL) == ADC_CHANNEL_6) || \ ((CHANNEL) == ADC_CHANNEL_7) || \ ((CHANNEL) == ADC_CHANNEL_8) || \ ((CHANNEL) == ADC_CHANNEL_9) || \ ((CHANNEL) == ADC_CHANNEL_10) || \ ((CHANNEL) == ADC_CHANNEL_11) || \ ((CHANNEL) == ADC_CHANNEL_12) || \ ((CHANNEL) == ADC_CHANNEL_13) || \ ((CHANNEL) == ADC_CHANNEL_14) || \ ((CHANNEL) == ADC_CHANNEL_15) || \ ((CHANNEL) == ADC_CHANNEL_16) || \ ((CHANNEL) == ADC_CHANNEL_17) )
Definition at line 797 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().
| #define IS_ADC_CONVERSION_GROUP | ( | CONVERSION | ) |
(((CONVERSION) == ADC_REGULAR_GROUP) || \ ((CONVERSION) == ADC_INJECTED_GROUP) || \ ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
Definition at line 850 of file stm32f1xx_hal_adc.h.
| #define IS_ADC_DATA_ALIGN | ( | ALIGN | ) |
(((ALIGN) == ADC_DATAALIGN_RIGHT) || \ ((ALIGN) == ADC_DATAALIGN_LEFT) )
Definition at line 788 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_Init().
| #define IS_ADC_EVENT_TYPE | ( | EVENT | ) | ((EVENT) == ADC_AWD_EVENT) |
Definition at line 854 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_PollForEvent().
| #define IS_ADC_EXTTRIG_EDGE | ( | EDGE | ) |
(((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
Definition at line 794 of file stm32f1xx_hal_adc.h.
| #define IS_ADC_REGULAR_RANK | ( | CHANNEL | ) |
(((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_10) || \ ((CHANNEL) == ADC_REGULAR_RANK_11) || \ ((CHANNEL) == ADC_REGULAR_RANK_12) || \ ((CHANNEL) == ADC_REGULAR_RANK_13) || \ ((CHANNEL) == ADC_REGULAR_RANK_14) || \ ((CHANNEL) == ADC_REGULAR_RANK_15) || \ ((CHANNEL) == ADC_REGULAR_RANK_16) )
Definition at line 825 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_ConfigChannel().
| #define IS_ADC_SAMPLE_TIME | ( | TIME | ) |
(((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
Definition at line 816 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().
| #define IS_ADC_SCAN_MODE | ( | SCAN_MODE | ) |
(((SCAN_MODE) == ADC_SCAN_DISABLE) || \ ((SCAN_MODE) == ADC_SCAN_ENABLE) )
Definition at line 791 of file stm32f1xx_hal_adc.h.
Referenced by HAL_ADC_Init().
1.7.6.1