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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_adc.h 00004 * @author MCD Application Team 00005 * @brief Header file containing functions prototypes of ADC HAL library. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * 00010 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00011 * All rights reserved.</center></h2> 00012 * 00013 * This software component is licensed by ST under BSD 3-Clause license, 00014 * the "License"; You may not use this file except in compliance with the 00015 * License. You may obtain a copy of the License at: 00016 * opensource.org/licenses/BSD-3-Clause 00017 * 00018 ****************************************************************************** 00019 */ 00020 00021 /* Define to prevent recursive inclusion -------------------------------------*/ 00022 #ifndef __STM32F1xx_HAL_ADC_H 00023 #define __STM32F1xx_HAL_ADC_H 00024 00025 #ifdef __cplusplus 00026 extern "C" { 00027 #endif 00028 00029 /* Includes ------------------------------------------------------------------*/ 00030 #include "stm32f1xx_hal_def.h" 00031 00032 /* Include low level driver */ 00033 #include "stm32f1xx_ll_adc.h" 00034 00035 /** @addtogroup STM32F1xx_HAL_Driver 00036 * @{ 00037 */ 00038 00039 /** @addtogroup ADC 00040 * @{ 00041 */ 00042 00043 /* Exported types ------------------------------------------------------------*/ 00044 /** @defgroup ADC_Exported_Types ADC Exported Types 00045 * @{ 00046 */ 00047 00048 /** 00049 * @brief Structure definition of ADC and regular group initialization 00050 * @note Parameters of this structure are shared within 2 scopes: 00051 * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode. 00052 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. 00053 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 00054 * ADC can be either disabled or enabled without conversion on going on regular group. 00055 */ 00056 typedef struct 00057 { 00058 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) 00059 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). 00060 This parameter can be a value of @ref ADC_Data_align */ 00061 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. 00062 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 00063 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 00064 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 00065 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). 00066 Scan direction is upward: from rank1 to rank 'n'. 00067 This parameter can be a value of @ref ADC_Scan_mode 00068 Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1) 00069 or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the 00070 the last conversion of the sequence. All previous conversions would be overwritten by the last one. 00071 Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ 00072 FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 00073 after the selected trigger occurred (software start or external trigger). 00074 This parameter can be set to ENABLE or DISABLE. */ 00075 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 00076 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 00077 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ 00078 FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 00079 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 00080 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 00081 This parameter can be set to ENABLE or DISABLE. */ 00082 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. 00083 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 00084 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 00085 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 00086 If set to ADC_SOFTWARE_START, external triggers are disabled. 00087 If set to external trigger source, triggering is on event rising edge. 00088 This parameter can be a value of @ref ADC_External_trigger_source_Regular */ 00089 }ADC_InitTypeDef; 00090 00091 /** 00092 * @brief Structure definition of ADC channel for regular group 00093 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 00094 * ADC can be either disabled or enabled without conversion on going on regular group. 00095 */ 00096 typedef struct 00097 { 00098 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 00099 This parameter can be a value of @ref ADC_channels 00100 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. 00101 Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) 00102 Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. 00103 It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. 00104 Refer to errata sheet of these devices for more details. */ 00105 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer 00106 This parameter can be a value of @ref ADC_regular_rank 00107 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ 00108 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 00109 Unit: ADC clock cycles 00110 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). 00111 This parameter can be a value of @ref ADC_sampling_times 00112 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 00113 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 00114 Note: In case of usage of internal measurement channels (VrefInt/TempSensor), 00115 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 00116 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ 00117 }ADC_ChannelConfTypeDef; 00118 00119 /** 00120 * @brief ADC Configuration analog watchdog definition 00121 * @note The setting of these parameters with function is conditioned to ADC state. 00122 * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. 00123 */ 00124 typedef struct 00125 { 00126 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. 00127 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 00128 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. 00129 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) 00130 This parameter can be a value of @ref ADC_channels. */ 00131 FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. 00132 This parameter can be set to ENABLE or DISABLE */ 00133 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 00134 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ 00135 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 00136 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ 00137 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ 00138 }ADC_AnalogWDGConfTypeDef; 00139 00140 /** 00141 * @brief HAL ADC state machine: ADC states definition (bitfields) 00142 */ 00143 /* States of ADC global scope */ 00144 #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ 00145 #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ 00146 #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ 00147 #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ 00148 00149 /* States of ADC errors */ 00150 #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ 00151 #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ 00152 #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ 00153 00154 /* States of ADC group regular */ 00155 #define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, 00156 external trigger, low power auto power-on, multimode ADC master control) */ 00157 #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ 00158 #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */ 00159 #define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */ 00160 00161 /* States of ADC group injected */ 00162 #define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, 00163 external trigger, low power auto power-on, multimode ADC master control) */ 00164 #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ 00165 #define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ 00166 00167 /* States of ADC analog watchdogs */ 00168 #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ 00169 #define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */ 00170 #define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */ 00171 00172 /* States of ADC multi-mode */ 00173 #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */ 00174 00175 00176 /** 00177 * @brief ADC handle Structure definition 00178 */ 00179 typedef struct __ADC_HandleTypeDef 00180 { 00181 ADC_TypeDef *Instance; /*!< Register base address */ 00182 00183 ADC_InitTypeDef Init; /*!< ADC required parameters */ 00184 00185 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 00186 00187 HAL_LockTypeDef Lock; /*!< ADC locking object */ 00188 00189 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 00190 00191 __IO uint32_t ErrorCode; /*!< ADC Error code */ 00192 00193 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00194 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 00195 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 00196 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 00197 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 00198 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ /*!< ADC end of sampling callback */ 00199 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 00200 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 00201 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00202 }ADC_HandleTypeDef; 00203 00204 00205 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00206 /** 00207 * @brief HAL ADC Callback ID enumeration definition 00208 */ 00209 typedef enum 00210 { 00211 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 00212 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 00213 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 00214 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 00215 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 00216 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 00217 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 00218 } HAL_ADC_CallbackIDTypeDef; 00219 00220 /** 00221 * @brief HAL ADC Callback pointer definition 00222 */ 00223 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 00224 00225 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00226 00227 /** 00228 * @} 00229 */ 00230 00231 00232 00233 /* Exported constants --------------------------------------------------------*/ 00234 00235 /** @defgroup ADC_Exported_Constants ADC Exported Constants 00236 * @{ 00237 */ 00238 00239 /** @defgroup ADC_Error_Code ADC Error Code 00240 * @{ 00241 */ 00242 #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ 00243 #define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, 00244 enable/disable, erroneous state */ 00245 #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ 00246 #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ 00247 00248 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00249 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 00250 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00251 /** 00252 * @} 00253 */ 00254 00255 00256 /** @defgroup ADC_Data_align ADC data alignment 00257 * @{ 00258 */ 00259 #define ADC_DATAALIGN_RIGHT 0x00000000U 00260 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) 00261 /** 00262 * @} 00263 */ 00264 00265 /** @defgroup ADC_Scan_mode ADC scan mode 00266 * @{ 00267 */ 00268 /* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */ 00269 /* compatibility with other STM32 devices having a sequencer with */ 00270 /* additional options. */ 00271 #define ADC_SCAN_DISABLE 0x00000000U 00272 #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) 00273 /** 00274 * @} 00275 */ 00276 00277 /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group 00278 * @{ 00279 */ 00280 #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U 00281 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) 00282 /** 00283 * @} 00284 */ 00285 00286 /** @defgroup ADC_channels ADC channels 00287 * @{ 00288 */ 00289 /* Note: Depending on devices, some channels may not be available on package */ 00290 /* pins. Refer to device datasheet for channels availability. */ 00291 #define ADC_CHANNEL_0 0x00000000U 00292 #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0)) 00293 #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 )) 00294 #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) 00295 #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 )) 00296 #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) 00297 #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) 00298 #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) 00299 #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 )) 00300 #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) 00301 #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 )) 00302 #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) 00303 #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 )) 00304 #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) 00305 #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) 00306 #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) 00307 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 )) 00308 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) 00309 00310 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */ 00311 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */ 00312 /** 00313 * @} 00314 */ 00315 00316 /** @defgroup ADC_sampling_times ADC sampling times 00317 * @{ 00318 */ 00319 #define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ 00320 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */ 00321 #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */ 00322 #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ 00323 #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */ 00324 #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ 00325 #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */ 00326 #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */ 00327 /** 00328 * @} 00329 */ 00330 00331 /** @defgroup ADC_regular_rank ADC rank into regular group 00332 * @{ 00333 */ 00334 #define ADC_REGULAR_RANK_1 0x00000001U 00335 #define ADC_REGULAR_RANK_2 0x00000002U 00336 #define ADC_REGULAR_RANK_3 0x00000003U 00337 #define ADC_REGULAR_RANK_4 0x00000004U 00338 #define ADC_REGULAR_RANK_5 0x00000005U 00339 #define ADC_REGULAR_RANK_6 0x00000006U 00340 #define ADC_REGULAR_RANK_7 0x00000007U 00341 #define ADC_REGULAR_RANK_8 0x00000008U 00342 #define ADC_REGULAR_RANK_9 0x00000009U 00343 #define ADC_REGULAR_RANK_10 0x0000000AU 00344 #define ADC_REGULAR_RANK_11 0x0000000BU 00345 #define ADC_REGULAR_RANK_12 0x0000000CU 00346 #define ADC_REGULAR_RANK_13 0x0000000DU 00347 #define ADC_REGULAR_RANK_14 0x0000000EU 00348 #define ADC_REGULAR_RANK_15 0x0000000FU 00349 #define ADC_REGULAR_RANK_16 0x00000010U 00350 /** 00351 * @} 00352 */ 00353 00354 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode 00355 * @{ 00356 */ 00357 #define ADC_ANALOGWATCHDOG_NONE 0x00000000U 00358 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) 00359 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) 00360 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 00361 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) 00362 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) 00363 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 00364 /** 00365 * @} 00366 */ 00367 00368 /** @defgroup ADC_conversion_group ADC conversion group 00369 * @{ 00370 */ 00371 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) 00372 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) 00373 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) 00374 /** 00375 * @} 00376 */ 00377 00378 /** @defgroup ADC_Event_type ADC Event type 00379 * @{ 00380 */ 00381 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ 00382 00383 #define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */ 00384 /** 00385 * @} 00386 */ 00387 00388 /** @defgroup ADC_interrupts_definition ADC interrupts definition 00389 * @{ 00390 */ 00391 #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ 00392 #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ 00393 #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ 00394 /** 00395 * @} 00396 */ 00397 00398 /** @defgroup ADC_flags_definition ADC flags definition 00399 * @{ 00400 */ 00401 #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ 00402 #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ 00403 #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ 00404 #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ 00405 #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ 00406 /** 00407 * @} 00408 */ 00409 00410 00411 /** 00412 * @} 00413 */ 00414 00415 /* Private constants ---------------------------------------------------------*/ 00416 00417 /** @addtogroup ADC_Private_Constants ADC Private Constants 00418 * @{ 00419 */ 00420 00421 /** @defgroup ADC_conversion_cycles ADC conversion cycles 00422 * @{ 00423 */ 00424 /* ADC conversion cycles (unit: ADC clock cycles) */ 00425 /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ 00426 /* resolution 12 bits) */ 00427 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U 00428 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U 00429 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U 00430 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U 00431 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U 00432 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U 00433 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U 00434 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U 00435 /** 00436 * @} 00437 */ 00438 00439 /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels 00440 * @{ 00441 */ 00442 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ 00443 (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \ 00444 ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \ 00445 ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2) 00446 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ 00447 (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \ 00448 ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 ) 00449 00450 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ 00451 (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \ 00452 ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \ 00453 ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1) 00454 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ 00455 (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \ 00456 ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 ) 00457 00458 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ 00459 (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \ 00460 ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \ 00461 ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0) 00462 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ 00463 (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ 00464 ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 ) 00465 00466 #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U 00467 #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) 00468 #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) 00469 #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) 00470 #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) 00471 #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) 00472 #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) 00473 #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) 00474 00475 #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U 00476 #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) 00477 #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) 00478 #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) 00479 #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) 00480 #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) 00481 #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) 00482 #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) 00483 /** 00484 * @} 00485 */ 00486 00487 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ 00488 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD ) 00489 00490 /** 00491 * @} 00492 */ 00493 00494 00495 /* Exported macro ------------------------------------------------------------*/ 00496 00497 /** @defgroup ADC_Exported_Macros ADC Exported Macros 00498 * @{ 00499 */ 00500 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 00501 /* final user. */ 00502 00503 /** 00504 * @brief Enable the ADC peripheral 00505 * @note ADC enable requires a delay for ADC stabilization time 00506 * (refer to device datasheet, parameter tSTAB) 00507 * @note On STM32F1, if ADC is already enabled this macro trigs a conversion 00508 * SW start on regular group. 00509 * @param __HANDLE__: ADC handle 00510 * @retval None 00511 */ 00512 #define __HAL_ADC_ENABLE(__HANDLE__) \ 00513 (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) 00514 00515 /** 00516 * @brief Disable the ADC peripheral 00517 * @param __HANDLE__: ADC handle 00518 * @retval None 00519 */ 00520 #define __HAL_ADC_DISABLE(__HANDLE__) \ 00521 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) 00522 00523 /** @brief Enable the ADC end of conversion interrupt. 00524 * @param __HANDLE__: ADC handle 00525 * @param __INTERRUPT__: ADC Interrupt 00526 * This parameter can be any combination of the following values: 00527 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 00528 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 00529 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 00530 * @retval None 00531 */ 00532 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 00533 (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 00534 00535 /** @brief Disable the ADC end of conversion interrupt. 00536 * @param __HANDLE__: ADC handle 00537 * @param __INTERRUPT__: ADC Interrupt 00538 * This parameter can be any combination of the following values: 00539 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 00540 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 00541 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 00542 * @retval None 00543 */ 00544 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 00545 (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 00546 00547 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 00548 * @param __HANDLE__: ADC handle 00549 * @param __INTERRUPT__: ADC interrupt source to check 00550 * This parameter can be any combination of the following values: 00551 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 00552 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 00553 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 00554 * @retval None 00555 */ 00556 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 00557 (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) 00558 00559 /** @brief Get the selected ADC's flag status. 00560 * @param __HANDLE__: ADC handle 00561 * @param __FLAG__: ADC flag 00562 * This parameter can be any combination of the following values: 00563 * @arg ADC_FLAG_STRT: ADC Regular group start flag 00564 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag 00565 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 00566 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag 00567 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 00568 * @retval None 00569 */ 00570 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 00571 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 00572 00573 /** @brief Clear the ADC's pending flags 00574 * @param __HANDLE__: ADC handle 00575 * @param __FLAG__: ADC flag 00576 * This parameter can be any combination of the following values: 00577 * @arg ADC_FLAG_STRT: ADC Regular group start flag 00578 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag 00579 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 00580 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag 00581 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 00582 * @retval None 00583 */ 00584 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 00585 (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__))) 00586 00587 /** @brief Reset ADC handle state 00588 * @param __HANDLE__: ADC handle 00589 * @retval None 00590 */ 00591 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00592 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 00593 do{ \ 00594 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 00595 (__HANDLE__)->MspInitCallback = NULL; \ 00596 (__HANDLE__)->MspDeInitCallback = NULL; \ 00597 } while(0) 00598 #else 00599 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 00600 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 00601 #endif 00602 00603 /** 00604 * @} 00605 */ 00606 00607 /* Private macro ------------------------------------------------------------*/ 00608 00609 /** @defgroup ADC_Private_Macros ADC Private Macros 00610 * @{ 00611 */ 00612 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 00613 /* code of final user. */ 00614 00615 /** 00616 * @brief Verification of ADC state: enabled or disabled 00617 * @param __HANDLE__: ADC handle 00618 * @retval SET (ADC enabled) or RESET (ADC disabled) 00619 */ 00620 #define ADC_IS_ENABLE(__HANDLE__) \ 00621 ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \ 00622 ) ? SET : RESET) 00623 00624 /** 00625 * @brief Test if conversion trigger of regular group is software start 00626 * or external trigger. 00627 * @param __HANDLE__: ADC handle 00628 * @retval SET (software start) or RESET (external trigger) 00629 */ 00630 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 00631 (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) 00632 00633 /** 00634 * @brief Test if conversion trigger of injected group is software start 00635 * or external trigger. 00636 * @param __HANDLE__: ADC handle 00637 * @retval SET (software start) or RESET (external trigger) 00638 */ 00639 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 00640 (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) 00641 00642 /** 00643 * @brief Simultaneously clears and sets specific bits of the handle State 00644 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 00645 * the first parameter is the ADC handle State, the second parameter is the 00646 * bit field to clear, the third and last parameter is the bit field to set. 00647 * @retval None 00648 */ 00649 #define ADC_STATE_CLR_SET MODIFY_REG 00650 00651 /** 00652 * @brief Clear ADC error code (set it to error code: "no error") 00653 * @param __HANDLE__: ADC handle 00654 * @retval None 00655 */ 00656 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 00657 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 00658 00659 /** 00660 * @brief Set ADC number of conversions into regular channel sequence length. 00661 * @param _NbrOfConversion_: Regular channel sequence length 00662 * @retval None 00663 */ 00664 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ 00665 (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos) 00666 00667 /** 00668 * @brief Set the ADC's sample time for channel numbers between 10 and 18. 00669 * @param _SAMPLETIME_: Sample time parameter. 00670 * @param _CHANNELNB_: Channel number. 00671 * @retval None 00672 */ 00673 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ 00674 ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10))) 00675 00676 /** 00677 * @brief Set the ADC's sample time for channel numbers between 0 and 9. 00678 * @param _SAMPLETIME_: Sample time parameter. 00679 * @param _CHANNELNB_: Channel number. 00680 * @retval None 00681 */ 00682 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ 00683 ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_))) 00684 00685 /** 00686 * @brief Set the selected regular channel rank for rank between 1 and 6. 00687 * @param _CHANNELNB_: Channel number. 00688 * @param _RANKNB_: Rank number. 00689 * @retval None 00690 */ 00691 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ 00692 ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1))) 00693 00694 /** 00695 * @brief Set the selected regular channel rank for rank between 7 and 12. 00696 * @param _CHANNELNB_: Channel number. 00697 * @param _RANKNB_: Rank number. 00698 * @retval None 00699 */ 00700 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ 00701 ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7))) 00702 00703 /** 00704 * @brief Set the selected regular channel rank for rank between 13 and 16. 00705 * @param _CHANNELNB_: Channel number. 00706 * @param _RANKNB_: Rank number. 00707 * @retval None 00708 */ 00709 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ 00710 ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13))) 00711 00712 /** 00713 * @brief Set the injected sequence length. 00714 * @param _JSQR_JL_: Sequence length. 00715 * @retval None 00716 */ 00717 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ 00718 (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos) 00719 00720 /** 00721 * @brief Set the selected injected channel rank 00722 * Note: on STM32F1 devices, channel rank position in JSQR register 00723 * is depending on total number of ranks selected into 00724 * injected sequencer (ranks sequence starting from 4-JL) 00725 * @param _CHANNELNB_: Channel number. 00726 * @param _RANKNB_: Rank number. 00727 * @param _JSQR_JL_: Sequence length. 00728 * @retval None 00729 */ 00730 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ 00731 ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) 00732 00733 /** 00734 * @brief Enable ADC continuous conversion mode. 00735 * @param _CONTINUOUS_MODE_: Continuous mode. 00736 * @retval None 00737 */ 00738 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ 00739 ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos) 00740 00741 /** 00742 * @brief Configures the number of discontinuous conversions for the regular group channels. 00743 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. 00744 * @retval None 00745 */ 00746 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ 00747 (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos) 00748 00749 /** 00750 * @brief Enable ADC scan mode to convert multiple ranks with sequencer. 00751 * @param _SCAN_MODE_: Scan conversion mode. 00752 * @retval None 00753 */ 00754 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ 00755 /* is equivalent to ADC_SCAN_ENABLE. */ 00756 #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ 00757 (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ 00758 )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ 00759 ) 00760 00761 /** 00762 * @brief Get the maximum ADC conversion cycles on all channels. 00763 * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) 00764 * Approximation of sampling time within 4 ranges, returns the highest value: 00765 * below 7.5 cycles {1.5 cycle; 7.5 cycles}, 00766 * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} 00767 * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} 00768 * equal to 239.5 cycles 00769 * Unit: ADC clock cycles 00770 * @param __HANDLE__: ADC handle 00771 * @retval ADC conversion cycles on all channels 00772 */ 00773 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ 00774 (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ 00775 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ 00776 \ 00777 (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ 00778 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ 00779 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ 00780 : \ 00781 ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ 00782 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ 00783 ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ 00784 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \ 00785 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \ 00786 ) 00787 00788 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 00789 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 00790 00791 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ 00792 ((SCAN_MODE) == ADC_SCAN_ENABLE) ) 00793 00794 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 00795 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) ) 00796 00797 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 00798 ((CHANNEL) == ADC_CHANNEL_1) || \ 00799 ((CHANNEL) == ADC_CHANNEL_2) || \ 00800 ((CHANNEL) == ADC_CHANNEL_3) || \ 00801 ((CHANNEL) == ADC_CHANNEL_4) || \ 00802 ((CHANNEL) == ADC_CHANNEL_5) || \ 00803 ((CHANNEL) == ADC_CHANNEL_6) || \ 00804 ((CHANNEL) == ADC_CHANNEL_7) || \ 00805 ((CHANNEL) == ADC_CHANNEL_8) || \ 00806 ((CHANNEL) == ADC_CHANNEL_9) || \ 00807 ((CHANNEL) == ADC_CHANNEL_10) || \ 00808 ((CHANNEL) == ADC_CHANNEL_11) || \ 00809 ((CHANNEL) == ADC_CHANNEL_12) || \ 00810 ((CHANNEL) == ADC_CHANNEL_13) || \ 00811 ((CHANNEL) == ADC_CHANNEL_14) || \ 00812 ((CHANNEL) == ADC_CHANNEL_15) || \ 00813 ((CHANNEL) == ADC_CHANNEL_16) || \ 00814 ((CHANNEL) == ADC_CHANNEL_17) ) 00815 00816 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ 00817 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ 00818 ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ 00819 ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ 00820 ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ 00821 ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ 00822 ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ 00823 ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) 00824 00825 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ 00826 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ 00827 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ 00828 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ 00829 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ 00830 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ 00831 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ 00832 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ 00833 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ 00834 ((CHANNEL) == ADC_REGULAR_RANK_10) || \ 00835 ((CHANNEL) == ADC_REGULAR_RANK_11) || \ 00836 ((CHANNEL) == ADC_REGULAR_RANK_12) || \ 00837 ((CHANNEL) == ADC_REGULAR_RANK_13) || \ 00838 ((CHANNEL) == ADC_REGULAR_RANK_14) || \ 00839 ((CHANNEL) == ADC_REGULAR_RANK_15) || \ 00840 ((CHANNEL) == ADC_REGULAR_RANK_16) ) 00841 00842 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ 00843 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 00844 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 00845 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 00846 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 00847 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 00848 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 00849 00850 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ 00851 ((CONVERSION) == ADC_INJECTED_GROUP) || \ 00852 ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) 00853 00854 #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) 00855 00856 00857 /** @defgroup ADC_range_verification ADC range verification 00858 * For a unique ADC resolution: 12 bits 00859 * @{ 00860 */ 00861 #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU) 00862 /** 00863 * @} 00864 */ 00865 00866 /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification 00867 * @{ 00868 */ 00869 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) 00870 /** 00871 * @} 00872 */ 00873 00874 /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification 00875 * @{ 00876 */ 00877 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) 00878 /** 00879 * @} 00880 */ 00881 00882 /** 00883 * @} 00884 */ 00885 00886 /* Include ADC HAL Extension module */ 00887 #include "stm32f1xx_hal_adc_ex.h" 00888 00889 /* Exported functions --------------------------------------------------------*/ 00890 /** @addtogroup ADC_Exported_Functions 00891 * @{ 00892 */ 00893 00894 /** @addtogroup ADC_Exported_Functions_Group1 00895 * @{ 00896 */ 00897 00898 00899 /* Initialization and de-initialization functions **********************************/ 00900 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 00901 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 00902 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 00903 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 00904 00905 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00906 /* Callbacks Register/UnRegister functions ***********************************/ 00907 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); 00908 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 00909 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00910 00911 /** 00912 * @} 00913 */ 00914 00915 /* IO operation functions *****************************************************/ 00916 00917 /** @addtogroup ADC_Exported_Functions_Group2 00918 * @{ 00919 */ 00920 00921 00922 /* Blocking mode: Polling */ 00923 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 00924 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 00925 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 00926 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 00927 00928 /* Non-blocking mode: Interruption */ 00929 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 00930 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 00931 00932 /* Non-blocking mode: DMA */ 00933 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 00934 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 00935 00936 /* ADC retrieve conversion value intended to be used with polling or interruption */ 00937 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 00938 00939 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 00940 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 00941 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 00942 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 00943 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 00944 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 00945 /** 00946 * @} 00947 */ 00948 00949 00950 /* Peripheral Control functions ***********************************************/ 00951 /** @addtogroup ADC_Exported_Functions_Group3 00952 * @{ 00953 */ 00954 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 00955 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 00956 /** 00957 * @} 00958 */ 00959 00960 00961 /* Peripheral State functions *************************************************/ 00962 /** @addtogroup ADC_Exported_Functions_Group4 00963 * @{ 00964 */ 00965 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 00966 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 00967 /** 00968 * @} 00969 */ 00970 00971 00972 /** 00973 * @} 00974 */ 00975 00976 00977 /* Internal HAL driver functions **********************************************/ 00978 /** @addtogroup ADC_Private_Functions 00979 * @{ 00980 */ 00981 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); 00982 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); 00983 void ADC_StabilizationTime(uint32_t DelayUs); 00984 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 00985 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 00986 void ADC_DMAError(DMA_HandleTypeDef *hdma); 00987 /** 00988 * @} 00989 */ 00990 00991 00992 /** 00993 * @} 00994 */ 00995 00996 /** 00997 * @} 00998 */ 00999 01000 #ifdef __cplusplus 01001 } 01002 #endif 01003 01004 01005 #endif /* __STM32F1xx_HAL_ADC_H */ 01006 01007 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1